Description
The ICX087AK is an interline CCD solid-state image
sensor suitable for PAL color video cameras. High
sensitivity is achieved through the use of Ye, Cy, Mg,
and G complementary color mosaic filters and through
the adoption of HAD (Hole-Accumulation Diode)
sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
The package is a 10mm-square 14-pin DIP (Plastic).
Features
High sensitivity and low dark current
Horizontal register:
3.3 to 5.0V drive
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
Low smear
Excellent antiblooming characteristics
Continuous variable-speed shutter
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Device Structure
Interline CCD image sensor
Image size:
Diagonal 4.5mm (Type 1/4)
Number of effective pixels:
500 (H)
582 (V) approx. 290K pixels
Total number of pixels:
537 (H)
597 (V) approx. 320K pixels
Chip size:
4.47mm (H)
3.80mm (V)
Unit cell size:
7.3m (H)
4.7m (V)
Optical black:
Horizontal (H) direction: Front 7 pixels, rear 30 pixels
Vertical (V) direction:
Front 14 pixels, rear 1 pixel
Number of dummy bits:
Horizontal 16
Vertical 1 (even fields only)
Substrate material:
Silicon
1
ICX087AK
E94823D99
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Optical black position
(Top View)
14 pin DIP (Plastic)
Pin 1
V
7
30
1
14
Pin 8
H
2
ICX087AK
1
5
6
7
9
10
11
13
Note)
Note) : Photo sensor
V
O
U
T
G
N
D
V
1
V
2
V
3
V
4
V
D
D
G
N
D
S
U
B
V
L
R
G
H
1
H
2
Horizontal Register
2
3
4
N
C
12
Cy
Mg
14
Ye
Cy
Mg
Ye
G
G
8
V
e
r
t
i
c
a
l
R
e
g
i
s
t
e
r
Cy
Mg
Ye
Cy
Mg
Ye
G
G
Cy
Mg
Ye
Cy
Mg
Ye
G
G
Substrate clock
SUB GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
H
1
, H
2
GND
H
1
, H
2
SUB
V
L
SUB
V
1
, V
3
, V
DD
, V
OUT
V
L
RG GND
V
2
, V
4
, H
1
, H
2
, GND V
L
Storage temperature
Operating temperature
Block Diagram and Pin Configuration
(Top View)
Pin No.
1
2
3
4
5
6
7
V
4
V
3
V
2
V
1
NC
GND
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
8
9
10
11
12
13
14
V
DD
GND
SUB
V
L
RG
H
1
H
2
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
Description
Pin No.
Description
Pin Description
Absolute Maximum Ratings
0.3 to +40
0.3 to +18
30 to +9
15 to +16
to +10
to +15
to +16
16 to +16
10 to +15
55 to +10
65 to +0.3
0.3 to +27.5
0.3 to +20.5
0.3 to +17.5
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
V
DD
, V
OUT
GND
V
DD
, V
OUT
SUB
V
1
, V
2
, V
3
, V
4
GND
V
1
, V
2
, V
3
, V
4
SUB
Item
Ratings
Unit
Remarks
1
+24V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Symbol
3
ICX087AK
Clock Voltage Conditions
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGH
V
SUB
14.55
0.05
0.2
8.0
6.8
0.25
0.25
3.0
0.05
4.5
V
DD
+
0.3
21.5
15.0
0
0
7.5
7.5
5.0
0
5.0
V
DD
+
0.6
22.5
15.45
0.05
0.05
7.0
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.8
V
DD
+
0.9
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01F
capacitance
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
V
DD
V
L
SUB
14.55
15.0
1
2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
DC Characteristics
Item
Supply current
I
DD
4
6
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
4
ICX087AK
Item
Capacitance between vertical transfer
clock and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
, C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
, R
4
R
GND
R
H
R
RG
680
820
180
150
62
30
18
3
190
33
15
24
40
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
R
RG
RG
C
RG
Reset gate clock equivalent circuit
Clock Equivalent Circuit Constant
5
ICX087AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
3
V
2
V
4
V
VHH
V
VH
V
VHL
V
VHH
V
VHL
V
VH1
V
VL1
V
VLH
V
VLL
V
VL
V
VHH
V
VH3
V
VHL
V
VH
V
VHH
V
VHL
V
VL3
V
VL
V
VLL
V
VLH
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VHH
V
VHL
V
VH4
V
VHL
V
VH
V
VL
V
VLH
V
VLL
V
VL4
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
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