Description
The ICX204AL is a diagonal 6mm (Type 1/3)
interline CCD solid-state image sensor with a square
pixel array and 800K effective pixels. Progressive
scan allows all pixels' signals to be output
independently. Also, the adoption of high frame rate
readout mode supports 60 frames per second. This
chip features an electronic shutter with variable
charge-storage time which makes it possible to
realize full-frame still image without a mechanical
shutter. Further, high sensitivity and low dark current
are achieved through the adoption of HAD (Hole-
Accumulation Diode) sensors.
This chip is suitable for applications such as FA
cameras, two-dimensional bar-code reader, etc.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High horizontal and vertical resolution (both approx.
768TV-lines) still image without a mechanical shutter.
Supports high frame rate readout mode
(effective 256 lines output, 15MHz drive: 45 frame/s,
20MHz drive: 60 frame/s)
Square pixel
Horizontal drive frequency: Typ.: 15MHz, Max.: 20MHz
No voltage adjustments
(reset gate and substrate bias are not adjusted.)
High resolution, high sensitivity, low dark current
Low smear, excellent antiblooming characteristics
Continuous variable-speed shutter
Recommended range of exit pupil distance: 20 to 100mm
Device Structure
Interline CCD image sensor
Image size:
Diagonal 6mm (Type 1/3)
Total number of pixels:
1077 (H)
788 (V) approx. 850K pixels
Number of effective pixels:
1034 (H)
779 (V) approx. 800K pixels
Number of active pixels:
1024 (H)
768 (V) approx. 790K pixels (diagonal 5.952mm)
Chip size:
5.80mm (H)
4.92mm (V)
Unit cell size:
4.65m (H)
4.65m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 7 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 29
Vertical 1
Substrate material:
Silicon
Diagonal 6mm (Type 1/3) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
1
E98809A99
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX204AL
16 pin DIP (Plastic)
Pin 1
V
3
40
2
7
Pin 9
H
Optical black position
(Top View)
2
ICX204AL
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
V
3
V
2B
V
1
V
2A
GND
NC
NC
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
9
10
11
12
13
14
15
16
V
DD
GND
SUB
C
SUB
V
L
RG
H
1
H
2
Supply voltage
GND
Substrate clock
Substrate bias
1
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Pin Description
Note)
: Photo sensor
V
O
U
T
N
C
N
C
G
N
D
V
2
A
V
1
V
2
B
V
3
V
D
D
G
N
D
S
U
B
C
S
U
B
V
L
R
G
H
1
H
2
Horizontal register
V
e
r
t
i
c
a
l
r
e
g
i
s
t
e
r
Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Block Diagram and Pin Configuration
(Top View)
1
DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1F.
4
ICX204AL
Clock Voltage Conditions
Item
Readout clock voltage
V
VT
V
VH02A
V
VH1
, V
VH2A
,
V
VH2B
, V
VH3
V
VL1
, V
VL2A
,
V
VL2B
, V
VL3
V
1
, V
2A
,
V
2B
, V
3
| V
VL1
V
VL3
|
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGL
V
RGLm
V
SUB
14.55
0.05
0.2
8
7
3.0
0.05
3.0
21.55
15.0
0
0
7.5
7.5
3.3
0
3.3
22.5
15.45
0.05
0.05
7
8
0.1
0.9
1.3
1.0
0.9
3.6
0.05
3.6
0.4
0.5
23.45
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
V
VH
= V
VH02A
V
VL
= (V
VL1
+ V
VL3
)/2
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
V
DD
V
L
SUB
RG
14.55
15.0
1
2
2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
DC Characteristics
Item
Supply current
I
DD
5.5
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
5
ICX204AL
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock and
GND
C
V1
C
V2A
C
V2B
C
V3
C
V12A
C
V2B1
C
V2A3
C
V32B
C
V13
C
V2A2B
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
R
2A
R
2B
R
3
R
GND
R
H
1500
1800
2700
2200
390
680
560
1000
1800
33
18
43
3
390
91
68
62
30
43
10
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12A
V
2A
V
2B
V
3
C
V32B
C
V2A3
C
V2B1
C
V13
C
V1
C
V2A
C
V2B
C
V3
R
GND
R
2B
R
1
R
3
R
2A
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
C
V2A2B
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