ICX409AK
Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Cameras
Description
The ICX409AK is an interline CCD solid-state
image sensor suitable for PAL color video cameras
with a diagonal 6mm (Type 1/3) system. Compared
with the conventional product ICX059CK, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
This chip is suitable for applications such as surveillance
cameras, automotive cameras, etc.
Features
High sensitivity (+6dB compared with the ICX059CK)
Low smear (15dB compared with the ICX059CK)
High D range (+5dB compared with the ICX059CK)
High S/N
High resolution and low dark current
Excellent antiblooming characteristics
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Continuous variable-speed shutter
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
Reset gate:
5V drive
Horizontal register: 5V drive
Device Structure
Interline CCD image sensor
Image size:
Diagonal 6mm (Type 1/3)
Number of effective pixels: 752 (H)
582 (V) approx. 440K pixels
Total number of pixels:
795 (H)
596 (V) approx. 470K pixels
Chip size:
5.59mm (H)
4.68mm (V)
Unit cell size:
6.50m (H)
6.25m (V)
Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction
: Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
1
E00611B28
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Pin 1
V
3
40
2
12
Pin 9
H
Optical black position
(Top View)
16 pin DIP (Plastic)
Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-
Accumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony
Corporation.
2
ICX409AK
Block Diagram and
Pin Configuration
(Top View)
6
7
Note)
NC
V
1
V
2
V
3
V
4
V
DD
GND
SUB
V
L
RG
H
2
Horizontal Register
Vertical Register
2
3
4
GND
Cy
Cy
G
G
Cy
Mg
Ye
Ye
Mg
Mg
Ye
G
Cy
Cy
G
G
Cy
Mg
Ye
Ye
Mg
Mg
Ye
G
8
1
V
OUT
NC
10
11
12
14
9
16
13
15
NC
5
H
1
Note) : Photo sensor
Pin No.
1
2
3
4
5
6
7
8
V
4
V
3
V
2
V
1
GND
NC
NC
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
9
10
11
12
13
14
15
16
V
DD
GND
SUB
V
L
RG
NC
H
1
H
2
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
Description
Pin No.
Description
Pin Description
Symbol
Absolute Maximum Ratings
1
+24V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Against
SUB
Against GND
Against V
L
Between input clock
pins
Storage temperature
Operating temperature
40 to +8
50 to +15
50 to +0.3
40 to +0.3
0.3 to +20
10 to +18
10 to +6
0.3 to +28
0.3 to +15
to +15
6 to +6
14 to +14
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
V
DD
, V
OUT
,
RG
SUB
V
1
, V
3
SUB
V
2
, V
4
, V
L
SUB
H
1
, H
2
, GND
SUB
V
DD
, V
OUT
,
RG GND
V
1
, V
2
, V
3
, V
4
GND
H
1
, H
2
GND
V
1
, V
3
V
L
V
2
, V
4
, H
1
, H
2
, GND V
L
Voltage difference between vertical clock input pins
H
1
H
2
H
1
, H
2
V
4
Item
Ratings
Unit
Remarks
1
3
ICX409AK
Bias Conditions
Clock Voltage Conditions
DC Characteristics
Item
Supply current
I
DD
4
6
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
Item
Supply voltage
Protective transistor bias
Substrate clock
V
DD
V
L
SUB
14.55
15.0
1
2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item
Readout clock voltage
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGL
V
RGLm
V
RGH
V
SUB
14.55
0.05
0.2
8.0
6.3
0.25
0.25
4.75
0.05
4.5
V
DD
+0.3
21.0
15.0
0
0
7.0
7.0
5.0
0
5.0
V
DD
+0.6
22.0
15.45
0.05
0.05
6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
V
DD
+0.9
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
4
5
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.1F
capacitance
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
4
ICX409AK
R
H
R
H
H
2
H
1
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
R
RG
RG
C
RG
Reset gate clock equivalent circuit
Item
Capacitance between vertical transfer
clock and GND
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
3
R
2
, R
4
R
GND
R
H
R
RG
1500
1000
820
330
120
100
75
22
5
270
100
150
68
15
50
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol
Min.
Typ.
Max.
Unit
Remarks
Clock Equivalent Circuit Constant
5
ICX409AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II
II
100%
90%
10%
0%
V
VT
tr
twh
tf
M
0V
M
2
V
1
V
3
V
2
V
4
V
VHH
V
VH
V
VHL
V
VHH
V
VHL
V
VH1
V
VL1
V
VLH
V
VLL
V
VL
V
VHH
V
VH3
V
VHL
V
VH
V
VHH
V
VHL
V
VL3
V
VL
V
VLL
V
VLH
V
VHH
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VHH
V
VHL
V
VH4
V
VHL
V
VH
V
VL
V
VLH
V
VLL
V
VL4
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
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