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1
E01911
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operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX419AKB
16 pin DIP (Ceramic)
Description
The ICX419AKB is an interline CCD solid-state
image sensor suitable for PAL color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX039DNB, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. Also, this outline is miniaturized by using
original package. This chip is compatible with the
pins of the ICX039DNB and has the same drive
conditions.
Features
High sensitivity (+6.0dB compared with the ICX039DNB)
Low smear (5.0dB compared with the ICX039DNB)
High D range (+3.0dB compared with the ICX039DNB)
High S/N
High resolution and low dark current
Excellent antiblooming characteristics
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Continuous variable-speed shutter
Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
Horizontal register:
5V drive
Maximum package dimensions:
13.2mm
Device Structure
Interline CCD image sensor
Optical size:
Diagonal 8mm (Type 1/2)
Number of effective pixels: 752 (H)
582 (V) approx. 440K pixels
Total number of pixels:
795 (H)
596 (V) approx. 470K pixels
Chip size:
7.40mm (H)
5.95mm (V)
Unit cell size:
8.6m (H)
8.3m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
Diagonal 8mm (Type 1/2) CCD Image Sensor for PAL Color Video Cameras
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 9
40
3
2
ICX419AKB
Block Diagram and Pin Configuration
(Top View)
9
10
11
12
13
14
15
16
Note) : Photo sensor
NC
V
DSUB
NC
GND
RD
RG
H
1
H
2
8
7
6
5
4
3
2
1
V
OUT
V
DD
V
L
V
1
SUB
V
2
V
3
V
4
Note)
Horizontal Register
V
e
r
tical Register
Ye
Ye
Ye
Ye
Ye
Ye
G
Mg
G
G
Mg
G
Cy
Cy
Cy
Cy
Cy
Cy
Mg
G
Mg
Mg
G
Mg
Pin Description
Pin No.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
Description
V
4
V
3
V
2
SUB
V
1
V
L
V
DD
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
Vertical register transfer clock
Protective transistor bias
Output circuit supply voltage
Signal output
Symbol
Description
NC
NC
GND
RD
RG
V
DSUB
H
1
H
2
GND
Reset drain bias
Reset gate clock
Substrate bias circuit supply voltage
Horizontal register transfer clock
Horizontal register transfer clock
3
ICX419AKB
Absolute Maximum Ratings
Item
Substrate clock
SUB
GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
RG
GND
RG
SUB
V
L
SUB
Pins other than GND and
SUB
V
L
Storage temperature
Operating temperature
0.3 to +50
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +30
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
1
+27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
V
DD
, V
RD
, V
DSUB
, V
OUT
GND
V
DD
, V
RD
, V
DSUB
, V
OUT
SUB
V
1
, V
2
, V
3
, V
4
GND
V
1
, V
2
, V
3
, V
4
SUB
4
ICX419AKB
DC Characteristics
Output circuit supply current
Item
I
DD
Symbol
5.0
Min.
Unit
Remarks
Typ.
Max.
mA
10.0
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item
V
DD
V
RD
V
L
V
DSUB
SUB
Symbol
15.0
15.0
1
15.0
2
Min.
V
V
V
Unit
Remarks
Typ.
Max.
14.55
14.55
14.55
15.45
15.45
15.45
V
RD
= V
DD
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
3
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
4
Connect to GND or leave open.
5
The setting value of the substrate voltage (V
SUB
) is indicated on the back of the image sensor by a
special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is 3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
V
SUB
code -- one character indication
Code and optimal setting correspond to each other as follows.
Item
V
DD
V
RD
V
L
V
DSUB
V
SUB
V
SUB
Symbol
15.0
15.0
3
4
Min.
V
V
V
%
Unit
Remarks
Typ.
Max.
14.55
14.55
6.0
3
15.45
15.45
14.0
+3
V
RD
= V
DD
5
5
<Example> "L"
V
SUB
= 9.0V
V
SUB
code
Optimal setting
f
6.5
G
7.0
h
7.5
J
8.0
K
8.5
L
9.0
m
9.5
N
10.0
P
10.5
Q
11.0
S
12.0
U
13.0
V
13.5
W
14.0
R
11.5
T
12.5
E
6.0
5
ICX419AKB
Clock Voltage Conditions
1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
1
Substrate clock voltage
Item
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
| V
VH1
V
VH2
|
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RGL
V
RG
V
RGLH
V
RGLL
V
SUB
Symbol
14.55
0.05
0.2
9.6
8.3
0.25
0.25
4.75
0.05
4.5
23.0
Min.
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Remarks
Reset gate clock
voltage
Item
V
RGL
V
RG
Symbol
4
4
Waveform
diagram
Remarks
15.0
0
0
9.0
9.0
5.0
0
1
5.0
24.0
Typ.
15.45
0.05
0.05
8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
Max. Unit
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
0.2
8.5
Min.
0
9.0
Typ.
0.2
9.5
Max. Unit
V
Vp-p
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