1
E01506B41
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX419ALL
20 pin DIP (Cer-DIP)
Diagonal 8mm (Type 1/2) CCD Image Sensor for CCIR B/W Video Cameras
Description
The ICX419ALL is an interline CCD solid-state
image sensor suitable for CCIE B/W video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX039DLA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX039DLA and has the same drive conditions.
Features
High sensitivity (+5.0dB compared with the ICX039DLA)
Low smear (5.0dB compared with the ICX039DLA)
High D range (+3.0dB compared with the ICX039DLA)
High S/N
High resolution and low dark current
Excellent antiblooming characteristics
Continuous variable-speed shutter
Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
Horizontal register: 5V drive
Device Structure
Interline CCD image sensor
Optical size:
Diagonal 8mm (Type 1/2)
Number of effective pixels: 752 (H)
582 (V) approx. 440K pixels
Total number of pixels:
795 (H)
596 (V) approx. 470K pixels
Chip size:
7.40mm (H)
5.95mm (V)
Unit cell size:
8.6m (H)
8.3m (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 11
40
3
2
ICX419ALL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products. You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products. You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
Export Control
If the Products are controlled items under the export control laws or regulations of various countries, approval
may be required for the export of the Products under the said laws or regulations. You should be responsible
for compliance with the said laws or regulations.
No License Implied
The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise. Sony
will not assume responsibility for any problems in connection with your use of such information or for any
infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to
resolve any such problems and infringement.
Governing Law
This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this
Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first
instance.
Other Applicable Terms and Conditions
The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.
3
ICX419ALL
Block Diagram and Pin Configuration
(Top View)
11
12
13
14
15
16
17
18
19
20
Note) : Photo sensor
NC
V
DSUB
NC
GND
GND
RD
RG
NC
H
1
H
2
10
9
8
7
6
5
4
3
2
1
V
OUT
V
DD
GND
V
L
V
1
GND
SUB
V
2
V
3
V
4
Note)
Horizontal Register
V
e
r
tical Register
Pin Description
Pin No.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
Description
V
4
V
3
V
2
SUB
GND
V
1
V
L
GND
V
DD
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
GND
Vertical register transfer clock
Protective transistor bias
GND
Output circuit supply voltage
Signal output
Symbol
Description
NC
V
DSUB
NC
GND
GND
RD
RG
NC
H
1
H
2
Substrate bias circuit supply voltage
GND
GND
Reset drain bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
4
ICX419ALL
Absolute Maximum Ratings
Item
Substrate clock
SUB
GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
H
1
, H
2
V
4
RG
GND
RG
SUB
V
L
SUB
Pins other than GND and
SUB
V
L
Storage temperature
Operating temperature
0.3 to +50
0.3 to +18
55 to +10
15 to +20
to +10
to +15
to +17
17 to +17
10 to +15
55 to +10
65 to +0.3
0.3 to +30
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
1
+27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
V
DD
, V
RD
, V
DSUB
, V
OUT
GND
V
DD
, V
RD
, V
DSUB
, V
OUT
SUB
V
1
, V
2
, V
3
, V
4
GND
V
1
, V
2
, V
3
, V
4
SUB
5
ICX419ALL
DC Characteristics
Output circuit supply current
Item
I
DD
Symbol
5.0
Min.
Unit
Remarks
Typ.
Max.
mA
10.0
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item
V
DD
V
RD
V
L
V
DSUB
SUB
Symbol
15.0
15.0
1
15.0
2
Min.
V
V
V
Unit
Remarks
Typ.
Max.
14.55
14.55
14.55
15.45
15.45
15.45
V
RD
= V
DD
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
3
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same supply voltage as the V
L
power supply for the V driver should be used. (When CXD1267AN is used.)
4
Connect to GND or leave open.
5
The setting value of the substrate voltage (V
SUB
) is indicated on the back of the image sensor by a
special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is 3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
V
SUB
code -- one character indication
Code and optimal setting correspond to each other as follows.
Item
V
DD
V
RD
V
L
V
DSUB
V
SUB
V
SUB
Symbol
15.0
15.0
3
4
Min.
V
V
V
%
Unit
Remarks
Typ.
Max.
14.55
14.55
6.0
3
15.45
15.45
14.0
+3
V
RD
= V
DD
5
5
<Example> "L"
V
SUB
= 9.0V
V
SUB
code
Optimal setting
f
6.5
G
7.0
h
7.5
J
8.0
K
8.5
L
9.0
m
9.5
N
10.0
P
10.5
Q
11.0
S
12.0
U
13.0
V
13.5
W
14.0
R
11.5
T
12.5
E
6.0
6
ICX419ALL
Clock Voltage Conditions
1
Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
1
Substrate clock voltage
Item
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
| V
VH1
V
VH2
|
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RGL
V
RG
V
RGLH
V
RGLL
V
SUB
Symbol
14.55
0.05
0.2
9.6
8.3
0.25
0.25
4.75
0.05
4.5
23.0
Min.
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Remarks
Reset gate clock
voltage
Item
V
RGL
V
RG
Symbol
4
4
Waveform
diagram
Remarks
15.0
0
0
9.0
9.0
5.0
0
1
5.0
24.0
Typ.
15.45
0.05
0.05
8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
Max. Unit
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
0.2
8.5
Min.
0
9.0
Typ.
0.2
9.5
Max. Unit
V
Vp-p
7
ICX419ALL
Horizontal transfer clock equivalent circuit
Vertical transfer clock equivalent circuit
H
1
H
2
C
H1
C
H2
C
HH
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
Clock Equivalent Circuit Constant
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
H1
C
H2
C
HH
C
RG
C
SUB
R
1
, R
3
R
2
, R
4
R
GND
Symbol
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Item
Min.
3300
3300
820
330
120
91
47
11
680
75
82
68
Typ.
Max.
pF
pF
pF
pF
pF
pF
pF
pF
pF
Unit
Remarks
8
ICX419ALL
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
100%
90%
10%
0%
tr
tf
0V
twh
M
2
M
V
VT
V
VH1
V
VHH
V
VHL
V
VH
V
VLH
V
VL1
V
VLL
V
VHL
V
VHH
V
VL
V
VHH
V
VH
V
VLH
V
VLL
V
VL
V
VHL
V
VL3
V
VHL
V
VH3
V
VHH
V
VH2
V
VHH
V
VHH
V
VHL
V
VHL
V
VH
V
VLH
V
VL2
V
VLL
V
VL
V
VH
V
VL
V
VHL
V
VLH
V
VLL
V
VHL
V
VH4
V
VHH
V
VHH
V
VL4
V
1
V
3
V
2
V
4
9
ICX419ALL
(3) Horizontal transfer clock waveform
(4) Reset gate clock waveform
V
RGLH
is the maximum value and V
RGLL
is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, V
RGL
is the average value of V
RGLH
and
V
RGLL
.
V
RGL
= (V
RGLH
+ V
RGLL
)/2
Assuming V
RGH
is the minimum value during the period twh, then:
V
RG
= V
RGH
V
RGL
Negative overshoot level during the falling edge of RG is V
RGLm
.
(5) Substrate clock waveform
100%
90%
10%
0%
V
SUB
tr
tf
twh
M
2
M
V
SUB
tr
twh
tf
90%
10%
twl
V
H
V
HL
Point A
twl
V
RG
V
RGH
V
RGL
V
RGLH
RG waveform
V
RGLL
H
1
waveform
twh
tr
tf
+2.5V
V
RGLm
V
RGL
+ 0.5V
10
ICX419ALL
Clock Switching Characteristics
1
When vertical transfer clock driver CXD1267AN is used.
2
tf
tr 2ns.
3
The overlap period for twh and twl of horizontal transfer clocks H
1
and H
2
is two.
Min.
two
Typ.
Max.
16
20
Unit
ns
Remarks
Item
Horizontal transfer clock
Symbol
H
1
, H
2
3
Min.
twh
Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
twl
tr
tf
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
Unit
s
ns
ns
s
ns
s
Remarks
During readout
1
2
When draining
charge
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
Symbol
V
T
V
1
, V
2
,
V
3
, V
4
H
H
1
H
2
RG
SUB
Hor
iz
ontal
tr
ansf
er cloc
k
0.5
During
imaging
During
parallel-serial
conversion
11
ICX419ALL
Image Sensor Characteristics
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Dark signal
Dark signal shading
Flicker
Lag
Symbol
S
Ysat
Sm
SH
Vdt
Vdt
F
Lag
Min.
880
1000
Typ.
1100
115
Max.
105
20
25
2
1
2
0.5
Unit
mV
mV
dB
%
%
mV
mV
%
%
Measurement
method
1
2
3
4
4
5
6
7
8
Remarks
Ta = 60C
Zone 0 and
I
Zone 0 to
II'
Ta = 60C
Ta = 60C
Zone Definition of Video Signal Shading
(Ta = 25C)
14
V
10
14
12
10
Ignored region
Effective pixel region
Zone 0,
I
Zone
II, II'
V
10
H
8
H
8
752 (H)
582 (V)
12
ICX419ALL
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Definition of standard imaging conditions
1) Standard imaging condition
I
:
Use a pattern box (luminance 706cd/m
2
, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
2) Standard imaging condition
II
:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition
I
. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the
following formula.
S = Vs
[mV]
2. Saturation signal
Set to standard imaging condition
II
. After adjusting the luminous intensity to 10 times the intensity with
average value of the signal output, 200mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped
and the charge drain is executed by the electronic shutter at the respective H blankings, measure the
maximum value VSm [mV] of the signal output and substitute the value into the following formula.
Sm = 20
log
4. Video signal shading
Set to standard imaging condition
II
. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vmax Vmin)/200
100 [%]
250
50
1
10
1
500
VSm
200
[dB] (1/10V method conversion value)
13
ICX419ALL
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
Vdt = Vdmax Vdmin [mV]
7. Flicker
Set to standard imaging condition
II
. Adjust the luminous intensity so that the average value of the signal
output is 200mV, and then measure the difference in the signal level between fields (
Vf [mV]). Then
substitute the value into the following formula.
Fy = (
Vf/200)
100 [%]
10. Lag
Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/200)
100 [%]
Light
signal output 200mV
Ylag (lag)
FLD
V1
Strobe light
timing
Output
14
ICX419ALL
Drive Cir
cuit 1 (substrate bias internal g
eneration mode)
22/16V
0.01
9V
3.3/16V
3.3/20V
0.01
1/35V
1
100
H
1
H
2
NC
RG
RD
GND
GND
NC
V
DSUB
NC
22/20V
CCD OUT
[
A]
15V
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
H
2
H
1
RG
100k
0.01
CXD1267AN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
3.9k
V
4
V
3
V
2
SUB
GND
V
L
GND
V
DD
V
OUT
V
1
ICX419
(BO
TT
OM VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1M
15
ICX419ALL
Drive Cir
cuit 2 (substrate bias e
xternal adjustment mode)
22/16V
0.01
9V
3.3/16V
3.3/20V
0.01
1/35V
0.1
100
H
1
H
2
NC
RG
RD
GND
GND
NC
V
DSUB
NC
22/20V
CCD OUT
[
A]
15V
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
H
2
H
1
RG
27k
0.01
CXD1267AN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
3.9k
0.1
39k
15k
47k
15k
270k
100k
1/35V
1/35V
0.1
V
4
V
3
V
2
SUB
GND
V
L
GND
V
DD
V
OUT
V
1
ICX419
(BO
TT
OM VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1M
56k
16
ICX419ALL
Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)
Sensor Readout Clock Timing Chart
1.0
0.8
0.9
0.6
0.4
0.2
0.7
0.5
0.3
0.1
0
400
500
600
700
Wave Length [nm]
Relativ
e Response
800
900
1000
Odd Field
Even Field
V1
V2
V3
V4
V1
V2
V3
V4
2.5
2.6 2.5 2.5
33.6
1.5
0.2
Unit: s
17
ICX419ALL
Drive Timing
Char
t
(V
er
tical
Sync)
FLD
VD
BLK
HD
V1
V2
V3
V4
CCD
OUT
620
625
1
2
3
4
5
15
20
25
310
320
335
330
340
581
582
13
5
24
6
13
5
24
6
582
581
2
1
4
3
6
5
10
315
325
2
1
4
3
6
5
18
ICX419ALL
Drive
Timing Char
t (Horizontal Sync)
745
750
1
3
5
10
20
30
40
1
2
3
5
10
20
22
1
2
3
1
2
3
10
20
752
HD
BLK
H1
H2
RG
V1
V2
V3
V4
SUB
19
ICX419ALL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
39N
Lower ceramic
Upper ceramic
Compressive strength
Low melting
point glass
29N
Shearing strength
29N
Tensile strength
0.9Nm
Torsional strength
20
ICX419ALL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to
perform the following actions as this may cause cracks.
Applying repeated bending stress to the outer leads.
Heating the outer leads for an extended period with a soldering iron.
Rapidly cooling or heating the package.
Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
21
ICX419ALL
P
a
c
k
a
g
e Outline
Unit:
mm
Sony Corporation
0.3
M
P
A
CKA
GE STR
UCTURE
P
A
CKA
GE MA
TERIAL
LEAD TREA
TMENT
LEAD MA
TERIAL
P
A
CKA
GE MASS
Cer-DIP
TIN PLA
TING
42 ALLO
Y
2.6g
DRA
WING NUMBER
AS-B14-01(E)
A
1
1
0 to 9
H
V
C
B
~
~
20pin DIP (600mil)
20
10
11
10
11
20
(0.7R)
1.4
15.24
0.25
18.0 0.4
9.0
7.55
15.1 0.3
1.27
4.0 0.3
14.6
3
0.55
3
11.55
3
0.7
0.8
1.778
0.4
(4.0)
(1.7)
1.4
(1.0)
0.70
3.26 0.3
0.46
0.4
0.51
~
B'
1.
"A"
is the center of the eff
ectiv
e image area.
2.
The tw
o points
"B"
of the pac
kage are the hor
iz
ontal ref
erence
.
The point
"B'"
of the pac
kage is the v
e
r
tical ref
erence
.
3.
The bottom
"C"
of the pac
kage is the height ref
erence
.
4.
The center of the eff
ectiv
e image area, relativ
e to
"B"
and
"B'"
is
(H,
V) = (9.0, 7.55) 0.15mm.
5.
The rotation angle of the eff
ectiv
e image area relativ
e to H and
V is 1
.
6.
The height from the bottom
"C"
to the eff
ectiv
e image area is 1.41 0.15mm.
7.
The tilt of the eff
ectiv
e image area relativ
e to the bottom
"C"
is less than 60m.
8.
The thic
kness of the co
v
er glass is 0.75mm, and the refr
activ
e inde
x is 1.5.
9.
The notch and the hole on the bottom m
ust not be used f
or ref
erence of fixing.
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