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Электронный компонент: ILX531A

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5150-pixel CCD Linear Sensor (B/W)
Description
The ILX531A is a reduction type CCD linear sensor
developed for high resolution copiers. This sensor
reads A3-size documents at a density of 400 DPI,
and A4-size documents at a density of 600 DPI at
high speed.
Features
Number of effective pixels: 5150 pixels
Pixel size:
7m
7m (7m pitch)
Clamp circuit are on-chip
Signal output phase of two-output
simultaneous-output
(alternate-output is available)
Ultra high sensitivity/Ultra low lag
Maximum data rate:
40MHz
Single 12V power supply
Input clock pulse:
CMOS 5V drive
Package:
22 pin Plastic DIP (400mil)
Absolute Maximum Ratings
Supply voltage
V
DD
15
V
Operating temperature
10 to +60
C
Storage temperature
30 to +80
C
Pin Configuration (Top View)
Block Diagram
1
E97X25B97-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ILX531A
22 pin DIP (Plastic)
5150
1
2
3
4
5
6
7
8
9
10
11
1
CLP-
ODD
GND
V
OUT
-
ODD
V
GG
GND
V
DD
RS-
ODD
LH-
ODD
2-
ODD
1-
ODD
ROG
12
13
14
15
16
17
18
19
20
21
22
V
DD
V
OUT
-
EVEN
V
DD
NC
GND
V
DD
CLP-
EVEN
RS-
EVEN
LH-
EVEN
2-
EVEN
1-
EVEN
D25
D26
D74
S1
S2
S5149
S5150
D75
D94
ROG pulse
generator
Read out gate
CCD analog shift register
10
V
DD
1-
ODD
9
ROG
11
RS-
ODD
2
LH-
ODD
3
GND
4
2-
ODD
8
GND
14
V
DD
12
1-
EVEN
13
2-
EVEN
15
V
DD
17
V
DD
19
LH-
EVEN
20
RS-
EVEN
21
Read out gate
CCD analog shift register
5
V
OUT
-
ODD
18
V
OUT
-
EVEN
6
V
GG
CLP-
ODD
1
Output
amplifier
CLP-
EVEN
22
Output
amplifier
2
ILX531A
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
CLP-
ODD
RS-
ODD
LH-
ODD
GND
V
OUT
-
ODD
V
GG
GND
2-
ODD
1-
ODD
V
DD
ROG
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
GND
Signal out (odd pixel)
Output circuit gate bias
GND
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
12V power supply
Readout gate clock pulse input
12
13
14
15
16
17
18
19
20
21
22
V
DD
1-
EVEN
GND
2-
EVEN
NC
V
DD
V
OUT-EVEN
V
DD
LH-
EVEN
RS-
EVEN
CLP-
EVEN
12V power supply
Clock pulse input (even pixel)
GND
Clock pulse input (even pixel)
NC
12V power supply
Signal out (even pixel)
12V power supply
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Recommended Supply Voltage
Item
V
DD
Min.
11.4
Typ.
12
Max.
12.6
Unit
V
Clock Characteristics
Symbol
C
1, C
2
C
LH
C
RS
C
CLP
C
ROG
Min.
--
--
--
--
--
Typ.
400
10
10
10
10
Max.
--
--
--
--
--
Unit
pF
pF
pF
pF
pF
Item
Input capacity of
1
1
,
2
1
Input capacity of
LH
1
Input capacity of
RS
1
Input capacity of
CLP
1
Input capacity of
ROG
Input Clock Pulse Voltage Condition
High level
Low level
Min.
4.75
--
Typ.
5.0
0
Max.
5.25
0.1
Unit
V
V
Item
1,
2,
LH,
RS,
CLP,
ROG
pulse voltage
1
It indicates that
1-
ODD
,
1-
EVEN
as
1,
2-
ODD
,
2-
EVEN
as
2,
LH-
ODD
,
LH-
EVEN
as
LH,
RS-
ODD
,
RS-
EVEN
as
RS,
CLP-
ODD
,
CLP-
EVEN
as
CLP.
Clock Frequency
Min.
--
--
Typ.
1
2
Max.
20
40
Unit
MHz
MHz
Item
Symbol
1,
2,
LH,
RS,
CLP
Data rate
f
1, f
2, f
LH
, f
RS
, f
CLP
f
R
3
ILX531A
Electrooptical Characteristics (Note 1)
(Ta = 25C, V
DD
= 12V, f
R
= 2MHz, Input clock = 5Vp-p,
Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Sensitivity1
Sensitivity2
Sensitivity nonuniformity
Saturation output voltage
Saturation exposure
Register imbalance
Dark voltage average
Dark signal nonuniformity
Image lag
Supply current
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
V
SAT
SE
RI
V
DRK
DSNU
IL
I
VDD
TTE
Z
O
V
OS
8.2
--
--
1.8
0.13
--
--
--
--
--
92
--
--
11
25.1
4
2.5
0.23
1
0.3
0.6
0.02
30
98
150
6.5
13.8
--
10
--
--
7
2.0
5.0
--
60
--
--
--
V/(lx s)
V/(lx s)
%
V
lx s
%
mV
mV
%
mA
%
V
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
--
--
--
Note 11
Notes
1) In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) W lamp (2854K)
4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
V
OUT
= 500mV (Typ.)
PRNU =
100 [%]
Where the 5150 pixels are divided into blocks of even and odd pixels, respectively. The maximum output of
each block is set to V
MAX
, the minimum output to V
MIN
and the average output to V
AVE
.
5) Use below the minimum value of the saturation output voltage.
6) Saturation exposure is defined as follows. SE = V
SAT
/R1
7) RI is defined as indicated bellow. V
OUT
= 500mV (Typ.)
RI =
100 [%]
Where average of odd pixels output is set to V
ODD-AVE
, even pixels to V
EVEN-AVE
.
8) Optical signal accumulated time
int stands at 10ms.
9) The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. The larger value is defined as the dark signal nonuniformity.
Optical signal accumulated time
int stands at 10ms.
(V
MAX
V
MIN
) /2
V
AVE
| V
ODD-AVE
V
EVEN-AVE
|
V
ODD-AVE
+ V
EVEN-AVE
(
2
)
4
ILX531A
10) V
OUT
= 500 mV (Typ.)
11) V
OS
is defined as indicated bellow.
V
OS
V
OUT
GND
5
ILX531A
5
0
5
0
5
0
5
0
5
0
1
2
3
26
22
R
O
G
1
-
O
D
D
1
-
E
V
E
N
L
H
-
O
D
D
L
H
-
E
V
E
N
2
-
O
D
D
2
-
E
V
E
N
R
S
-
O
D
D
R
S
-
E
V
E
N
C
L
P
-
O
D
D
C
L
P
-
E
V
E
N
V
O
U
T
-
E
V
E
N
V
O
U
T
-
O
D
D
D1
D3
D5
D2
3
D2
5
D2
7
D6
9
D7
1
D7
3
S1
S3
S5
14
5
S5
14
7
S5
14
9
D7
5
D7
7
D7
9
D8
1
D8
3
D9
3
D2
D4
D6
D2
4
D2
6
D2
8
D7
0
D7
2
D7
4
S2
S4
S5
14
6
S5
14
8
S5
15
0
D7
6
D7
8
D8
0
D8
2
D8
4
D9
4
O
p
t
i
c
a
l

b
l
a
c
k

(
4
8

p
i
x
e
l
s
)
D
u
m
m
y

s
i
g
n
a
l

(
7
4

p
i
x
e
l
s
)
1
-
l
i
n
e

o
u
t
p
u
t

p
e
r
i
o
d

(
5
2
4
4

p
i
x
e
l
s
)
N
o
t
e
)

T
h
e

t
r
a
n
s
f
e
r

p
u
l
s
e
s

(
1
,
2
,
L
H
)

m
u
s
t

h
a
v
e

m
o
r
e

t
h
a
n

2
6
2
2

c
y
c
l
e
s
.
Clock Timing Chart 1
(simultaneous output)