Publication Number S29AL016D_00 Revision A Amendment 2 Issue Date December 17, 2004

PRELIMINARY

S29AL016D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory

Data Sheet

Distinctive Characteristics

Architectural Advantages

Single power supply operation

-- Full voltage range: 2.7 to 3.6 volt read and write op-

erations for battery-powered applications

Manufactured on 200nm process technology

-- Fully compatible with 0.23 祄 Am29LV160D and

MBM29LV160E devices

Flexible sector architecture

-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-

one 64 Kbyte sectors (byte mode)

-- One 8 Kword, two 4 Kword, one 16 Kword, and thirty-

one 32 Kword sectors (word mode)

Sector Protection features

-- A hardware method of locking a sector to prevent any

program or erase operations within that sector

-- Sectors can be locked in-system or via programming

equipment

-- Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Program Command

-- Reduces overall programming time when issuing

multiple program command sequences

Top or bottom boot block configurations
available
Compatibility with JEDEC standards

-- Pinout and software compatible with single-power

supply Flash

-- Superior inadvertent write protection

Performance Characteristics

High performance

-- Access times as fast as 70 ns

Ultra low power consumption (typical values
at 5 MHz)

-- 200 nA Automatic Sleep mode current
-- 200 nA standby mode current
-- 9 mA read current
-- 20 mA program/erase current

Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical

Package Options

48-ball FBGA
48-pin TSOP
44-pin SOP

Software Features

CFI (Common Flash Interface) compliant

-- Provides device-specific information to the system,

allowing host software to easily reconfigure for
different Flash devices

Erase Suspend/Erase Resume

-- Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,
then resumes the erase operation

Data# Polling and toggle bits

-- Provides a software method of detecting program or

erase operation completion

Hardware Features

Ready/Busy# pin (RY/BY#)

-- Provides a hardware method of detecting program or

erase cycle completion

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S29AL016D_00_A2 December 17, 2004

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General Description

The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152
bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP
packages. The word-wide data (x16) appears on DQ15璂Q0; the byte-wide (x8)
data appears on DQ7璂Q0. This device is designed to be programmed in-system
with the standard system 3.0 volt V

supply. A 12.0 V V

or 5.0 V

are not

required for write or erase operations. The device can also be programmed in
standard EPROM programmers.

The device offers access times of 70 ns and 90 ns allowing high speed micropro-
cessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.

The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.

The S29AL016D is entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This
initiates the Embedded Program algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm--an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle) status bits. After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low V

detector that automat-

ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved.

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Table of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6

Special Handling Instructions ...............................................................7

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

S29AL016D Standard Products ........................................................... 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. S29AL016D Device Bus Operations .........................10

Word/Byte Configuration ...................................................................10
Requirements for Reading Array Data ............................................ 11
Writing Commands/Command Sequences .................................... 11
Program and Erase Operation Status ............................................... 11
Standby Mode ......................................................................................... 12
Automatic Sleep Mode ......................................................................... 12
RESET#: Hardware Reset Pin ............................................................ 12
Output Disable Mode ........................................................................... 13

Table 2. Sector Address Tables (Top Boot Device) .................13
Table 3. Sector Address Tables (Bottom Boot Device) ............14

Autoselect Mode ................................................................................... 14

Table 4. S29AL016D Autoselect Codes (High Voltage Method) .15

Sector Protection/Unprotection ....................................................... 15
Temporary Sector Unprotect ........................................................... 15

Figure 1. Temporary Sector Unprotect Operation................... 16
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 17

Common Flash Memory Interface (CFI). . . . . . . 18

Table 5. CFI Query Identification String ...............................18
Table 6. System Interface String .........................................19
Table 7. Device Geometry Definition ....................................19
Table 8. Primary Vendor-Specific Extended Query .................20

Hardware Data Protection ................................................................20
Low V

Write Inhibit .......................................................................20

Write Pulse "Glitch" Protection ......................................................20
Logical Inhibit .......................................................................................... 21
Power-Up Write Inhibit ...................................................................... 21

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 22

Reading Array Data ............................................................................. 22
Reset Command ................................................................................... 22
Autoselect Command Sequence ...................................................... 23
Word/Byte Program Command Sequence ................................... 23
Unlock Bypass Command Sequence ............................................... 24

Figure 3. Program Operation .............................................. 24

Chip Erase Command Sequence ...................................................... 25
Sector Erase Command Sequence .................................................. 25
Erase Suspend/Erase Resume Commands .................................... 26

Figure 4. Erase Operation .................................................. 27

Command Definitions .........................................................................28

Table 9. S29AL016D Command Definitions ...........................28

Write Operation Status . . . . . . . . . . . . . . . . . . . . 29

DQ7: Data# Polling .............................................................................. 29

Figure 5. Data# Polling Algorithm ....................................... 30

RY/BY#: Ready/Busy# ......................................................................... 30
DQ6: Toggle Bit I ................................................................................... 31

DQ2: Toggle Bit II ................................................................................ 32
Reading Toggle Bits DQ6/DQ2 ........................................................ 32

Figure 6. Toggle Bit Algorithm ............................................ 33

DQ5: Exceeded Timing Limits ...........................................................33
DQ3: Sector Erase Timer .................................................................. 34

Table 10. Write Operation Status ....................................... 34

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 35

Figure 7. Maximum Negative Overshoot Waveform................ 35
Figure 8. Maximum Positive Overshoot Waveform ................. 35

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Industrial (I) Devices ............................................................................ 36
V

Supply Voltages ............................................................................ 36

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

CMOS Compatible ................................................................................37
Zero Power Flash ................................................................................. 38

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ................................................. 38
Figure 10. Typical I

CC1

vs. Frequency .................................. 38

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Test Setup ........................................................ 39
Table 11. Test Specifications ............................................. 39

Key to Switching Waveforms ...........................................................40

Figure 12. Input Waveforms and Measurement Levels............ 40

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

Read Operations .................................................................................... 41

Figure 13. Read Operations Timings .................................... 41

Hardware Reset (RESET#) ................................................................ 42

Figure 14. RESET# Timings ................................................ 42

Word/Byte Configuration (BYTE#) ................................................ 43

Figure 15. BYTE# Timings for Read Operations ..................... 43
Figure 16. BYTE# Timings for Write Operations..................... 44

Erase/Program Operations ................................................................ 45

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 17. Program Operation Timings ................................. 46
Figure 18. Chip/Sector Erase Operation Timings.................... 47
Figure 19. Data# Polling Timings (During Embedded
Algorithms)...................................................................... 48
Figure 20. Toggle Bit Timings (During Embedded Algorithms) . 48
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend

Operations....................................................................... 49

Temporary Sector Unprotect ..........................................................49

Figure 22. Temporary Sector Unprotect/Timing Diagram ........ 49
Figure 23. Sector Protect/Unprotect Timing Diagram.............. 50

Alternate CE# Controlled Erase/Program Operations ............. 51

Figure 24. Alternate CE# Controlled Write Operation Timings.. 52

Erase and Programming Performance . . . . . . . . 53
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 54

TS 048--48-Pin Standard TSOP ...................................................... 54
VBK048--48-Ball Fine-Pitch Ball Grid Array (FBGA)

8.15 mm x 6.15 mm ................................................................................ 56

SO044--44-Pin Small Outline Package (SOP)

28.20 mm x 13.30 mm . . . . . . . . . . . . . . . . . . . . . . . 57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision A (May 4, 2004) ................................................................... 58
Revision A1 (July 28, 2004) ................................................................. 58
Revision A2 (December 17, 2004) ................................................... 58

December 17, 2004 S29AL016D_00_A2

S29AL016D

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Ordering Information

S29AL016D Standard Products

Spansion standard products are available in several packages and operating
ranges. The order number (Valid Combination) is formed by a combination of the
elements below.

Notes:

1. Type 0 is standard. Specify other options as required.
2. TSOP and SOP package markings omit packing type designator from ordering part number.
3. BGA package marking omits leading "S29" and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your

local sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

S29AL016D

PACKING TYPE

= Tray

= 13" Tape and Reel

MODEL NUMBER

= V

= 2.7 - 3.6V, top boot sector device

= V

= 2.7 - 3.6V, bottom boot sector device

TEMPERATURE RANGE

I =

Industrial

(�40

�

C to +85

�

PACKAGE MATERIAL SET

= Standard

= Pb-Free

PACKAGE TYPE

= Thin Small Outline Package (TSOP) Standard Pinout

= Fine-pitch Ball-Grid Array Package

= Small Outline Package (SOP) Standard Pinout

SPEED OPTION

= 70 ns Access Speed

= 90 ns Access Speed

DEVICE NUMBER/DESCRIPTION

S29AL016D
16 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase

S29AL016D Valid Combinations

Package

Description

Device

Number

Speed

Option

Package Type,

Material, and

Temperature Range

Model

Number

Packing

Type

S29AL016D

70, 90

TAI, TFI

01, 02

0, 2, 3

(

Note 1

)

TS048 (

Note 2

)

TSOP

BAI, BFI

VBK048 (

Note 3

)

Fine-Pitch BGA

MAI, MFI

SO044 (

Note 2

)

SOP

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Device Bus Operations

This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
function of the device.

Table 1

lists the device bus operations, the inputs and con-

trol levels they require, and the resulting output. The following subsections
describe each of these operations in further detail.

Table 1. S29AL016D Device Bus Operations

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 12.0 � 0.5 V, X = Don't Care, A

= Address In, D

= Data In, D

OUT

= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V

), A19:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the

"Sector Protection/Unprotection" section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15璂Q0 operate in
the byte or word configuration. If the BYTE# pin is set at logic `1', the device is in
word configuration, DQ15璂Q0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic `0', the device is in byte configuration, and only
data I/O pins DQ0璂Q7 are active and controlled by CE# and OE#. The data I/
O pins DQ8璂Q14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.

Operation

CE# OE# WE# RESET#

Addresses

(

Note 1

)

DQ0�

DQ7

DQ8璂Q15

BYTE#

= V

BYTE#

= V

Read

OUT

DQ8璂Q14 = High-Z,

DQ15 = A-1

Write

Standby

�

0.3 V

�

0.3 V

High-Z High-Z

High-Z

Output Disable

High-Z High-Z

High-Z

Reset

High-Z High-Z

High-Z

Sector Protect (

Note 2

)

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Unprotect (

Note 2

)

Sector Address,

A6 = H, A1 = H,

A0 = L

Temporary Sector

Unprotect

High-Z

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Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins
to V

. CE# is the power control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should remain at V

. The BYTE#

pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the com-
mand register contents are altered.

See

Reading Array Data

for more information. Refer to the AC

Read Operations

table for timing specifications and to

Figure 13

for the timing diagram. I

CC1

in the

DC Characteristics table represents the active current specification for reading ar-

ray data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. See

Word/Byte Configuration

for more

information.

The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four.

Word/Byte Program Command

Sequence

has details on programming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Tables

and

indicate the address space that each sector occupies. A "sector

address" consists of the address bits required to uniquely select a sector. The

Command Definitions

section has details on erasing a sector or the entire chip,

or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7璂Q0. Standard read
cycle timings apply in this mode. Refer to the

Autoselect Mode

and

Autoselect

Command Sequence

sections for more information.

CC2

in the DC Characteristics table represents the active current specification for

the write mode. The

AC Characteristics

section contains timing specification ta-

bles and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the
operation by reading the status bits on DQ7璂Q0. Standard read cycle timings
and I

read specifications apply. Refer to

Write Operation Status

for more infor-

mation, and to

AC Characteristics

for timing diagrams.

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Standby Mode

When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.

The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V

� 0.3 V. (Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at V

, but not within V

� 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t

) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.

In the

DC Characteristics

table, I

CC3

and I

CC4

represents the standby current

specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t

ACC

+ 30

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. I

CC4

in the

DC Characteristics

table represents the automatic sleep mode

current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V

for at least a period of

, the device immediately terminates any operation in progress, tristates all

data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V

�0.3 V, the device draws CMOS standby current (I

CC4

). If RESET# is held

at V

but not within V

�0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a "0" (busy) until the internal reset operation is complete, which requires
a time of t

READY

(during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is "1"), the reset
operation is completed within a time of t

READY

(not during Embedded Algorithms).

The system can read data t

after the RESET# pin returns to V

Refer to the

AC Characteristics

tables for RESET# parameters and to

Figure 14

for the timing diagram.

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Output Disable Mode

When the OE# input is at V

, output from the device is disabled. The output pins

are placed in the high impedance state.

Table 2. Sector Address Tables (Top Boot Device)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section.

Sector

A19

A18

A17

A16

A15

A14

A13

A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8)

Word Mode (x16)

SA0

64/32

000000�00FFFF

00000�07FFF

SA1

64/32

010000�01FFFF

08000�0FFFF

SA2

64/32

020000�02FFFF

10000�17FFF

SA3

64/32

030000�03FFFF

18000�1FFFF

SA4

64/32

040000�04FFFF

20000�27FFF

SA5

64/32

050000�05FFFF

28000�2FFFF

SA6

64/32

060000�06FFFF

30000�37FFF

SA7

64/32

070000�07FFFF

38000�3FFFF

SA8

64/32

080000�08FFFF

40000�47FFF

SA9

64/32

090000�09FFFF

48000�4FFFF

SA10

64/32

0A0000�0AFFFF

50000�57FFF

SA11

64/32

0B0000�0BFFFF

58000�5FFFF

SA12

64/32

0C0000�0CFFFF

60000�67FFF

SA13

64/32

0D0000�0DFFFF

68000�6FFFF

SA14

64/32

0E0000�0EFFFF

70000�77FFF

SA15

64/32

0F0000�0FFFFF

78000�7FFFF

SA16

64/32

100000�10FFFF

80000�87FFF

SA17

64/32

110000�11FFFF

88000�8FFFF

SA18

64/32

120000�12FFFF

90000�97FFF

SA19

64/32

130000�13FFFF

98000�9FFFF

SA20

64/32

140000�14FFFF

A0000瑼7FFF

SA21

64/32

150000�15FFFF

A8000瑼FFFF

SA22

64/32

160000�16FFFF

B0000瑽7FFF

SA23

64/32

170000�17FFFF

B8000瑽FFFF

SA24

64/32

180000�18FFFF

C0000瑿7FFF

SA25

64/32

190000�19FFFF

C8000瑿FFFF

SA26

64/32

1A0000�1AFFFF

D0000璂7FFF

SA27

64/32

1B0000�1BFFFF

D8000璂FFFF

SA28

64/32

1C0000�1CFFFF

E0000璄7FFF

SA29

64/32

1D0000�1DFFFF

E8000璄FFFF

SA30

64/32

1E0000�1EFFFF

F0000璅7FFF

SA31

32/16

1F0000�1F7FFF

F8000璅BFFF

SA32

8/4

1F8000�1F9FFF

FC000璅CFFF

SA33

8/4

1FA000�1FBFFF

FD000璅DFFF

SA34

16/8

1FC000�1FFFFF

FE000璅FFFF

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Table 3. Sector Address Tables (Bottom Boot Device)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the "Word/Byte Configuration" section.

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7璂Q0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V

(11.5 V

to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in

Table 4

. In addition, when verifying sector protection, the sector address must

appear on the appropriate highest order address bits (see

Table 2

and

Table 3

Table 4

shows the remaining address bits that are don't care. When all necessary

bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.

Sector

A19

A18

A17

A16

A15

A14

A13

A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8)

Word Mode (x16)

SA0

16/8

000000�003FFF

00000�01FFF

SA1

8/4

004000�005FFF

02000�02FFF

SA2

8/4

006000�007FFF

03000�03FFF

SA3

32/16

008000�00FFFF

04000�07FFF

SA4

64/32

010000�01FFFF

08000�0FFFF

SA5

64/32

020000�02FFFF

10000�17FFF

SA6

64/32

030000�03FFFF

18000�1FFFF

SA7

64/32

040000�04FFFF

20000�27FFF

SA8

64/32

050000�05FFFF

28000�2FFFF

SA9

64/32

060000�06FFFF

30000�37FFF

SA10

64/32

070000�07FFFF

38000�3FFFF

SA11

64/32

080000�08FFFF

40000�47FFF

SA12

64/32

090000�09FFFF

48000�4FFFF

SA13

64/32

0A0000�0AFFFF

50000�57FFF

SA14

64/32

0B0000�0BFFFF

58000�5FFFF

SA15

64/32

0C0000�0CFFFF

60000�67FFF

SA16

64/32

0D0000�0DFFFF

68000�6FFFF

SA17

64/32

0E0000�0EFFFF

70000�77FFF

SA18

64/32

0F0000�0FFFFF

78000�7FFFF

SA19

64/32

100000�10FFFF

80000�87FFF

SA20

64/32

110000�11FFFF

88000�8FFFF

SA21

64/32

120000�12FFFF

90000�97FFF

SA22

64/32

130000�13FFFF

98000�9FFFF

SA23

64/32

140000�14FFFF

A0000瑼7FFF

SA24

64/32

150000�15FFFF

A8000瑼FFFF

SA25

64/32

160000�16FFFF

B0000瑽7FFF

SA26

64/32

170000�17FFFF

B8000瑽FFFF

SA27

64/32

180000�18FFFF

C0000瑿7FFF

SA28

64/32

190000�19FFFF

C8000瑿FFFF

SA29

64/32

1A0000�1AFFFF

D0000璂7FFF

SA30

64/32

1B0000�1BFFFF

D8000璂FFFF

SA31

64/32

1C0000�1CFFFF

E0000璄7FFF

SA32

64/32

1D0000�1DFFFF

E8000璄FFFF

SA33

64/32

1E0000�1EFFFF

F0000璅7FFF

SA34

64/32

1F0000�1FFFFF

F8000璅FFFF

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in

Table 9

. This method does

not require V

. See

Command Definitions

for details on using the autoselect

mode.

Table 4. S29AL016D Autoselect Codes (High Voltage Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don't care.

Note: The autoselect codes may also be accessed in-system via command sequences. See

Table 9

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.

The device is shipped with all sectors unprotected. Spansion offers the option of
programming and protecting sectors at its factory prior to shipping the device
through Spansion's ExpressFlashTM Service. Contact a Spansion representative
for details.

It is possible to determine whether a sector is protected or unprotected. See

Au-

toselect Mode

for details.

Sector protection/unprotection can be implemented via two methods.

The primary method requires V

on the RESET# pin only, and can be imple-

mented either in-system or via programming equipment.

Figure 2

shows the

algorithms and

Figure 23

shows the timing diagram. This method uses standard

microprocessor bus cycle timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect write cycle.

The alternate method intended only for programming equipment requires V

address pin A9 and OE#. This method is compatible with programmer routines
written for earlier 3.0 volt-only Spansion flash devices. Details on this method are
provided in a supplement, publication number 21468. Contact a Spansion repre-
sentative to request a copy.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to V

. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once V

is removed from

the RESET# pin, all the previously protected sectors are protected again. shows
the algorithm, and

Figure 22

shows the timing diagrams, for this feature.

Description

Mode

CE#

OE#

WE#

A19

A12

A11

A10

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: Spansion

01h

Device ID:

S29AL016D

(Top Boot Block)

Word

22h

C4h

Byte

C4h

Device ID:

S29AL016D

(Bottom Boot Block)

Word

22h

49h

Byte

49h

Sector Protection Verification

01h (protected)

00h (unprotected)

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addresses given in

Tables

�

. In word mode, the upper address bits (A7�

MSB) must be all zeros. To terminate reading CFI data, the system must write
the reset command.

The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in

Tables

�

. The system must write the reset

command to return the device to the autoselect mode.

For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/products/nvd/
overview/cfi.html. Alternatively, contact a Spansion representative for copies of
these documents.

Table 5. CFI Query Identification String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

10h
11h
12h

20h
22h
24h

0051h
0052h
0059h

Query Unique ASCII string "QRY"

13h
14h

26h
28h

0002h
0000h

Primary OEM Command Set

15h
16h

2Ah
2Ch

0040h
0000h

Address for Primary Extended Table

17h
18h

2Eh
30h

0000h
0000h

Alternate OEM Command Set (00h = none exists)

19h
1Ah

32h
34h

0000h
0000h

Address for Alternate OEM Extended Table (00h = none exists)

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

Table 6. System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

1Bh

36h

0027h

Min. (write/erase)

D7璂4: volt, D3璂0: 100 millivolt

1Ch

38h

0036h

Max. (write/erase)

D7璂4: volt, D3璂0: 100 millivolt

1Dh

3Ah

0000h

Min. voltage (00h = no V

pin present)

1Eh

3Ch

0000h

Max. voltage (00h = no V

pin present)

1Fh

3Eh

0004h

Typical timeout per single byte/word write 2

祍

20h

40h

0000h

Typical timeout for Min. size buffer write 2

祍 (00h = not supported)

21h

42h

000Ah

Typical timeout per individual block erase 2

22h

44h

0000h

Typical timeout for full chip erase 2

ms (00h = not supported)

23h

46h

0005h

Max. timeout for byte/word write 2

times typical

24h

48h

0000h

Max. timeout for buffer write 2

times typical

25h

4Ah

0004h

Max. timeout per individual block erase 2

times typical

26h

4Ch

0000h

Max. timeout for full chip erase 2

times typical (00h = not supported)

Table 7. Device Geometry Definition

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2

byte

28h
29h

50h
52h

0002h
0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah
2Bh

54h
56h

0000h
0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh
2Fh
30h

5Ah
5Ch
5Eh
60h

0000h
0000h
0040h
0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h
32h
33h
34h

62h
64h
66h
68h

0001h
0000h
0020h
0000h

Erase Block Region 2 Information

35h
36h
37h
38h

6Ah
6Ch
6Eh
70h

0000h
0000h
0080h
0000h

Erase Block Region 3 Information

39h
3Ah
3Bh
3Ch

72h
74h
76h
78h

001Eh
0000h
0000h
0001h

Erase Block Region 4 Information

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to

Table 9

for command

definitions). In addition, the following hardware data protection measures pre-
vent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during V

power-up and power-down transitions,

or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept any write cycles. This pro-

tects data during V

power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V

is greater than V

LKO

. The system must provide the

proper signals to the control pins to prevent unintentional writes when V

greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.

Table 8. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

40h
41h
42h

80h
82h
84h

0050h
0052h
0049h

Query-unique ASCII string "PRI"

43h

86h

0031h

Major version number, ASCII

44h

88h

0030h

Minor version number, ASCII

45h

8Ah

0000h

Address Sensitive Unlock

0 = Required, 1 = Not Required

46h

8Ch

0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h

8Eh

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h

90h

0001h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h

92h

0004h

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

4Ah

94h

0000h

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Bh

96h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch

98h

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Command Definitions

Writing specific address and data commands or sequences into the command
register initiates device operations.

Table 9

defines the valid register command

sequences. Writing incorrect address and data values or writing them in the
improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

AC Characteristics

section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See

Erase Suspend/Erase Resume Commands

for more information on this mode.

The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode. See the

Reset Com-

mand

section, next.

See also

Requirements for Reading Array Data

in the

Device Bus Operations

sec-

tion for more information. The

Read Operations

table provides the read

parameters, and

Figure 13

shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data.
Address bits are don't care for this command.

The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to read-
ing array data (also applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset commands until the op-
eration is complete.

The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to reading array data (also applies to autoselect during Erase
Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to reading array data (also applies during Erase Suspend).

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-
facturer and devices codes, and determine whether or not a sector is protected.

Table 9

shows the address and data requirements. This method is an alternative

to that shown in

Table 4

, which is intended for PROM programmers and requires

on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, fol-
lowed by the autoselect command. The device then enters the autoselect mode,
and the system may read at any address any number of times, without initiating
another command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at
address XX01h returns the device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to Tables

and

for valid

sector addresses.

The system must write the reset command to exit the autoselect mode and return
to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of
the BYTE# pin. Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically generates the pro-
gram pulses and verifies the programmed cell margin.

Table 9

shows the address

and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See

Write Operation Status

for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program-
ming operation. The Byte Program command sequence should be reinitiated once
the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from a "0" back to a "1". Attempting to do so may
halt the operation and set DQ5 to "1," or cause the Data# Polling algorithm to
indicate the operation was successful. However, a succeeding read will show that
the data is still "0". Only erase operations can convert a "0" to a "1".

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.

Table 9

shows the address and data requirements

for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See

Write Operation Status

for information on these status bits.

When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.

Figure 4

illustrates the algorithm for the erase operation. See the

Erase/Program

Operations

tables in

AC Characteristics

for parameters, and to

Figure 18

for tim-

ing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command.

Table 9

shows the address and data re-

quirements for the sector erase command sequence.

The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 祍 begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 祍, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 祍, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See

DQ3: Sector Erase Timer

.) The time-out begins from the rising edge of

the final WE# pulse in the command sequence.

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to

Write

Operation Status

for information on these status bits.)

Figure 4

illustrates the algorithm for the erase operation. Refer to the

Erase/Pro-

gram Operations

tables in the

AC Characteristics

section for parameters, and to

Figure 18

for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 祍 time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out period and suspends
the erase operation. Addresses are "don't-cares" when writing the Erase Suspend
command.

When the Erase Suspend command is written during a sector erase operation, the
device requires a maximum of 20 祍 to suspend the erase operation. However,
when the Erase Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the system can read array data
from or program data to any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal read and write timings and
command definitions apply. Reading at any address within erase-suspended sec-
tors produces status data on DQ7璂Q0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
See

Write Operation Status

for information on these status bits.

After an erase-suspended program operation is complete, the system can once
again read array data within non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See

Write Operation Status

for more

information.

The system may also write the autoselect command sequence when the device
is in the Erase Suspend mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device reverts to the Erase
Suspend mode, and is ready for another valid operation. See

Autoselect Com-

mand Sequence

for more information.

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Command Definitions

Table 9. S29AL016D Command Definitions

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19瑼12 uniquely select any sector.

Note:

1. See

Table 1

for description of bus operations.

2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15璂Q8 are don't cares for unlock and command cycles.
5. Address bits A19瑼11 are don't cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device

is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also

acceptable.

13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase

Suspend command is valid only during a sector erase operation.

14. The Erase Resume command is valid only during the Erase Suspend mode.

Command

Sequence

(

Note 1

)

c
l
e

Bus Cycles (Notes

�

)

First

Second

Third

Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data Addr

Data

Addr Data

Addr

Data

Read (

Note 6

)

Reset (

Note 7

)

XXX

t
o
sel

e
c
t

(

te 8

) Manufacturer ID

Word

555

2AA

555

X00

Byte

AAA

555

AAA

Device ID,

Top Boot Block

Word

555

2AA

555

X01

22C4

Byte

AAA

555

AAA

X02

Device ID,

Bottom Boot Block

Word

555

2AA

555

X01

2249

Byte

AAA

555

AAA

X02

Sector Protect Verify

(

Note 9

)

Word

555

2AA

555

(SA)

X02

XX00
XX01

Byte

AAA

555

AAA

(SA)

X04

00
01

CFI Query (

Note 10

)

Word

Byte

Program

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass Program (

Note 11

)

XXX

Unlock Bypass Reset (

Note 12

)

XXX

Chip Erase

Word

555

2AA

555

2AA

555

Byte

AAA

555

AAA

555

AAA

Sector Erase

Word

555

2AA

555

2AA

Byte

AAA

555

AAA

555

Erase Suspend (

Note 13

)

XXX

Erase Resume (

Note 14

)

XXX

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

Write Operation Status

The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#.

Table 10

and the following subsections

describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method
for determining whether a program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final WE# pulse in the program
or erase command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 祍, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to "1"; prior to this, the
device outputs the "complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.

After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 祍, then the
device returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.

When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ7璂Q0 on the following read cycles. This is because
DQ7 may change asynchronously with DQ0璂Q6 while Output Enable (OE#) is
asserted low.

Figure 19

, Data# Polling Timings (During Embedded Algorithms),

in the

AC Characteristics

section illustrates this.

Table 10

shows the outputs for Data# Polling on DQ7.

Figure 6

shows the Data#

Polling algorithm.

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Em-
bedded Algorithm is in progress or complete. The RY/BY# status is valid after the
rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an
open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.

Table 10

shows the outputs for RY/BY#. Figures

and

shows RY/BY#

for read, reset, program, and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. (The system may use either OE# or CE#
to control the read cycles.) When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 祍, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling

If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 祍 after the program command sequence is written, then returns to
reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.

Table 10

shows the outputs for Toggle Bit I on DQ6.

Figure 6

shows the toggle bit

algorithm in flowchart form, and the section

Reading Toggle Bits DQ6/DQ2

ex-

plains the algorithm.

Figure 20

in the

AC Characteristics

section shows the toggle

bit timing diagrams.

Figure 21

shows the differences between DQ2 and DQ6 in

graphical form. See also the subsection on

DQ2: Toggle Bit II

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

DQ2: Toggle Bit II

The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to

Table 10

to compare outputs for DQ2 and DQ6.

Figure 6

shows the toggle bit algorithm in flowchart form, and the section

Reading

Toggle Bits DQ6/DQ2

explains the algorithm. See also the

DQ6: Toggle Bit I

sub-

section.

Figure 20

shows the toggle bit timing diagram.

Figure 21

shows the

differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to

Figure 6

for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7璂Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7璂Q0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of

Figure 6

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was not successfully
completed.

The DQ5 failure condition may appear if the system tries to program a "1" to a
location that is previously programmed to "0." Only an erase operation can
change a "0" back to a "1." Under this condition, the device halts the opera-
tion, and when the operation has exceeded the timing limits, DQ5 produces a "1."

Under both these conditions, the system must issue the reset command to return
the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches from "0" to "1." The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 祍. See also the

Sector Erase

Command Sequence

section.

After the sector erase command sequence is written, the system should read the
status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If DQ3 is "1", the internally
controlled erase cycle has begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete. If DQ3 is "0", the device
will accept additional sector erase commands. To ensure the command has been
accepted, the system software should check the status of DQ3 prior to and fol-
lowing each subsequent sector erase command. If DQ3 is high on the second
status check, the last command might not have been accepted.

Table 10

shows

the outputs for DQ3.

Table 10. Write Operation Status

Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. See

DQ5: Exceeded Timing Limits

for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

Operation

DQ7

(

Note 2

)

DQ6

DQ5

(

Note 1

)

DQ3

DQ2

(

Note 2

)

RY/BY#

Standard
Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase
Suspend
Mode

Reading within Erase

Suspended Sector

No toggle

N/A

Toggle

Reading within Non-Erase
Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

Absolute Maximum Ratings

Storage Temperature

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .�65癈 to +150癈
Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .�65癈 to +125癈
Voltage with Respect to Ground

(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .�0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . �0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . �0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is �0.5 V. During voltage transitions, input or I/O pins may overshoot V

to �2.0 V for periods of up to 20 ns. See

Figure 7

. Maximum DC voltage on input or I/O pins is

+0.5 V. During

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See

Figure 8

2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V

to �2.0 V for periods of up to 20 ns. See

Figure 7

. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the op-
erational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.

Figure 7. Maximum Negative Overshoot Waveform

Figure 8. Maximum Positive Overshoot Waveform

20 ns

+0.8 V

�0.5 V

20 ns

�2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

DC Characteristics

CMOS Compatible

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with OE# at V

. Typical V

is 3.0 V.

2. Maximum I

specifications are tested with V

= V

max.

3. I

active while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85�C), typical current is 5 礎 and maximum current is 10 礎.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns. Typical sleep

mode current is 200 nA.

6. Not 100% tested.

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input Load Current

= V

to V

= V

max

�1.0

礎

LIT

A9 Input Load Current

= V

CC max

; A9 = 12.5 V

礎

Output Leakage Current

OUT

= V

to V

= V

CC max

�1.0

礎

CC1

Active Read Current

(Notes

)

CE# = V

IL,

OE#

IH,

Byte Mode

10 MHz

5 MHz

1 MHz

CE# = V

IL,

OE#

IH,

Word Mode

10 MHz

5 MHz

1 MHz

CC2

Active Write Current

(Notes

)

CE# = V

IL,

OE# = V

CC3

Standby Current (Notes

) CE#, RESET# = V

�0.3 V

0.2

礎

CC4

Standby Current During Reset

(Notes

)

RESET# = V

� 0.3 V

0.2

礎

CC5

Automatic Sleep Mode

(Notes

)

= V

� 0.3 V;

= V

� 0.3 V

0.2

礎

Input Low Voltage

�0.5

0.8

Input High Voltage

0.7 x V

+ 0.3

Voltage for Autoselect and
Temporary Sector Unprotect

= 3.3 V

11.5

12.5

Output Low Voltage

= 4.0 mA, V

= V

CC min

0.45

OH1

Output High Voltage

= -2.0 mA, V

= V

CC min

2.4

OH2

= -100 礎, V

= V

CC min

�0.4

LKO

Low V

Lock-Out Voltage (Note 4)

2.3

2.5

December 17, 2004 S29AL016D_00_A2

S29AL016D

P r e l i m i n a r y

* For reference only. BSC is an ANSI standard for Basic Space Centering.

MO-142 (D) DD

MIN

0.05
0.95

0.17
0.17

0.10

18.30

19.80

0.50

0�

0.08

11.90

0.50 BASIC

MAX

0.15

1.20

0.27

0.16

0.21

8�

0.20

18.50

12.10

0.70

20.20

0.23

1.05

0.20

1.00

0.22

18.40

20.00

0.60

12.00

NOM

Symbol

Jedec

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

REVERSE PIN OUT (TOP VIEW)

2X (N/2 TIPS)

0.10

SEATING

PLANE

SEE DETAIL A

2X (N/2 TIPS)

0.25

0.10

N
2

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

DETAIL A

(c)

�

0.25MM (0.0098") BSC

GAUGE PLANE

PARALLEL TO

SEATING PLANE

(c)

WITH PLATING

BASE METAL

0.08MM (0.0031") M C A - B S

SECTION B-B

DETAIL B

e/2

X = A OR B

3355 \ 16-038.10c

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Physical Dimensions

VBK048--48-Ball Fine-Pitch Ball Grid Array (FBGA)

8.15 mm x 6.15 mm

3338 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS

NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D"

DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E"

DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

SIDE VIEW

TOP VIEW

SEATING PLANE

(4X)

0.10

0.08

BOTTOM VIEW

A1 CORNER

0.15

0.08

PIN A1

CORNER

INDEX MARK

PACKAGE VBK

048

JEDEC N/A

8.15 mm x 6.15 mm NOM

PACKAGE

SYMBOL MIN NOM MAX

NOTE

---

1.00 OVERALL

THICKNESS

0.18

---

--- BALL

HEIGHT

A2 0.62 --- 0.76

BODY

THICKNESS

8.15

BSC. BODY

SIZE

6.15

BSC. BODY

SIZE

5.60

BSC. BALL

FOOTPRINT

4.00

BSC. BALL

FOOTPRINT

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

N 48

TOTAL

BALL

COUNT

b 0.35 --- 0.43

BALL

DIAMETER

0.80

BSC. BALL

PITCH

SD / SE

0.40 BSC.

SOLDER BALL PLACEMENT

---

DEPOPULATED

SOLDER

BALLS

S29AL016D

S29AL016D_00_A2 December 17, 2004

P r e l i m i n a r y

Revision Summary

Revision A (May 4, 2004)

Initial Release.

Revision A1 (July 28, 2004)

Ordering Information
Updated ordering information: model number, speed options, and valid combinations
for TSOP and BGA packages.

DC Characteristics
Updated Max information for I

CC2

Physical Dimensions
Updated VBK048 and TS048 drawings.

Revision A2 (December 17, 2004)

Data Sheet Type
Changed from Advance Information to Preliminary.

Ordering Information
Updated ordering information: Small Outline Package options

Physical Dimensions
Added SO044 Package.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.

Copyright �2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof are trademarks of Spansion LLC. Other
company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: S29AL016D70BAI023