S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more spe-
cific products, but has not committed any design to production. Information presented in a doc-
ument with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Informa-
tion content:

"This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice."

Preliminary

The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
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manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:

"This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
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tions due to changes in technical specifications."

Combination

Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V

range. Changes

may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion LLC applies the following conditions to documents in this category:

"This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur."

Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not

design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

Publication Number S29AL032D_00 Revision A Amendment 3 Issue Date June 13, 2005

Distinctive Characteristics

Architectural Advantages

Single power supply operation

-- Full voltage range: 2.7 to 3.6 volt read and write op-

erations for battery-powered applications

Manufactured on 200 nm process technology

-- Fully compatible with 0.23 µm Am29LV320D, 0.32 µm

Am29LV033C, and 0.33 µm MBM29LV320E devices

Flexible sector architecture

-- Boot sector models: Eight 8-Kbyte sectors; sixty-

three 64-Kbyte sectors; top or bottom boot block
configurations available

-- Uniform sector models: Sixty-four 64-Kbyte sectors

Sector Protection features

-- A hardware method of locking a sector to prevent any

program or erase operations within that sector

-- Sectors can be locked in-system or via programming

equipment

-- Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Program Command

-- Reduces overall programming time when issuing

multiple program command sequences

Secured Silicon Sector

-- 128-word sector for permanent, secure identification

through an 8-word random Electronic Serial Number

-- May be programmed and locked at the factory or by

the customer

-- Accessible through a command sequence

Compatibility with JEDEC standards

-- Pinout and software compatible with single-power

supply Flash

-- Superior inadvertent write protection

Package Options

48-ball FBGA
48-pin TSOP
40-pin TSOP

Performance Characteristics

High performance

-- Access times as fast as 70 ns

Ultra low power consumption (typical values
at 5 MHz)

-- 200 nA Automatic Sleep mode current
-- 200 nA standby mode current
-- 9 mA read current
-- 20 mA program/erase current

Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical

Software Features

CFI (Common Flash Interface) compliant

-- Provides device-specific information to the system,

allowing host software to easily reconfigure for
different Flash devices

Erase Suspend/Erase Resume

-- Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,
then resumes the erase operation

Data# Polling and toggle bits

-- Provides a software method of detecting program or

erase operation completion

-- Unlock Bypass Program Command

Reduces overall programming time when issuing
multiple program command sequences

Hardware Features

Ready/Busy# pin (RY/BY#)

-- Provides a hardware method of detecting program or

erase cycle completion

Hardware reset pin (RESET#)

-- Hardware method to reset the device to reading array

data

WP#/ACC input pin

-- Write protect (WP#) function allows protection of two

outermost boot sectors (boot sector models only),
regardless of sector protect status

-- Acceleration (ACC) function provides accelerated

program times

S29AL032D

32 Megabit CMOS 3.0 Volt-only Flash Memory

4 M x 8-Bit Uniform Sector

4 M x 8-Bit/2 M x 16-Bit Boot Sector

Data Sheet

ADVANCE

INFORMATION

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

General Description

The S29AL032D is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152
words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0-DQ15;
byte mode data appears on DQ0-DQ7. The device is designed to be programmed in-system with
the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.

The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP,
48-pin TSOP and 48-ball FBGA packages. Standard control pins- chip enable (CE#), write enable
(WE#), and output enable (OE#)-control normal read and write operations, and avoid bus con-
tention issues.

The device requires only a single 3.0 volt power supply for both read and write functions. In-
ternally generated and regulated voltages are provided for the pro-gram and erase operations.

S29AL032D Features

The Secured Silicon Sector is an extra sector capable of being permanently locked by Spansion
or customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is
factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never
be used to replace a factory locked part. Note that the S29AL032D has a Secured Silicon
Sector size of 128 words (256 bytes).

Factory locked parts provide several options. The Secured Silicon Sector may store a secure, ran-
dom 16 byte ESN (Electronic Serial Number), customer code (programmed through the Spansion
programming service), or both.

The S29AL032D is entirely command set compatible with the JEDEC single-power-supply
Flash standard. Commands are written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Em-
bedded Program algorithm--an internal algorithm that automatically times the program pulse
widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming
times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded
Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not al-
ready programmed) before executing the erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the
RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a pro-
gram or erase cycle has been completed, the device is ready to read array data or accept another
command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.

Hardware data protection measures include a low V

detector that automatically inhibits write

operations during power transitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors of memory. This can be achieved
in-system or via programming equipment.

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11

Table 1. S29AL032D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .11

Word/Byte Configuration (Models 03, 04 Only) . . . . . . . . . . . 11
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . . 11
Writing Commands/Command Sequences . . . . . . . . . . . . . . . 12
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 12
Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . 12
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. Model 00 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Model 00 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 15
Table 4. Model 03 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Model 03 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 17
Table 6. Model 04 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Model 04 Secured Silicon Sector Addresses . . . . . . . . . . . . . . 19

Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. S29AL032D Autoselect Codes (High Voltage Method) . . . . .20

Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Sector Block Addresses for Protection/Unprotection
-- Model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Sector Block Addresses for Protection/Unprotection
-- Model 03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Sector Block Addresses for Protection/Unprotection
-- Model 04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Write Protect (WP#) -- Models 03, 04 Only . . . . . . . . . . . . 23
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . . . . 24
Figure 2. In-System Sector Protect/Unprotect Algorithms. . . . . . . . . . 25

Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . 26

Figure 3. Secured Silicon Sector Protect Verify. . . . . . . . . . . . . . . . . . . 27

Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Common Flash Memory Interface (CFI). . . . . . . 28

Table 12. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . .28
Table 13. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 14. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . 30

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 31

Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32
Enter Secured Silicon

Sector/Exit Secured Silicon Sector

Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Word/Byte Program Command Sequence . . . . . . . . . . . . . . . 32

Figure 4. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 34
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 35

Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . .35

Figure 5. Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 16. S29AL032D Command Definitions -- Model 00 . . . . . . . . . . 37
Table 17. S29AL032D Command Definitions -- Models 03, 04 . . . . . . 38

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 39

DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 6. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 7. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .43
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 45

Figure 8. Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . 45
Figure 9. Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . 45

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Typical I

CC1

vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 12. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Input Waveforms and Measurement Levels . . . . . . . . . . . . . 49

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 14. Read Operations Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 15. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . 52
Figure 17. BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . 53

Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 18. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19. Chip/Sector Erase Operation Timings. . . . . . . . . . . . . . . . . . 56
Figure 20. Back to Back Read/Write Cycle Timing. . . . . . . . . . . . . . . . 56
Figure 21. Data# Polling Timings (During Embedded Algorithms) . . . . 57
Figure 22. Toggle Bit Timings (During Embedded Algorithms) . . . . . . 57
Figure 23. DQ2 vs. DQ6 for Erase and Erase Suspend Operations. . . 58
Figure 24. Temporary Sector Unprotect/Timing Diagram . . . . . . . . . . 58
Figure 25. Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . 59
Figure 26. Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . 59
Figure 27. Alternate CE# Controlled Write Operation Timings. . . . . . 61

Erase and Programming Performance . . . . . . . . 62
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63

TS040--40-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . .63
TS 048--48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . 64
VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA)

10.0 x 6.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 66

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Ordering Information

S29AL032D Standard Products

Spansion standard products are available in several packages and operating
ranges. The order number (Valid Combination) is formed by a combination of the
elements below.

Notes:

1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your

local sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

S29AL032D

PACKING TYPE

= Tray

= 7" Tape and Reel

= 13" Tape and Reel

MODEL NUMBER

= x8, V

= 2.7 V to 3.6 V, Uniform sector device

= x8/x16, V

= 2.7 V to 3.6 V, Top boot sector device, top two address

sectors protected when WP#/ACC = V

= x8/x16, V

= 2.7 V to 3.6 V, Bottom boot sector device, bottom two

address sectors protected when WP#/ACC = V

TEMPERATURE RANGE

I =

Industrial

(40

C to +85

= Engineering Samples (available prior to Production Release only)

PACKAGE MATERIAL SET

= Standard

= Pb-Free

PACKAGE TYPE

= Thin Small Outline Package (TSOP) Standard Pinout

= Fine-pitch Ball-Grid Array Package

SPEED OPTION

See "Product Selector Guide" and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29AL032D
3.0 Volt-only, 32 Megabit Standard Flash Memory
manufactured using 200 nm process technology

S29AL032D Valid Combinations

Package Description

Device Number

Speed

Option

Package Type,

Material, and

Temperature Range

Model

Number

Packing Type

S29AL032D

70, 90

TAI, TFI

0, 3

(Note 1)

TS040

(Note 2)

TSOP

03, 04

TS048

(Note 2)

TSOP

BAI, BFI

00, 03, 04

0, 2, 3

(Note 1)

VBN048

(Note 3)

Fine-Pitch BGA

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is composed of latches that store the commands, along with
the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device.

Table 1

lists the device bus operations, the inputs and control levels they require, and

the resulting output. The following subsections describe each of these operations in further detail.

Table 1. S29AL032D Device Bus Operations

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 12.0 ± 0.5 V, X = Don't Care, A

= Address In, D

= Data In, D

OUT

= Data Out

Notes:
1. When the ACC pin is at V

, the device enters the accelerated program mode. See

2. Addresses are A20:A0 in word mode (BYTE# = V

), A20:A-1 in byte mode (BYTE# = V

3. The sector protect and sector unprotect functions may also be implemented via programming equipment.
4. If WP#/ACC = V

, the two outermost boot sectors remain protected. If WP#/ACC = V

, the two outermost boot sector

protection depends on whether they were last protected or unprotected. If WP#/ACC = V

, all sectors are unprotected.

5. D

or D

OUT

as required by command sequence, data polling, or sector protection algorithm.

6. Models 03, 04 only

Word/Byte Configuration (Models 03, 04 Only)

The BYTE# pin controls whether the device data I/O pins DQ15DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15DQ0
are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0
DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8DQ14 are tri-stated, and
the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V

. CE# is

the power control and selects the device. OE# is the output control and gates array data to the
output pins. WE# should remain at V

. The BYTE# pin determines whether the device outputs

array data in words or bytes.

Operation

CE#

OE# WE#

RESET#

WP#

(Note 6)

ACC

Addresses

(Note 3)

DQ0

DQ7

DQ8DQ15

(Note 6)

BYTE#

= V

BYTE# = V

Read

L/H

OUT

DQ8DQ14 =

High-Z, DQ15 =

A-1

Write

(Note 1)

(Note 4)

(Note 5) (Note 5)

Accelerated Program

(Note 6)

(Note 5) (Note 5)

Standby

0.3 V

High-Z

Output Disable

L/H

High-Z

Reset

L/H

High-Z

Sector Protect

(Note 3)

L/H

SA, A6 = L,

A1 = H, A0 = L

(Note 5)

Sector Unprotect

(Note 3)

(Note 4)

SA, A6 = H,

A1 = H, A0 = L

(Note 5)

Temporary Sector

Unprotect

(Note 4)

(Note 5) (Note 5)

High-Z

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register con-
tents are altered.

See

Reading Array Data on page 31

for more information. Refer to the AC

Read Operations on

page 50

table for timing specifications and to

Figure 14, on page 50

for the timing diagram. I

CC1

in the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive WE# and CE# to V

, and OE# to V

For program operations, the BYTE# pin determines whether the device accepts program data in
bytes or words. Refer to

Word/Byte Configuration (Models 03, 04 Only) on page 11

for more

information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word or byte,
instead of four. The

Word/Byte Program Command Sequence on page 32

section has details on

programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 2 on page 14

and

Table 4 on page 16

indicate the address space that each sector occupies. A sector address

consists of the address bits required to uniquely select a sector. The

Command Definitions on

page 31

contains details on erasing a sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence, the device enters the autoselect
mode. The system can then read autoselect codes from the internal register (which is separate
from the memory array) on DQ7DQ0. Standard read cycle timings apply in this mode. Refer to

Autoselect Mode on page 20

and

Autoselect Command Sequence on page 32

for more

information.

CC2

in the DC Characteristics table represents the active current specification for the write mode.

AC Characteristics on page 50

contains timing specification tables and timing diagrams for write

operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by read-
ing the status bits on DQ7DQ0. Standard read cycle timings and I

read specifications apply.

Refer to

Write Operation Status on page 39

for more information, and to

AC Characteristics on

page 50

for timing diagrams.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two
functions provided by the WP#/ACC (ACC on Model 00) pin. This function is primarily intended to
allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the device automatically enters the aforementioned Unlock

Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the
pin to reduce the time required for program operations. The system would use a two-cycle pro-
gram command sequence as required by the Unlock Bypass mode. Removing V

from the WP#/

ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at V

for operations other than accelerated programming, or device damage may result. In addition,

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3 V. (Note that this is a more restricted voltage range than V

.) If CE# and RESET# are held

at V

, but not within V

± 0.3 V, the device will be in the standby mode, but the standby current

will be greater. The device requires standard access time (t

) for read access when the device is

in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.

In the

DC Characteristics

table, I

CC3

and I

CC4

represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is

independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. I

CC4

DC Characteristics on page 46

represents the automatic sleep

mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When
the system drives the RESET# pin to V

for at least a period of t

, the device immediately ter-

minates any operation in progress, tristates all data output pins, and ignores all read/write
attempts for the duration of the RESET# pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

±0.3 V, the

device draws CMOS standby current (I

CC4

). If RESET# is held at V

but not within V

±0.3 V, the

standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy)
until the internal reset operation is complete, which requires a time of t

READY

(during Embedded

Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is
complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin
is 1), the reset operation is completed within a time of t

READY

(not during Embedded Algorithms).

The system can read data t

after the RESET# pin returns to V

Refer to

AC Characteristics on page 50

for RESET# parameters and to

Figure 15, on page 51

for

the timing diagram.

Output Disable Mode

When the OE# input is at V

, output from the device is disabled. The output pins are placed in

the high impedance state.

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Table 4. Model 03 Sector Addresses (Sheet 1 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000xxx

64/32

000000h00FFFFh

000000h07FFFh

SA1

000001xxx

64/32

010000h01FFFFh

008000h0FFFFh

SA2

000010xxx

64/32

020000h02FFFFh

010000h17FFFh

SA3

000011xxx

64/32

030000h03FFFFh

018000h01FFFFh

SA4

000100xxx

64/32

040000h04FFFFh

020000h027FFFh

SA5

000101xxx

64/32

050000h05FFFFh

028000h02FFFFh

SA6

000110xxx

64/32

060000h06FFFFh

030000h037FFFh

SA7

000111xxx

64/32

070000h07FFFFh

038000h03FFFFh

SA8

001000xxx

64/32

080000h08FFFFh

040000h047FFFh

SA9

001001xxx

64/32

090000h09FFFFh

048000h04FFFFh

SA10

001010xxx

64/32

0A0000h0AFFFFh

050000h057FFFh

SA11

001011xxx

64/32

0B0000h0BFFFFh

058000h05FFFFh

SA12

001100xxx

64/32

0C0000h0CFFFFh

060000h067FFFh

SA13

001101xxx

64/32

0D0000h0DFFFFh

068000h06FFFFh

SA14

001110xxx

64/32

0E0000h0EFFFFh

070000h077FFFh

SA15

001111xxx

64/32

0F0000h0FFFFFh

078000h07FFFFh

SA16

010000xxx

64/32

100000h10FFFFh

080000h087FFFh

SA17

010001xxx

64/32

110000h11FFFFh

088000h08FFFFh

SA18

010010xxx

64/32

120000h12FFFFh

090000h097FFFh

SA19

010011xxx

64/32

130000h13FFFFh

098000h09FFFFh

SA20

010100xxx

64/32

140000h14FFFFh

0A0000h0A7FFFh

SA21

010101xxx

64/32

150000h15FFFFh

0A8000h0AFFFFh

SA22

010110xxx

64/32

160000h16FFFFh

0B0000h0B7FFFh

SA23

010111xxx

64/32

170000h17FFFFh

0B8000h0BFFFFh

SA24

011000xxx

64/32

180000h18FFFFh

0C0000h0C7FFFh

SA25

011001xxx

64/32

190000h19FFFFh

0C8000h0CFFFFh

SA26

011010xxx

64/32

1A0000h1AFFFFh

0D0000h0D7FFFh

SA27

011011xxx

64/32

1B0000h1BFFFFh

0D8000h0DFFFFh

SA28

011100xxx

64/32

1C0000h1CFFFFh

0E0000h0E7FFFh

SA29

011101xxx

64/32

1D0000h1DFFFFh

0E8000h0EFFFFh

SA30

011110xxx

64/32

1E0000h1EFFFFh

0F0000h0F7FFFh

SA31

011111xxx

64/32

1F0000h1FFFFFh

0F8000h0FFFFFh

SA32

100000xxx

64/32

200000h20FFFFh

100000h107FFFh

SA33

100001xxx

64/32

210000h21FFFFh

108000h10FFFFh

SA34

100010xxx

64/32

220000h22FFFFh

110000h117FFFh

SA35

100011xxx

64/32

230000h23FFFFh

118000h11FFFFh

SA36

100100xxx

64/32

240000h24FFFFh

120000h127FFFh

SA37

100101xxx

64/32

250000h25FFFFh

128000h12FFFFh

SA38

100110xxx

64/32

260000h26FFFFh

130000h137FFFh

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Note: The address range is A20:A-1 in byte mode (BYTE#=V

) or A20:A0 in word mode (BYTE#=V

Table 5. Model 03 Secured Silicon Sector Addresses

SA39

100111xxx

64/32

270000h27FFFFh

138000h13FFFFh

SA40

101000xxx

64/32

280000h28FFFFh

140000h147FFFh

SA41

101001xxx

64/32

290000h29FFFFh

148000h14FFFFh

SA42

101010xxx

64/32

2A0000h2AFFFFh

150000h157FFFh

SA43

101011xxx

64/32

2B0000h2BFFFFh

158000h15FFFFh

SA44

101100xxx

64/32

2C0000h2CFFFFh

160000h167FFFh

SA45

101101xxx

64/32

2D0000h2DFFFFh

168000h16FFFFh

SA46

101110xxx

64/32

2E0000h2EFFFFh

170000h177FFFh

SA47

101111xxx

64/32

2F0000h2FFFFFh

178000h17FFFFh

SA48

110000xxx

64/32

300000h30FFFFh

180000h187FFFh

SA49

110001xxx

64/32

310000h31FFFFh

188000h18FFFFh

SA50

110010xxx

64/32

320000h32FFFFh

190000h197FFFh

SA51

110011xxx

64/32

330000h33FFFFh

198000h19FFFFh

SA52

110100xxx

64/32

340000h34FFFFh

1A0000h1A7FFFh

SA53

110101xxx

64/32

350000h35FFFFh

1A8000h1AFFFFh

SA54

110110xxx

64/32

360000h36FFFFh

1B0000h1B7FFFh

SA55

110111xxx

64/32

370000h37FFFFh

1B8000h1BFFFFh

SA56

111000xxx

64/32

380000h38FFFFh

1C0000h1C7FFFh

SA57

111001xxx

64/32

390000h39FFFFh

1C8000h1CFFFFh

SA58

111010xxx

64/32

3A0000h3AFFFFh

1D0000h1D7FFFh

SA59

111011xxx

64/32

3B0000h3BFFFFh

1D8000h1DFFFFh

SA60

111100xxx

64/32

3C0000h3CFFFFh

1E0000h1E7FFFh

SA61

111101xxx

64/32

3D0000h3DFFFFh

1E8000h1EFFFFh

SA62

111110xxx

64/32

3E0000h3EFFFFh

1F0000h1F7FFFh

SA63

111111000

8/4

3F0000h3F1FFFh

1F8000h1F8FFFh

SA64

111111001

8/4

3F2000h3F3FFFh

1F9000h1F9FFFh

SA65

111111010

8/4

3F4000h3F5FFFh

1FA000h1FAFFFh

SA66

111111011

8/4

3F6000h3F7FFFh

1FB000h1FBFFFh

SA67

111111100

8/4

3F8000h3F9FFFh

1FC000h1FCFFFh

SA68

111111101

8/4

3FA000h3FBFFFh

1FD000h1FDFFFh

SA69

111111110

8/4

3FC000h3FDFFFh

1FE000h1FEFFFh

SA70

111111111

8/4

3FE000h3FFFFFh

1FF000h1FFFFFh

Sector Address

A20A12

Sector Size

(bytes/words)

(x8)

Address Range

(x16)

Address Range

111111111

256/128

3FFF00h3FFFFFh

1FFF80h1FFFFFh

Table 4. Model 03 Sector Addresses (Sheet 2 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Table 6. Model 04 Sector Addresses (Sheet 1 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

SA0

000000000

8/4

000000h-001FFFh

000000h000FFFh

SA1

000000001

8/4

002000h-003FFFh

001000h001FFFh

SA2

000000010

8/4

004000h-005FFFh

002000h002FFFh

SA3

000000011

8/4

006000h-007FFFh

003000h003FFFh

SA4

000000100

8/4

008000h-009FFFh

004000h004FFFh

SA5

000000101

8/4

00A000h-00BFFFh

005000h005FFFh

SA6

000000110

8/4

00C000h-00DFFFh

006000h006FFFh

SA7

000000111

8/4

00E000h-00FFFFh

007000h007FFFh

SA8

000001xxx

64/32

010000h-01FFFFh

008000h00FFFFh

SA9

000010xxx

64/32

020000h-02FFFFh

010000h017FFFh

SA10

000011xxx

64/32

030000h-03FFFFh

018000h01FFFFh

SA11

000100xxx

64/32

040000h-04FFFFh

020000h027FFFh

SA12

000101xxx

64/32

050000h-05FFFFh

028000h02FFFFh

SA13

000110xxx

64/32

060000h-06FFFFh

030000h037FFFh

SA14

000111xxx

64/32

070000h-07FFFFh

038000h03FFFFh

SA15

001000xxx

64/32

080000h-08FFFFh

040000h047FFFh

SA16

001001xxx

64/32

090000h-09FFFFh

048000h04FFFFh

SA17

001010xxx

64/32

0A0000h-0AFFFFh

050000h057FFFh

SA18

001011xxx

64/32

0B0000h-0BFFFFh

058000h05FFFFh

SA19

001100xxx

64/32

0C0000h-0CFFFFh

060000h067FFFh

SA20

001101xxx

64/32

0D0000h-0DFFFFh

068000h06FFFFh

SA21

001110xxx

64/32

0E0000h-0EFFFFh

070000h077FFFh

SA22

001111xxx

64/32

0F0000h-0FFFFFh

078000h07FFFFh

SA23

010000xxx

64/32

100000h-10FFFFh

080000h087FFFh

SA24

010001xxx

64/32

110000h-11FFFFh

088000h08FFFFh

SA25

010010xxx

64/32

120000h-12FFFFh

090000h097FFFh

SA26

010011xxx

64/32

130000h-13FFFFh

098000h09FFFFh

SA27

010100xxx

64/32

140000h-14FFFFh

0A0000h0A7FFFh

SA28

010101xxx

64/32

150000h-15FFFFh

0A8000h0AFFFFh

SA29

010110xxx

64/32

160000h-16FFFFh

0B0000h0B7FFFh

SA30

010111xxx

64/32

170000h-17FFFFh

0B8000h0BFFFFh

SA31

011000xxx

64/32

180000h-18FFFFh

0C0000h0C7FFFh

SA32

011001xxx

64/32

190000h-19FFFFh

0C8000h0CFFFFh

SA33

011010xxx

64/32

1A0000h-1AFFFFh

0D0000h0D7FFFh

SA34

011011xxx

64/32

1B0000h-1BFFFFh

0D8000h0DFFFFh

SA35

011100xxx

64/32

1C0000h-1CFFFFh

0E0000h0E7FFFh

SA36

011101xxx

64/32

1D0000h-1DFFFFh

0E8000h0EFFFFh

SA37

011110xxx

64/32

1E0000h-1EFFFFh

0F0000h0F7FFFh

SA38

011111xxx

64/32

1F0000h-1FFFFFh

0F8000h0FFFFFh

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Note: The address range is A20:A-1 in byte mode (BYTE#=V

) or A20:A0 in word mode (BYTE#=V

Table 7. Model 04 Secured Silicon Sector Addresses

SA39

100000xxx

64/32

200000h-20FFFFh

100000h107FFFh

SA40

100001xxx

64/32

210000h-21FFFFh

108000h10FFFFh

SA41

100010xxx

64/32

220000h-22FFFFh

110000h117FFFh

SA42

100011xxx

64/32

230000h-23FFFFh

118000h11FFFFh

SA43

100100xxx

64/32

240000h-24FFFFh

120000h127FFFh

SA44

100101xxx

64/32

250000h-25FFFFh

128000h12FFFFh

SA45

100110xxx

64/32

260000h-26FFFFh

130000h137FFFh

SA46

100111xxx

64/32

270000h-27FFFFh

138000h13FFFFh

SA47

101000xxx

64/32

280000h-28FFFFh

140000h147FFFh

SA48

101001xxx

64/32

290000h-29FFFFh

148000h14FFFFh

SA49

101010xxx

64/32

2A0000h-2AFFFFh

150000h157FFFh

SA50

101011xxx

64/32

2B0000h-2BFFFFh

158000h15FFFFh

SA51

101100xxx

64/32

2C0000h-2CFFFFh

160000h167FFFh

SA52

101101xxx

64/32

2D0000h-2DFFFFh

168000h16FFFFh

SA53

101110xxx

64/32

2E0000h-2EFFFFh

170000h177FFFh

SA54

101111xxx

64/32

2F0000h-2FFFFFh

178000h17FFFFh

SA55

111000xxx

64/32

300000h-30FFFFh

180000h187FFFh

SA56

110001xxx

64/32

310000h-31FFFFh

188000h18FFFFh

SA57

110010xxx

64/32

320000h-32FFFFh

190000h197FFFh

SA58

110011xxx

64/32

330000h-33FFFFh

198000h19FFFFh

SA59

110100xxx

64/32

340000h-34FFFFh

1A0000h1A7FFFh

SA60

110101xxx

64/32

350000h-35FFFFh

1A8000h1AFFFFh

SA61

110110xxx

64/32

360000h-36FFFFh

1B0000h1B7FFFh

SA62

110111xxx

64/32

370000h-37FFFFh

1B8000h1BFFFFh

SA63

111000xxx

64/32

380000h-38FFFFh

1C0000h1C7FFFh

SA64

111001xxx

64/32

390000h-39FFFFh

1C8000h1CFFFFh

SA65

111010xxx

64/32

3A0000h-3AFFFFh

1D0000h1D7FFFh

SA66

111011xxx

64/32

3B0000h-3BFFFFh

1D8000h1DFFFFh

SA67

111100xxx

64/32

3C0000h-3CFFFFh

1E0000h1E7FFFh

SA68

111101xxx

64/32

3D0000h-3DFFFFh

1E8000h1EFFFFh

SA69

111110xxx

64/32

3E0000h-3EFFFFh

1F0000h1F7FFFh

SA70

111111xxx

64/32

3F0000h-3FFFFFh

1F8000h1FFFFFh

Sector Address

A20A12

Sector Size

(bytes/words)

(x8)

Address Range

(x16)

Address Range

000000000

256/128

000000h-0000FFh

00000h-0007Fh

Table 6. Model 04 Sector Addresses (Sheet 2 of 2)

Sector

Sector Address

A20A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection ver-
ification, through identifier codes output on DQ7DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its correspond-
ing programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect mode requires V

(11.5 V to 12.5 V) on

address pin A9. Address pins A6, A1, and A0 must be as shown in

Table 8

. In addition, when ver-

ifying sector protection, the sector address must appear on the appropriate highest order address
bits (see

Table 2 on page 14

and

Table 4 on page 16

Table 8

shows the remaining address bits

that are don't care. When all necessary bits have been set as required, the programming equip-
ment may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via
the command register, as shown in

Table 17 on page 38

. This method does not require V

. See

"Command Definitions" for details on using the autoselect mode.

Table 8. S29AL032D Autoselect Codes (High Voltage Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don't care.

Note: The autoselect codes may also be accessed in-system via command sequences. See

Table 17 on page 38

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotection feature re-enables both program and erase operations in pre-
viously protected sectors.

Description

Mode

CE#

OE#

WE#

A19

A12

A11

A10

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: Spansion

01h

Device ID:

S29AL032D

(Model 00)

Byte

N/A

A3h

Device ID:

S29AL032D

(Model 03)

Word

22h

F6h

Byte

F6h

Device ID:

S29AL032D

(Model 04)

Word

22h

F9h

Byte

F9h

Sector Protection

Verification

01h (protected)

00h

(unprotected)

Secured Silicon Sector

Indicator Bit (DQ7)
(Model 00)

85 (factory

locked)

05 (not factory

locked)

Secured Silicon Sector

Indicator Bit (DQ7)
(Model 03)

8D (factory

locked)

0D (not factory

locked)

Secured Silicon Sector

Indicator Bit (DQ7)
(Model 04)

9D (factory

locked)

1D (not factory

locked)

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

The device is shipped with all sectors unprotected. Spansion offers the option of programming
and protecting sectors at its factory prior to shipping the device through the Spansion Express-
FlashTM Service. Contact a Spansion representative for further details.

It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode"
for details.

Sector protection/unprotection can be implemented via two methods.

The primary method requires V

on the RESET# pin only, and can be implemented either in-sys-

tem or via programming equipment.

Figure 2, on page 25

shows the algorithms and

Figure 26,

on page 59

shows the timing diagram. This method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.

The alternate method intended only for programming equipment requires V

on address pin A9

and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only
Spansion flash devices. Details on this method are provided in a supplement, publication number
21468. Contact a Spansion representative to request a copy.

Table 9. Sector Block Addresses for Protection/Unprotection -- Model 00

Sector/Sector Block

A21A16

Sector/Sector Block Size

SA0

000000

64 Kbytes

SA1-SA3

000001,000010,

000011

192 (3x64) Kbytes

SA4-SA7

000100, 000101,

000110, 000111

256 (4x64) Kbytes

SA8-SA11

001000, 001001,

001010, 001011

256 (4x64) Kbytes

SA12-SA15

001100, 001101,

001110, 001111

256 (4x64) Kbytes

SA16-SA19

010000, 010001,

010010, 010011

256 (4x64) Kbytes

SA20-SA23

010100, 010101,

010110, 010111

256 (4x64) Kbytes

SA24-SA27

011000, 011001,

011010, 011011

256 (4x64) Kbytes

SA28-SA31

011100, 011101,

011110, 011111

256 (4x64) Kbytes

SA32-SA35

100000, 100001,

100010, 100011

256 (4x64) Kbytes

SA36-SA39

100100, 100101,

100110, 100111

256 (4x64) Kbytes

SA40-SA43

101000, 101001,

101010, 101011

256 (4x64) Kbytes

SA44-SA47

101100, 101101,

101110, 101111

256 (4x64) Kbytes

SA48-SA51

110000, 110001,

110010, 110011

256 (4x64) Kbytes

SA52-SA55

110100, 110101,

110110, 110111

256 (4x64) Kbytes

SA56-SA59

111000, 111001,

111010, 111011

256 (4x64) Kbytes

SA60-SA62

111100, 111101,

111110

192 (4x64) Kbytes

SA63

111111

64 Kbytes

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A d v a n c e I n f o r m a t i o n

Write Protect (WP#) -- Models 03, 04 Only

The Write Protect function provides a hardware method of protecting certain boot sectors without
using V

. This function is one of two provided by the WP#/ACC pin.

If the system asserts V

on the WP#/ACC pin, the device disables program and erase functions

in the two outermost 8 Kbyte boot sectors independently of whether those sectors were protected
or unprotected using the method described in

Sector Protection/Unprotection on page 20

. The

two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bot-
tom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-
configured device.

If the system asserts V

on the WP#/ACC pin, the device reverts to whether the two outermost

8K Byte boot sectors were last set to be protected or unprotected. That is, sector protection or
unprotection for these two sectors depends on whether they were last protected or unprotected
using the method described in

Sector Protection/Unprotection on page 20

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the
device may result.

Table 11. Sector Block Addresses for Protection/Unprotection -- Model 04

Sector / Sector Block

A20A12

Sector/Sector Block Size

SA70-SA67

111111XXX,

111110XXX,

111101XXX,

111100XXX

256 (4x64) Kbytes

SA66-SA63

1110XXXXX

256 (4x64) Kbytes

SA62-SA59

1101XXXXX

256 (4x64) Kbytes

SA58-SA55

1100XXXXX

256 (4x64) Kbytes

SA54-SA51

1011XXXXX

256 (4x64) Kbytes

SA50-SA47

1010XXXXX

256 (4x64) Kbytes

SA46-SA43

1001XXXXX

256 (4x64) Kbytes

SA42-SA39

1000XXXXX

256 (4x64) Kbytes

SA38-SA35

0111XXXXX

256 (4x64) Kbytes

SA34-SA31

0110XXXXX

256 (4x64) Kbytes

SA30-SA27

0101XXXXX

256 (4x64) Kbytes

SA26-SA23

0100XXXXX

256 (4x64) Kbytes

SA22SA19

0011XXXXX

256 (4x64) Kbytes

SA18-SA15

0010XXXXX

256 (4x64) Kbytes

SA14-SA11

0001XXXXX

256 (4x64) Kbytes

SA10-SA8

000011XXX,

000010XXX,

000001XXX

192 (3x64) Kbytes

SA7

000000111

8 Kbytes

SA6

000000110

8 Kbytes

SA5

000000101

8 Kbytes

SA4

000000100

8 Kbytes

SA3

000000011

8 Kbytes

SA2

000000010

8 Kbytes

SA1

000000001

8 Kbytes

SA0

000000000

8 Kbytes

S29AL032D

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A d v a n c e I n f o r m a t i o n

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a 256 byte Flash memory region that enables per-
manent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector
uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon
Sector is locked when shipped from the factory. This bit is permanently set at the factory and can-
not be changed, which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field.

Spansion offers the device with the Secured Silicon Sector either factory locked or customer lock-
able. The factory-locked version is always protected when shipped from the factory, and has the
Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is
shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector
in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indi-
cator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents
customer-lockable devices from being used to replace devices that are factory locked.

The system accesses the Secured Silicon Sector through a command sequence (see

Enter Se-

cured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 32

). After the

system writes the Enter Secured Silicon Sector command sequence, it may read the Secured Sil-
icon Sector by using the addresses normally occupied by the boot sectors. This mode of operation
continues until the system issues the Exit Secured Silicon Sector command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts
to sending commands to the boot sectors.

Factory Locked: Secured Silicon Sector Programmed

and Protected at the Factory

In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from
the factory. The Secured Silicon Sector cannot be modified in any way. The device is available pre-
programmed with one of the following:

A random, secure ESN only
Customer code through the ExpressFlash service
Both a random, secure ESN and customer code through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at
addresses 00000h0000Fh in byte mode (or 00000h00007h in word mode). In the Top Boot de-
vice the ESN is in sector 70 at addresses 3FFF00h3FFF0Fh in byte mode (or 1FFF80h1FFF87h
in word mode). In the Uniform device the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in
byte mode (or 1FFF80h-1FFF87h in word mode).

Customers may opt to have their code programmed by Spansion through the Spansion Express-
Flash service. Spansion programs the customer's code, with or without the random ESN. The
devices are then shipped from the Spansion factory with the Secured Silicon Sector permanently
locked. Contact a Spansion representative for details on using the Spansion ExpressFlash service.

Customer Lockable: Secured Silicon Sector NOT Programmed

or Protected at the Factory

The customer lockable version allows the Secured Silicon Sector to be programmed once and then
permanently locked after it ships from Spansion. Note that the accelerated programming (ACC)
and unlock bypass functions are not available when programming the Secured Silicon Sector.

The Secured Silicon Sector area can be protected using the following procedures:

Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the
in-system sector protect algorithm as shown in

Figure 2, on page 25

, except that RESET#

may be at either V

or V

. This allows in-system protection of the Secured Silicon Sector

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A d v a n c e I n f o r m a t i o n

without raising any device pin to a high voltage. Note that this method is only applicable to
the Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm
shown in

Figure 3, on page 27

Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured
Silicon Sector Region command sequence to return to reading and writing the remainder of the
array.

The Secured Silicon Sector protection must be used with caution since, once protected, there is
no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in
the Secured Silicon Sector memory space can be modified in any way.

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to

Table 17 on page 38

for command definitions). In

addition, the following hardware data protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spurious system level signals during V

power-up and power-down transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept any write cycles. This protects data during

power-up and power-down. The command register and all internal program/erase circuits are

disabled, and the device resets. Subsequent writes are ignored until V

is greater than V

LKO

. The

system must provide the proper signals to the control pins to prevent unintentional writes when
V

is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = V

or WE# = V

. To initiate

a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

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A d v a n c e I n f o r m a t i o n

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up, the device does not accept commands on

the rising edge of WE#. The internal state machine is automatically reset to reading array data
on power-up.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read
array data. The system can read CFI information at the addresses given in Tables

. In word

mode, the upper address bits (A7MSB) must be all zeros. To terminate reading CFI data, the
system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode.
The device enters the CFI query mode, and the system can read CFI data at the addresses given
in Tables

. The system must write the reset command to return the device to the autoselect

mode.

For further information, please contact a Spansion representative for a copy of this document.

Table 12. CFI Query Identification String

Addresses

(Models 03, 04

Byte Mode

Only)

Data

Description

10h
11h
12h

20h
22h
24h

0051h
0052h
0059h

Query Unique ASCII string QRY

13h
14h

26h
28h

0002h
0000h

Primary OEM Command Set

15h
16h

2Ah
2Ch

0040h
0000h

Address for Primary Extended Table

17h
18h

2Eh
30h

0000h
0000h

Alternate OEM Command Set (00h = none exists)

19h
1Ah

32h
34h

0000h
0000h

Address for Alternate OEM Extended Table (00h = none exists)

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Table 14. Device Geometry Definition

Addresses

(Models 03, 04

Byte Mode

Only)

Data

Description

27h

4Eh

0016h

Device Size = 2

byte

28h
29h

50h
52h

000xh
0000h

Flash Device Interface description (refer to CFI publication 100)

(0 = Model 00, 2 = Models 03, 04)

2Ah
2Bh

54h
56h

0000h
0000h

Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch

58h

000xh

Number of Erase Block Regions within device

(1 = Model 00, 2 = Models 03, 04)

2Dh

2Eh
2Fh
30h

5Ah
5Ch
5Eh
60h

00xxh

0000h
00x0h
000xh

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

(003F, 0000, 0000, 0001) = Model 00
(0007, 0000, 0020, 0000) = Models 03, 04

31h
32h
33h
34h

62h
64h
66h
68h

00xxh

0000h
0020h
000xh

Erase Block Region 2 Information

(0000, 0000, 0000, 0000) = Model 00
(003E, 0000, 0000, 0001) = Models 03, 04

35h
36h
37h
38h

6Ah
6Ch
6Eh
70h

0000h
0000h
0000h
0000h

Erase Block Region 3 Information

39h
3Ah
3Bh
3Ch

72h
74h
76h
78h

0000h
0000h
0000h
0000h

Erase Block Region 4 Information

Table 15. Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Addresses

(Models 03, 04

Byte Mode

Only)

Data

Description

40h
41h
42h

80h
82h
84h

0050h
0052h
0049h

Query-unique ASCII string "PRI"

43h

86h

0031h

Major version number, ASCII

44h

88h

0031h

Minor version number, ASCII

45h

8Ah

000xh

Address Sensitive Unlock

0 = Required (Models 03, 04), 1 = Not Required (Model 00)

46h

8Ch

0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h

8Eh

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

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Command Definitions

Writing specific address and data commands or sequences into the command register initiates
device operations.

Table 17 on page 38

defines the valid register command sequences. Writing

incorrect address and data values or writing them in the improper sequence resets the de-
vice to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate tim-
ing diagrams in the "AC Characteristics" section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embed-
ded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an ad-
dress within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data
with the same exception. See

Erase Suspend/Erase Resume Commands on page 35

for more in-

formation on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See the

Reset Command on page 32

section, next.

See also

Requirements for Reading Array Data on page 11

for more information. The

Read

Operations on page 50

provides the read parameters, and

Figure 14, on page 50

shows the timing

diagram.

48h

90h

0001h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h

92h

0004h

Sector Protect/Unprotect scheme

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

4Ah

94h

0000h

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Bh

96h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch

98h

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh

9Ah

00B5h

ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh

9Ch

00C5h

ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh

9Eh

000xh

Top/Bottom Boot Sector Flag
(0 = Model 00, 2 = Model 03, 3 = Model 04)

Table 15. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses

(Models 03, 04

Byte Mode

Only)

Data

Description

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A d v a n c e I n f o r m a t i o n

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are
don't care for this command.

The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however,
the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command se-
quence before programming begins. This resets the device to reading array data (also applies to
programming in Erase Suspend mode). Once programming begins, however, the device ignores
reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be written to return to reading
array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and de-
vices codes, and determine whether a sector is protected.

Table 17 on page 38

shows the address

and data requirements. This method is an alternative to that shown in

Table 8 on page 20

, which

is intended for PROM programmers and requires V

on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the au-
toselect command. The device then enters the autoselect mode, and the system may read at any
address any number of times, without initiating another command sequence.

A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address
0XXX01h returns the device code. A read cycle containing a sector address (SA) and the address
02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to

Table 2 on page 14

and

Table 4 on page 16

for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading
array data.

Enter Secured Silicon

Sector/Exit Secured Silicon Sector

Command Sequence

The Secured Silicon Sector region provides a secured data area containing a random, sixteen-
byte electronic serial number (ESN). The system can access the Secured Silicon Sector region by
issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to
access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Sili-
con Sector command sequence. The Exit Secured Silicon Sector command sequence returns the
device to normal operation.

Table 16. S29AL032D Command Definitions -- Model 00 on page 37

and

Table 17. S29AL032D Command Definitions -- Models 03, 04 on page 38

show the ad-

dresses and data requirements for both command sequences. Note that the ACC function and
unlock bypass modes are not available when the device enters the Secured Silicon Sector. See
also

Secured Silicon Sector Flash Memory Region on page 26

for further information.

Word/Byte Program Command Sequence

Models 03, 04 may program the device by word or byte, depending on the state of the BYTE#
pin. Model 00 may program the device by byte only. Programming is a four-bus-cycle operation.
The program command sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which in turn initiate

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the Embedded Program algorithm. The system is not required to provide further controls or tim-
ings. The device automatically generates the program pulses and verifies the programmed cell
margin.

Table 17 on page 38

shows the address and data requirements for the byte program

command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array
data and addresses are no longer latched. The system can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. See

Write Operation Status on page 39

for information

on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note
that a hardware reset immediately terminates the programming operation. The Byte Program
command sequence should be reinitiated once the device has reset to reading array data, to en-
sure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be pro-
grammed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1,
or cause the Data# Polling algorithm to indicate the operation was successful. However, a suc-
ceeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the device faster than
using the standard program command sequence. The unlock bypass command sequence is initi-
ated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock
bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second cycle contains
the program address and data. Additional data is programmed in the same manner. This mode
dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time.

Table 17 on page 38

shows the requirements for the

command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don't care for both cycles. The device then returns to reading array data.

Figure 4, on page 34

illustrates the algorithm for the program operation. See the

Erase/Program

Operations on page 54

for parameters, and to

Figure 18, on page 55

for timing diagrams.

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NOTE: See

Table 17

for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations.

Table 17 on page 38

shows the address and data requirements for the chip erase

command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that
a hardware reset during the chip erase operation immediately terminates the operation. The
Chip Erase command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#.
See

Write Operation Status on page 39

for information on these status bits. When the Embedded

Erase algorithm is complete, the device returns to reading array data and addresses are no longer
latched.

Figure 5, on page 36

illustrates the algorithm for the erase operation. See

Erase/Program

Operations on page 54

for parameters, and to

Figure 19, on page 56

for timing diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the address of the sector to be erased, and the sector erase command.

Table 17 on

page 38

shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram the memory prior to erase. The Embedded
Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior
to electrical erase. The system is not required to provide any controls or timings during these
operations.

After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-
out period, additional sector addresses and sector erase commands may be written. Loading the
sector erase buffer may be done in any sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise
the last address and command might not be accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be less than 50 µs, the system need not
monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-
out period resets the device to reading array data. The system must rewrite the command
sequence and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3:
Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in
the command sequence.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. Note that a hardware reset during the sector erase operation immedi-
ately terminates the operation. The Sector Erase command sequence should be reinitiated once
the device has returned to reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these
status bits.)

Figure 5, on page 36

illustrates the algorithm for the erase operation. Refer to

Erase/Program

Operations on page 54

for parameters, and to

Figure 19, on page 56

for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. This command is valid
only during the sector erase operation, including the 50 µs time-out period during the sector erase
command sequence. The Erase Suspend command is ignored if written during the chip erase op-
eration or Embedded Program algorithm. Writing the Erase Suspend command during the Sector
Erase time-out immediately terminates the time-out period and suspends the erase operation.
Addresses are don't-cares when writing the Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires
a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command
is written during the sector erase time-out, the device immediately terminates the time-out pe-
riod and suspends the erase operation.

After the erase operation has been suspended, the system can read array data from or program
data to any sector not selected for erasure. (The device erase suspends all sectors selected for
erasure.) Normal read and write timings and command definitions apply. Reading at any address

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Command Definitions

Table 16. S29AL032D Command Definitions -- Model 00

Legend:

X = Don't care, RA = Address of the memory location to be read, RD = Data read from location RA during read operation,
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE#
pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address
of the sector to be erased or verified. Address bits A21A16 uniquely select any sector.

Notes:
1. See

Table 1 on page 11

for descriptions of bus operations.

2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in read mode.
6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high.
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. In the third and fourth cycles of the command sequence, set A21 to 0.
9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 031, or to 1 if verifying

sectors 3264. The data in the fourth cycle is 00h for an unprotected sector/sector block and 01h for a protected sector/
sector block.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode.
12. The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the Erase

Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

13. The Erase Resume command is valid only during the Erase Suspend mode.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. The data is 85h for factory locked and 05h for not factory locked.

Command Sequence

(Note 1)

Cyc

l
e

Bus Cycles (Notes 24)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

(Note 5)

Reset

(Note 7)

XXX

t
e 7

)

Manufacturer ID

(Note 8)

XXX

0XXXXX

0XXX00

Device ID

(Note 8)

XXX

0XXXXX

0XXX01

Secured Silicon Sector Factory

Protect

(Note 15)

AAA

555

AAA

X06

85/05

Sector Protect Verify

(Note 9)

XXX

0XXXXX

2XXXXX

X02

XXX

Enter Secured Silicon Sector Region

XXX

Exit Secured Silicon Sector Region

XXX

Byte Program

XXX

Unlock Bypass

XXX

Unlock Bypass Program

(Note 10)

XXX

Unlock Bypass Reset

(Note 11)

XXX

Chip Erase

XXX

Sector Erase

XXX

Erase Suspend

(Note 12)

XXX

Erase Resume

(Note 13)

XXX

CFI Query

(Note 14)

XXX

S29AL032D

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A d v a n c e I n f o r m a t i o n

Table 17. S29AL032D Command Definitions -- Models 03, 04

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19A12 uniquely select any sector.

Command

Sequence

(Note 1)

c
l
e

Bus Cycles (Notes 25)

First

Second

Third

Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data Addr

Data

Addr Data

Addr

Data

Read

(Note 6)

Reset

(Note 7)

XXX

u
t
o
sel

e
ct

(No

t
e
8)

Manufacturer ID

Word

555

2AA

555

X00

Byte

AAA

555

AAA

Device ID,

Model 03

Word

555

2AA

555

X01

22F6

Byte

AAA

555

AAA

X02

Device ID,

Model 04

Word

555

2AA

555

X01

22F9

Byte

AAA

555

AAA

X02

Secured Silicon Sector

Factory Protect
Model 03,

(Note 9)

Word

555

2AA

555

X03

8D/0D

Byte

AAA

555

AAA

X06

Secured Silicon Sector

Factory Protect
Model 04,

(Note 9)

Word

555

2AA

555

X03

9D/1D

Byte

AAA

555

AAA

X06

Sector Protect Verify

(Note 10)

Word

555

2AA

555

(SA)

X02

XX00
XX01

Byte

AAA

555

AAA

(SA)

X04

00
01

Enter Secured Silicon Sector

Region

Word

555

2AA

555

Byte

AAA

555

AAA

Exit Secured Silicon Sector

Region

Word

555

2AA

555

XXX

Byte

AAA

555

AAA

CFI Query

(Note 11)

Word

Byte

Program

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass Program

(Note 12)

XXX

Unlock Bypass Reset

(Note 13)

XXX

Chip Erase

Word

555

2AA

555

2AA

555

Byte

AAA

555

AAA

555

AAA

Sector Erase

Word

555

2AA

555

2AA

Byte

AAA

555

AAA

555

Erase Suspend

(Note 14)

XXX

Erase Resume

(Note 15)

XXX

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A d v a n c e I n f o r m a t i o n

Notes:

1. See

Table 1 on page 11

for description of bus operations.

2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15DQ8 are don't cares for unlock and command cycles.
5. Address bits A19A11 are don't cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device

is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.
9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh

for not factory locked.

10. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also

acceptable.

14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase

Suspend command is valid only during a sector erase operation.

15. The Erase Resume command is valid only during the Erase Suspend mode.

Write Operation Status

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5,
DQ6, DQ7, and RY/BY#.

Table 18 on page 44

and the following subsections describe the functions

of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or
erase operation is complete or in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in
progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the
rising edge of the final WE# pulse in the program or erase command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 µs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling pro-
duces a 1 on DQ7. This is analogous to the complement/true datum output described for the
Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to
this, the device outputs the complement, or 0. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the complement to true data, it can read valid
data at DQ7DQ0 on the following read cycles. This is because DQ7 may change asynchronously
with DQ0DQ6 while Output Enable (OE#) is asserted low.

Figure 21, on page 57

, Data# Polling

Timings (During Embedded Algorithms), in the

AC Characteristics on page 50

section illustrates

this.

June 13, 2005 S29AL032D_00_A3

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A d v a n c e I n f o r m a t i o n

If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array
data (including during the Erase Suspend mode), or is in the standby mode.

Table 18 on page 44

shows the outputs for RY/BY#. Figures

Figure 14, on page 50

Figure 15, on

page 51

Figure 18, on page 55

and

Figure 19, on page 56

shows RY/BY# for read, reset, pro-

gram, and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read
at any address, and is valid after the rising edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.)
When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling on

page 39

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the
program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.

Table 18 on page 44

shows the outputs for Toggle Bit I on DQ6.

Figure 7, on page 43

shows the

toggle bit algorithm in flowchart form, and the section

Reading Toggle Bits DQ6/DQ2 on page 42

explains the algorithm.

Figure 22, on page 57

shows the toggle bit timing diagrams.

Figure 23,

on page 58

shows the differences between DQ2 and DQ6 in graphical form. See also the subsec-

tion on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected
for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot
distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, in-
dicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to

Table 18 on page 44

to compare outputs for DQ2 and DQ6.

Figure 7, on page 43

shows the toggle bit algorithm in flowchart form, and the section

Reading

Toggle Bits DQ6/DQ2 on page 42

explains the algorithm. See also the DQ6: Toggle Bit I subsec-

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

tion.

Figure 22, on page 57

shows the toggle bit timing diagram.

Figure 23, on page 58

shows

the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to

Figure 7, on page 43

for the following discussion. Whenever the system initially begins

reading toggle bit status, it must read DQ7DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after
the first read. After the second read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has completed the program or erase
operation. The system can read array data on DQ7DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system must write the reset command to
return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (top of

Figure 7, on page

S29AL032D

S29AL032D_00_A3 June 13, 2005

A d v a n c e I n f o r m a t i o n

condition, the device halts the operation, and when the operation has exceeded the timing limits,
DQ5 produces a 1.

Under both these conditions, the system must issue the reset command to return the device to
reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) If additional sectors are selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to
1. The system may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 s. See also the

Sector Erase Command

Sequence on page 35

section.

After the sector erase command sequence is written, the system should read the status on DQ7
(Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence,
and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further com-
mands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0,
the device will accept additional sector erase commands. To ensure the command has been ac-
cepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check, the last command
might not have been accepted.

Table 18

shows the outputs for DQ3.

Table 18. Write Operation Status

Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. See

DQ5: Exceeded Timing Limits on page 43

for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

Operation

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

Standard
Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase
Suspend
Mode

Reading within Erase

Suspended Sector

No toggle

N/A

Toggle

Reading within Non-Erase
Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Absolute Maximum Ratings

Storage Temperature

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +150°C
Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +125°C
Voltage with Respect to Ground

(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . 0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may overshoot V

to 2.0 V for periods of up to 20 ns. See

Figure 8, on page 45

. Maximum DC voltage on input or I/O pins is

+0.5

V. During voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See

Figure 9,

on page 45

2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V

to 2.0 V for periods of up to 20 ns. See

Figure 8, on page 45

. Maximum DC input

voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the op-
erational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.

Operating Ranges

Industrial (I) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C

Supply Voltages

for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is
guaranteed.

Figure 8. Maximum Negative

Overshoot Waveform

Figure 9. Maximum Positive Overshoot Waveform

20 ns

+0.8 V

0.5 V

20 ns

2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

S29AL032D

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A d v a n c e I n f o r m a t i o n

DC Characteristics

CMOS Compatible

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with OE# at V

. Typical V

is 3.0 V.

2. Maximum I

specifications are tested with V

= V

max.

3. I

active while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns. Typical sleep

mode current is 200 nA.

6. Not 100% tested.
7. On the ACC pin only, the maximum input load current when ACC = V

is ±5.0 µA.

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input Load Current

(Note 7)

= V

to V

= V

max

±1.0

µA

LIT

A9 Input Load Current

= V

CC max

; A9 = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

= V

CC max

±1.0

µA

CC1

Active Read Current

(Notes 1, 2)

CE# = V

IL,

OE#

IH,

Byte Mode

10 MHz

5 MHz

1 MHz

CE# = V

IL,

OE#

IH,

Word Mode

10 MHz

5 MHz

1 MHz

CC2

Active Write Current

(Notes 2, 3, 5)

CE# = V

IL,

OE# = V

CC3

Standby Current (Notes 2, 4)

CE#, RESET# = V

±0.3 V

0.2

µA

CC4

Standby Current During Reset

(Notes 2, 4)

RESET# = V

± 0.3 V

0.2

µA

CC5

Automatic Sleep Mode

(Notes 2, 4, 6)

= V

± 0.3 V;

= V

± 0.3 V

0.2

µA

ACC

ACC Accelerated Program Current,

Word or Byte

CE# = V

, OE# = V

ACC pin

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 x V

+ 0.3

Voltage for WP#/ACC Sector Protect/

Unprotect and Program Acceleration

= 3.0 V ± 10%

11.5

12.5

Voltage for Autoselect and Temporary

Sector Unprotect

= 3.3 V

11.5

12.5

Output Low Voltage

= 4.0 mA, V

= V

CC min

0.45

OH1

Output High Voltage

= -2.0 mA, V

= V

CC min

2.4

OH2

= -100 µA, V

= V

CC min

0.4

LKO

Low V

Lock-Out Voltage (Note 4)

2.3

2.5

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A d v a n c e I n f o r m a t i o n

Erase and Programming Performance

Notes:
1. Typical program and erase times assume the following conditions: 25

C, V

= 3.0 V, 100,000 cycles, checkerboard

data pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See

Table 17

for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

TSOP and BGA Pin Capacitance

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25°C, f = 1.0 MHz.

Parameter

Typ

(Note 1)

Max

(Note 2)

Unit

Comments

Sector Erase Time

0.7

Excludes 00h programming
prior to erasure

(Note 4)

Chip Erase Time

Byte Programming Time

300

µs

Excludes system level
overhead

(Note 5)

Word Programming Time

360

µs

Accelerated Byte/Word Programming
Time

210

µs

Chip Programming Time

(Note 3)

Byte Mode

108

Word Mode

Parameter

Symbol

Parameter Description

Test Setup

Package

Typ

Max

Unit

Input Capacitance

= 0

TSOP

7.5

BGA

4.2

5.0

OUT

Output Capacitance

OUT

= 0

TSOP

8.5

BGA

5.4

6.5

IN2

Control Pin Capacitance

= 0

TSOP

7.5

BGA

3.9

4.7

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A d v a n c e I n f o r m a t i o n

Physical Dimensions

TS 048--48-Pin Standard TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

MO-142 (D) DD

MIN

0.05
0.95

0.17
0.17

0.10

18.30

19.80

0.50

0°

0.08

11.90

0.50 BASIC

MAX

0.15

1.20

0.27

0.16

0.21

8°

0.20

18.50
12.10

0.70

20.20

0.23

1.05

0.20

1.00

0.22

18.40

20.00

0.60

12.00

NOM

Symbol

Jedec

R
N

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

REVERSE PIN OUT (TOP VIEW)

2X (N/2 TIPS)

0.10

SEATING

PLANE

SEE DETAIL A

2X (N/2 TIPS)

0.25

0.10

N
2

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

DETAIL A

(c)

0.25MM (0.0098") BSC

GAUGE PLANE

PARALLEL TO

SEATING PLANE

(c)

WITH PLATING

BASE METAL

0.08MM (0.0031") M C A - B S

SECTION B-B

DETAIL B

e/2

X = A OR B

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Physical Dimensions

VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA)

10.0 x 6.0 mm

3425\ 16-038.25

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS

NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D"

DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E"

DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBN

048

JEDEC N/A

10.00 mm x 6.00 mm NOM

PACKAGE

SYMBOL MIN NOM MAX

NOTE

---

1.00 OVERALL

THICKNESS

0.17

---

--- BALL

HEIGHT

A2 0.62 --- 0.73

BODY

THICKNESS

10.00

BSC. BODY

SIZE

6.00

BSC. BODY

SIZE

5.60

BSC. BALL

FOOTPRINT

4.00

BSC. BALL

FOOTPRINT

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

N 48

TOTAL

BALL

COUNT

b 0.35 --- 0.45

BALL

DIAMETER

0.80

BSC. BALL

PITCH

SD / SE

0.40 BSC.

SOLDER BALL PLACEMENT

NONE

DEPOPULATED

SOLDER

BALLS

+0.20

-0.50

1.00

-0.50

+0.20

1.00

Ø0.50

SEATING PLANE

A1 ID.

A1 CORNER

Øb

Ø0.15

0.10

0.08

Ø0.08

June 13, 2005 S29AL032D_00_A3

S29AL032D

A d v a n c e I n f o r m a t i o n

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for

any

use

that

includes

fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2)

for any use where chance of failure is intolerable

(i.e., submersible repeater and

artificial satellite). Please note that Spansion LLC will not be liable

you and/or any third party for any claims or damages arising in connection with above-

mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan

, the US Export Administration Regulations or the applicable laws of any other country,

the

prior authorization by

the respective government entity

will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.

Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29AL032D90TFI003

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29AL032D90TFI003