Publication Number S29GL-A_00 Revision A Amendment 3 Issue Date April 22, 2005
S29GL-A MirrorBitTM Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
ii
S29GL-A MirrorBitTM Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e I n f o r m a t i o n
Notice On Data Sheet Designations
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readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
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"This document contains information on one or more products under development at Spansion LLC. The
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tacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice."
Preliminary
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IO
range. Changes
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Questions regarding these document designations may be directed to your local AMD or Fujitsu
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This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S29GL-A_00 Revision A Amendment 3 Issue Date April 22, 2005
Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- 3 volt read, erase, and program operations
Manufactured on 200 nm MirrorBit process
technology
Secured Silicon Sector region
-- 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
-- May be programmed and locked at the factory or by
the customer
Flexible sector architecture
-- 64Mb (uniform sector models): 128 32 Kword (64 KB)
sectors
-- 64Mb (boot sector models): 127 32 Kword (64 KB)
sectors + 8 4Kword (8KB) boot sectors
-- 32Mb (uniform sector models): 64 32Kword (64KB)
sectors
-- 32Mb (boot sector models): 63 32Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors
-- 16MB (boot sector models): 31 31Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors
Compatibility with JEDEC standards
-- Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles typical per sector
20-year data retention typical
Performance Characteristics
High performance
-- 90 ns access time
-- 4-word/8-byte page read buffer
-- 25 ns page read times
-- 16-word/32-byte write buffer which reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
-- 18 mA typical active read current
-- 50 mA typical erase/program current
-- 1 A typical standby mode current
Package options
-- 48-pin TSOP
-- 56-pin TSOP
-- 64-ball Fortified BGA
-- 48-ball fine-pitch BGA
Software & Hardware Features
Software features
-- Program Suspend & Resume: read other sectors
before programming operation is completed
-- Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
-- Data# polling & toggle bits provide status
-- CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
-- Unlock Bypass Program command reduces overall
multiple-word programming time
Hardware features
-- Sector Group Protection: hardware-level method of
preventing write operations within a sector group
-- Temporary Sector Unprotect: V
ID
-level method of
charging code in locked sectors
-- WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
-- Hardware reset input (RESET#) resets device
-- Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
S29GL-A MirrorBitTM Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
Data Sheet
ADVANCE
INFORMATION
2
S29GL-A MirrorBitTM Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e I n f o r m a t i o n
General Description
The S29GL-A family of devices are 3.0 V single power Flash memory manufac-
tured using 200 nm MirrorBit technology. The S29GL064A is a 64-Mb device
organized as 4,194,304 words or 8,388,608 bytes. The S29GL032A is a 32-Mb
device organized as 2,097,152 words or 4,194,304 bytes. The S29Gl016A is a
16 Mb device organized as 1,048,576 words or 2,097,152 bytes. Depending on
the model number, the devices have an 8-bit wide data bus only, 16-bit wide
data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The devices can be programmed either in
the host system or in standard EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a
specific operating voltage range (V
CC
) as specified in the
Product Selector Guide
and the
Ordering InformationS29GL016A
,
Ordering InformationS29GL032A
,
and
Ordering InformationS29GL064A
. Package offerings include 48-pin TSOP,
56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on
model number. Each device has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a V
CC
input, a high-voltage accelerated program
(ACC) feature provides shorter programming times through increased current
on the WP#/ACC input. This feature is intended to facilitate factory throughput
during system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-
supply Flash standard. Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and
data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation begins, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause
an erase operation in a given sector to read or program any other sector and
then complete the erase operation. The Program Suspend/Program Resume
feature enables the host system to pause a program operation in a given sector
to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the de-
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBitTM Flash Family
3
A d v a n c e I n f o r m a t i o n
vice, enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses are stable for a
specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting
a logic low on the WP#/ACC pin or WP# pin, depending on model number. The
protected sector is still protected even during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or
data that can be permanently protected. Once this sector is protected, no further
changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufac-
turing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via hot-hole assisted erase. The data is programmed using hot electron
injection.
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