This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the
right to change or discontinue work on this proposed product without notice.
Publication Number 27631 Revision A Amendment 4 Issue Date May 13, 2004
ADVANCE
INFORMATION
S29GLxxxN MirrorBit
TM
Flash Family
S29GL512N, S29GL256N, S29GL128N
512 Megabit, 256 Megabit, and 128 Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
110 nm MirrorBit process technology
Datasheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- 3 volt read, erase, and program operations
Enhanced VersatileI/OTM control
-- All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on V
IO
input.
V
IO
range is 1.65 to V
CC
Manufactured on 110 nm MirrorBit process
technology
SecSiTM (Secured Silicon) Sector region
-- 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
-- May be programmed and locked at the factory or by
the customer
Flexible sector architecture
-- S29GL512N: Five hundred twelve 64 Kword (128
Kbyte) sectors
-- S29GL256N: Two hundred fifty-six 64 Kword (128
Kbyte) sectors
-- S29GL128N: One hundred twenty-eight 64 Kword
(128 Kbyte) sectors
Compatibility with JEDEC standards
-- Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
100,000 erase cycles per sector typical
20-year data retention typical
Performance Characteristics
High performance
-- 80 ns access time (S29GL128N, S29GL256N),
90 ns access time (S29GL512N)
-- 8-word/16-byte page read buffer
-- 25 ns page read times
-- 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
-- 25 mA typical active read current;
-- 50 mA typical erase/program current
-- 1 A typical standby mode current
Package options
-- 56-pin TSOP
-- 64-ball Fortified BGA
Software & Hardware Features
Software features
-- Program Suspend & Resume: read other sectors
before programming operation is completed
-- Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
-- Data# polling & toggle bits provide status
-- Unlock Bypass Program command reduces overall
multiple-word or byte programming time
-- CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
-- Advanced Sector Protection
-- WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
-- Hardware reset input (RESET#) resets device
-- Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The devices have
a 16-bit wide data bus that can also function as an 8-bit wide data bus by using
the BYTE# input. The device can be programmed either in the host system or in
standard EPROM programmers.
Access times as fast as 80 ns (S29GL128N, S29GL256N) or 90 ns (S29GL512N)
are available. Note that each access time has a specific operating voltage range
(V
CC
) and an I/O voltage range (V
IO
), as specified in the
Product Selector Guide
and the
Ordering Information (512 Mb)
sections. The devices are offered in a 56-
pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a V
CC
input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/OTM (V
IO
) control allows the host system to set the
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the V
IO
pin. This allows the device to operate in a 1.8 V or 3 V system environ-
ment as required.
Hardware data protection measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at V
CC
. Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
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S29GLxxxN MirrorBitTM Flash Family
3
A d v a n c e I n f o r m a t i o n
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the device,
enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses have been stable
for a specified period of time.
The SecSiTM (Secured Silicon) Sector provides a 128-word/256-byte area for
code or data that can be permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the first or last sector by as-
serting a logic low on the WP# pin.
MirrorBit flash technology combines years of Flash memory manufacturing expe-
rience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via hot-hole
assisted erase. The data is programmed using hot electron injection.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
4
A d v a n c e I n f o r m a t i o n
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
S29GL512N ..............................................................................................................6
S29GL256N .............................................................................................................6
S29GL128N ..............................................................................................................6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .8
Special Package Handling Instructions ............................................................9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
S29GL512N ......................................................................................................... 11
S29GL256N ........................................................................................................ 11
S29GL128N ........................................................................................................ 11
Ordering Information (512 Mb) . . . . . . . . . . . . . . . 12
Ordering Information (256 Mb) . . . . . . . . . . . . . . . 13
Ordering Information (128 Mb) . . . . . . . . . . . . . . . 14
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 15
Table 1. Device Bus Operations ........................................... 15
Word/Byte Configuration .................................................................................15
VersatileIO
TM
(V
IO
) Control ..............................................................................15
Requirements for Reading Array Data ......................................................... 16
Page Mode Read .............................................................................................. 16
Writing Commands/Command Sequences ................................................. 16
Write Buffer ......................................................................................................17
Accelerated Program Operation ................................................................17
Autoselect Functions ......................................................................................17
Standby Mode ........................................................................................................17
Automatic Sleep Mode .......................................................................................17
RESET#: Hardware Reset Pin ......................................................................... 18
Output Disable Mode ........................................................................................ 18
Table 2. Sector Address TableS29GL512N ........................... 18
Table 3. Sector Address TableS29GL256N ........................... 33
Table 4. Sector Address TableS29GL128N ........................... 40
Autoselect Mode ................................................................................................ 44
Table 5. Autoselect Codes, (High Voltage Method) ................ 45
Sector Protection ................................................................................................45
Persistent Sector Protection .......................................................................45
Password Sector Protection ........................................................................45
WP# Hardware Protection .........................................................................45
Selecting a Sector Protection Mode .........................................................45
Advanced Sector Protection .......................................................................... 46
Lock Register ....................................................................................................... 46
Table 6. Lock Register ........................................................ 47
Persistent Sector Protection ...........................................................................47
Dynamic Protection Bit (DYB) ...................................................................47
Persistent Protection Bit (PPB) ................................................................. 48
Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 49
Table 7. Sector Protection Schemes ..................................... 49
Persistent Protection Mode Lock Bit .......................................................... 49
Password Sector Protection ........................................................................... 50
Password and Password Protection Mode Lock Bit ............................... 50
64-bit Password ....................................................................................................51
Persistent Protection Bit Lock (PPB Lock Bit) ............................................51
SecSi (Secured Silicon) Sector Flash Memory Region ...............................51
Write Protect (WP#) ........................................................................................53
Hardware Data Protection ..............................................................................53
Low VCC Write Inhibit ................................................................................53
Write Pulse "Glitch" Protection ................................................................53
Logical Inhibit ...................................................................................................53
Power-Up Write Inhibit ................................................................................53
Common Flash Memory Interface (CFI) . . . . . . . 53
Table 9. System Interface String.......................................... 55
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 57
Reading Array Data ...........................................................................................58
Reset Command .................................................................................................58
Autoselect Command Sequence ...................................................................58
Enter SecSi Sector/Exit SecSi Sector Command Sequence ................... 59
Word Program Command Sequence .......................................................... 59
Unlock Bypass Command Sequence ........................................................60
Write Buffer Programming .........................................................................60
Accelerated Program .....................................................................................61
Figure 1. Write Buffer Programming Operation....................... 63
Figure 2. Program Operation ............................................... 64
Program Suspend/Program Resume Command Sequence ....................64
Figure 3. Program Suspend/Program Resume ........................ 65
Chip Erase Command Sequence ................................................................... 65
Sector Erase Command Sequence ................................................................66
Figure 4. Erase Operation ................................................... 67
Erase Suspend/Erase Resume Commands .................................................. 67
Lock Register Command Set Definitions ....................................................68
Password Protection Command Set Definitions ......................................68
Non-Volatile Sector Protection Command Set Definitions ..................70
Global Volatile Sector Protection Freeze Command Set ......................70
Volatile Sector Protection Command Set ................................................... 71
SecSi Sector Entry Command .......................................................................... 71
SecSi Sector Exit Command ........................................................................... 72
Command Definitions ........................................................................................73
Table 12. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x16 .........................................................................73
Table 13. S29GL512N, S29GL256N, S29GL128N Command Defini-
tions, x8 ...........................................................................76
Write Operation Status ...................................................................................78
DQ7: Data# Polling ...........................................................................................78
Figure 5. Data# Polling Algorithm ........................................ 80
RY/BY#: Ready/Busy# .......................................................................................80
DQ6: Toggle Bit I ................................................................................................81
Figure 6. Toggle Bit Algorithm ............................................. 82
DQ2: Toggle Bit II ..............................................................................................82
Reading Toggle Bits DQ6/DQ2 ..................................................................... 83
DQ5: Exceeded Timing Limits ........................................................................ 83
DQ3: Sector Erase Timer ................................................................................ 83
DQ1: Write-to-Buffer Abort ...........................................................................84
Table 14. Write Operation Status .........................................84
Figure 7. Maximum Negative Overshoot Waveform................. 85
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 85
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 9. Test Setup........................................................... 87
Table 15. Test Specifications ...............................................87
Key to Switching Waveforms . . . . . . . . . . . . . . . . 87
Figure 10. Input Waveforms and
Measurement Levels........................................................... 87
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 88
Read-Only OperationsS29GL512N Only ..................................................88
Read-Only OperationsS29GL256N Only .................................................89
Read-Only OperationsS29GL128N Only ..................................................90
Figure 11. Read Operation Timings....................................... 91
Figure 12. Page Read Timings.............................................. 91
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S29GLxxxN MirrorBitTM Flash Family
5
A d v a n c e I n f o r m a t i o n
Hardware Reset (RESET#) .............................................................................. 92
Figure 13. Reset Timings..................................................... 92
Erase and Program OperationsS29GL512N Only ...................................93
Erase and Program OperationsS29GL256N Only ................................. 94
Erase and Program OperationsS29GL128N Only ...................................95
Figure 14. Program Operation Timings .................................. 96
Figure 15. Accelerated Program Timing Diagram .................... 96
Figure 16. Chip/Sector Erase Operation Timings ..................... 97
Figure 17. Data# Polling Timings
(During Embedded Algorithms) ............................................ 98
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99
Figure 19. DQ2 vs. DQ6 ...................................................... 99
Alternate CE# Controlled Erase and Program Operations
S29GL512N Only ...............................................................................................100
Alternate CE# Controlled Erase and Program Operations
S29GL256N Only ................................................................................................101
Alternate CE# Controlled Erase and Program Operations
S29GL128N Only ...............................................................................................102
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................ 103
Erase And Programming Performance . . . . . . . 104
TSOP Pin and BGA Package Capacitance . . . . 104
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . .105
TS056--56-Pin Standard Thin Small Outline Package (TSOP) ............105
LAA064--64-Ball Fortified Ball Grid Array (FBGA) ..............................106
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 107
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Product Selector Guide
S29GL512N
S29GL256N
S29GL128N
Part Number
S29GL512N
Speed Option
V
CC
= 2.73.6 V
V
IO
= 2.73.6 V
90
10
V
IO
= 1.651.95 V
10
11
Max. Access Time (ns)
90
100
100
110
Max. CE# Access Time (ns)
90
100
100
110
Max. Page access time (ns)
25
25
35
35
Max. OE# Access Time (ns)
25
25
35
35
Part Number
S29GL256N
Speed Option
V
CC
= 2.73.6 V
V
IO
= 2.73.6 V
80
90
V
IO
= 1.651.95 V
90
10
Max. Access Time (ns)
80
90
90
100
Max. CE# Access Time (ns)
80
90
90
100
Max. Page access time (ns)
25
25
35
35
Max. OE# Access Time (ns)
25
25
35
35
Part Number
S29GL128N
Speed Option
V
CC
= 2.73.6 V
V
IO
= 2.73.6 V
80
90
V
IO
= 1.651.95 V
90
10
Max. Access Time (ns)
80
90
90
100
Max. CE# Access Time (ns)
80
90
90
100
Max. Page access time (t
PACC
)
25
25
35
35
Max. OE# Access Time (ns)
25
25
35
35
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
7
A d v a n c e I n f o r m a t i o n
Block Diagram
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
V
IO
WE#
WP#/ACC
BYTE#
CE#
OE#
STB
STB
DQ15
DQ0 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Addr
e
ss La
t
c
h
A
Max
**A0
** A
Max
GL512N = A24, A
Max
GL256N = A23, A
Max
GL128N = A22
8
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Connection Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
A24
NC
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
23
24
25
26
27
28
A4
A3
A2
A1
NC
NC
34
33
32
31
30
29
OE#
V
SS
CE#
A0
NC
V
IO
NC for S29GL256N
and S29GL128N
NC for S29GL128N
56-Pin Standard TSOP
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
9
A d v a n c e I n f o r m a t i o n
Connection Diagrams
Note:
1. Ball C8 is NC on S29GL128N
2. Ball F8 is NC on S29GL256N and S29GL128N
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP, BGA). The package and/or data integrity may be compromised if the pack-
age body is exposed to temperatures above 150C for prolonged periods of time.
A2
C2
D2
E2
F2
G2
H2
A3
C3
D3
E3
F3
G3
H3
A4
C4
D4
E4
F4
G4
H4
A5
C5
D5
E5
F5
G5
H5
A6
C6
D6
E6
F6
G6
H6
A7
C7
D7
E7
F7
G7
H7
DQ15/A-1
V
SS
BYTE#
A16
A15
A14
A12
A13
DQ13
DQ6
DQ14
DQ7
A11
A10
A8
A9
V
CC
DQ4
DQ12
DQ5
A19
A21
RESET#
WE#
DQ11
DQ3
DQ10
DQ2
A20
A18
WP#/ACC
RY/BY#
DQ9
DQ1
DQ8
DQ0
A5
A6
A17
A7
OE#
V
SS
CE#
A0
A1
A2
A4
A3
A1
C1
D1
E1
F1
G1
H1
NC
NC
V
IO
NC
NC
NC
NC
NC
A8
C8
B2
B3
B4
B5
B6
B7
B1
B8
D8
E8
F8
G8
H8
NC
NC
A24
2
V
SS
V
IO
A23
1
A22
NC
64-ball Fortified BGA
Top View, Balls Facing Down
10
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
PIN DESCRIPTION
A24A0
=
25 Address inputs (512 Mb)
A23A0
=
24 Address inputs (256 Mb)
A22A0
=
23 Address inputs (128 Mb)
DQ14DQ0
=
15 Data inputs/outputs
DQ15/A-1
=
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
CE#
=
Chip Enable input
OE#
=
Output Enable input
WE#
=
Write Enable input
WP#/ACC
=
Hardware Write Protect input;
Acceleration input
RESET#
=
Hardware Reset Pin input
BYTE#
=
Selects 8-bit or 16-bit mode
RY/BY#
=
Ready/Busy output
V
CC
=
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
V
IO
=
Output Buffer power
V
SS
=
Device Ground
NC
=
Pin Not Connected Internally
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
11
A d v a n c e I n f o r m a t i o n
LOGIC SYMBOL
S29GL512N
S29GL256N
S29GL128N
25
16 or 8
DQ15DQ0
(A-1)
A24A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
V
IO
BYTE#
24
16 or 8
DQ15DQ0
(A-1)
A23A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
V
IO
BYTE#
23
16 or 8
DQ15DQ0
(A-1)
A22A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
V
IO
BYTE#
12
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Ordering Information (512 Mb)
The ordering part number is formed by a valid combination of the following:
Notes:
1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading "S29" and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
S29GL512N
10
F
A
I
00
0
PACKING TYPE
0
= Tray (standard; see note 1)
3
= 13" Tape and Reel
MODEL NUMBER (V
IO
range, protection when WP# =V
IL
)
01
= V
IO
= 2.7 to 3.6 V, highest address sector protected
02
= V
IO
= 2.7 to 3.6 V, lowest address sector protected
L
V1
= V
IO
= 1.65 to 1.95 V, highest address sector protected
V2
= V
IO
= 1.65 to 1.95 V, lowest address sector protected
TEMPERATURE RANGE
I =
Industrial
(40
C to +85
C)
PACKAGE MATERIALS SET
A
= Standard
F
= Pb-free
PACKAGE TYPE
T
= Thin Small Outline Package (TSOP) Standard Pinout
F
= Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
90
= 90 ns
10
= 100 ns
11
= 110 ns
DEVICE NUMBER/DESCRIPTION
S29GL512N
3.0 Volt-only, 512 Megabit (32 M x 16-Bit/64 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 110 nm MirrorBit
TM
process technology
S29GL512N Valid Combinations
Package Description
512 Mb
Speed (ns)
Package &
Temperature
Model Number
Pack Type
S29GL512N
90, 10
TAI, TFI
FAI, FFI
01, 02
0, 3 (Note 1)
TS056 (Note 2)
TSOP
10, 11
V1, V2
LAA064 (Note 3)
Fortified BGA
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
13
A d v a n c e I n f o r m a t i o n
Ordering Information (256 Mb)
The ordering part number is formed by a valid combination of the following:
Notes:
1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading "S29" and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
S29GL256N
90
T
A
I
00
0
PACKING TYPE
0
= Tray (standard; see note 1)
3
= 13" Tape and Reel
MODEL NUMBER (V
IO
range, protection when WP# =V
IL
)
01
= V
IO
= 2.7 to 3.6 V, highest address sector protected
02
= V
IO
= 2.7 to 3.6 V, lowest address sector protected
L
V1
= V
IO
= 1.65 to 1.95 V, highest address sector protected
V2
= V
IO
= 1.65 to 1.95 V, lowest address sector protected
TEMPERATURE RANGE
I =
Industrial
(40
C to +85
C)
PACKAGE MATERIALS SET
A
= Standard
F
= Pb-free
PACKAGE TYPE
T
= Thin Small Outline Package (TSOP) Standard Pinout
F
= Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
80
= 80 ns
90
= 90 ns
10
= 100 ns
DEVICE NUMBER/DESCRIPTION
S29GL256N
3.0 Volt-only, 256 Megabit (16 M x 16-Bit/64 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 110 nm MirrorBit
TM
process technology
S29GL512N Valid Combinations
Package Description
256 Mb
Speed (ns)
Package &
Temperature
Model Number
Pack Type
S29GL256N
80, 90
TAI, TFI
FAI, FFI
01, 02
0, 2 (Note 1)
TS056 (Note 2)
TSOP
90, 10
V1, V2
LAA064 (Note 3)
Fortified BGA
14
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Ordering Information (128 Mb)
The ordering part number is formed by a valid combination of the following:
Notes:
1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading "S29" and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
Consult your local sales office to confirm availability of specific valid combinations and to
check on newly released combinations.
S29GL128N
90
T
A
I
00
0
PACKING TYPE
0
= Tray (standard; see note 1)
3
= 13" Tape and Reel
MODEL NUMBER (V
IO
range, protection when WP# =V
IL
)
01
= V
IO
= 2.7 to 3.6 V, highest address sector protected
02
= V
IO
= 2.7 to 3.6 V, lowest address sector protected
L
V1
= V
IO
= 1.65 to 1.95 V, highest address sector protected
V2
= V
IO
= 1.65 to 1.95 V, lowest address sector protected
TEMPERATURE RANGE
I =
Industrial
(40
C to +85
C)
PACKAGE MATERIALS SET
A
= Standard
F
= Pb-free
PACKAGE TYPE
T
= Thin Small Outline Package (TSOP) Standard Pinout
F
= Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
80
= 80 ns
90
= 90 ns
10
= 100 ns
DEVICE NUMBER/DESCRIPTION
S29GL128N
3.0 Volt-only, 512 Megabit (32 M x 16-Bit/64 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 110 nm MirrorBit
TM
process technology
S29GL512N Valid Combinations
Package Description
128 Mb
Speed (ns)
Package &
Temperature
Model Number
Pack Type
S29GL128N
80, 90
TAI, TFI
FAI, FFI
01, 02
0, 3 (Note 1)
TS056 (Note 2)
TSOP
90, 10
V1, V2
LAA064 (Note 3)
Fortified BGA
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
15
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.512.5 V, V
HH
= 11.512.5V, X = Don't Care, SA = Sector
Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are AMax:A0 in word mode; A
Max
:A-1 in byte mode. Sector addresses are A
Max
:A16 in both modes.
2. If WP# = V
IL
, the first or last sector group remains protected. If WP# = V
IH
, the first or last sector will be
protected or unprotected as determined by the method described in "Write Protect (WP#)". All sectors are
unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
3. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic `1', the device is in word con-
figuration, DQ0DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic `0', the device is in byte configuration, and only
data I/O pins DQ0DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
VersatileIO
TM
(V
IO
) Control
The VersatileIO
TM
(V
IO
) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
Operation
CE#
OE#
WE
#
RESET#
WP#/
ACC
Addresses
(Note 2)
DQ0
DQ7
DQ8DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read
L
L
H
H
X
A
IN
D
OUT
D
OUT
DQ8DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
L
H
L
H
Note 2
A
IN
(Note 3)
(Note
3)
Accelerated Program
L
H
L
H
V
HH
A
IN
(Note 3)
(Note
3)
Standby
V
CC
0.3 V
X
X
V
CC
0.3 V
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
High-Z
High-Z
High-Z
16
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
level that is asserted on V
IO
. See Ordering Information for V
IO
options on this
device.
For example, a V
I/O
of 1.653.6 volts allows for I/O at the 1.8 or 3 volt levels,
driving and receiving signals to and from other 1.8 or 3 V devices on the same
data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
IL
. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and to Figure 11 for the timing diagram.
Refer to the DC Characteristics table for the active current specification on read-
ing array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)A3. Address
bits A2A0 in word mode (A2A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t
ACC
or t
CE
and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to t
PACC
. When CE# is de-asserted and reasserted
for a subsequent access, the access time is t
ACC
or t
CE
. Fast page mode accesses
are obtained by keeping the "read-page addresses" constant and changing the
"intra-read page" addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The "Word/Byte Program
Command Sequence" section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2 indicates the address space that each sector occupies.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
17
A d v a n c e I n f o r m a t i o n
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See "Write Buffer" for more
information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts V
HH
on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Removing V
HH
from the WP#/
ACC pin returns the device to normal operation. Note that the WP#/ACC pin must
not be at V
HH
for operations other than accelerated programming, or device dam-
age may result. WP# has an internal pullup; when unconnected, WP# is at V
IH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7DQ0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect Mode" section on page
44 and "Autoselect Command Sequence" section on page 58 sections for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
IO
0.3 V. (Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within V
IO
0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
CE
) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
Refer to the "DC Characteristics" section on page 86 for the standby current
specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
18
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the "DC Characteristics" section on page 86 for the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
SS
0.3 V, the device draws CMOS standby current (I
CC5
). If RESET# is held
at V
IL
but not within V
SS
0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output pins
are placed in the high impedance state.
Table 2. Sector Address TableS29GL512N
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
0
0
0
128/64
0000000001FFFF
0000000000FFFF
SA1
0
0
0
0
0
0
0
0
1
128/64
0020000003FFFF
0010000001FFFF
SA2
0
0
0
0
0
0
0
1
0
128/64
0040000005FFFF
0020000002FFFF
SA3
0
0
0
0
0
0
0
1
1
128/64
0060000007FFFF
0030000003FFFF
SA4
0
0
0
0
0
0
1
0
0
128/64
0080000009FFFF
0040000004FFFF
SA5
0
0
0
0
0
0
1
0
1
128/64
00A000000BFFFF
0050000005FFFF
SA6
0
0
0
0
0
0
1
1
0
128/64
00C000000DFFFF
0060000006FFFF
SA7
0
0
0
0
0
0
1
1
1
128/64
00E000000FFFFF
0070000007FFFF
SA8
0
0
0
0
0
1
0
0
0
128/64
0100000011FFFF
0080000008FFFF
SA9
0
0
0
0
0
1
0
0
1
128/64
0120000013FFFF
0090000009FFFF
SA10
0
0
0
0
0
1
0
1
0
128/64
0140000015FFFF
00A000000AFFFF
SA11
0
0
0
0
0
1
0
1
1
128/64
0160000017FFFF
00B000000BFFFF
SA12
0
0
0
0
0
1
1
0
0
128/64
0180000019FFFF
00C000000CFFFF
SA13
0
0
0
0
0
1
1
0
1
128/64
01A000001BFFFF
00D000000DFFFF
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
19
A d v a n c e I n f o r m a t i o n
SA14
0
0
0
0
0
1
1
1
0
128/64
01C000001DFFFF
00E000000EFFFF
SA15
0
0
0
0
0
1
1
1
1
128/64
01E000001FFFFF
00F000000FFFFF
SA16
0
0
0
0
1
0
0
0
0
128/64
0200000021FFFF
0100000010FFFF
SA17
0
0
0
0
1
0
0
0
1
128/64
0220000023FFFF
0110000011FFFF
SA18
0
0
0
0
1
0
0
1
0
128/64
0240000025FFFF
0120000012FFFF
SA19
0
0
0
0
1
0
0
1
1
128/64
0260000027FFFF
0130000013FFFF
SA20
0
0
0
0
1
0
1
0
0
128/64
0280000029FFFF
0140000014FFFF
SA21
0
0
0
0
1
0
1
0
1
128/64
02A000002BFFFF
0150000015FFFF
SA22
0
0
0
0
1
0
1
1
0
128/64
02C000002DFFFF
0160000016FFFF
SA23
0
0
0
0
1
0
1
1
1
128/64
02E000002FFFFF
0170000017FFFF
SA24
0
0
0
0
1
1
0
0
0
128/64
0300000031FFFF
0180000018FFFF
SA25
0
0
0
0
1
1
0
0
1
128/64
0320000033FFFF
0190000019FFFF
SA26
0
0
0
0
1
1
0
1
0
128/64
0340000035FFFF
01A000001AFFFF
SA27
0
0
0
0
1
1
0
1
1
128/64
0360000037FFFF
01B000001BFFFF
SA28
0
0
0
0
1
1
1
0
0
128/64
0380000039FFFF
01C000001CFFFF
SA29
0
0
0
0
1
1
1
0
1
128/64
03A000003BFFFF
01D000001DFFFF
SA30
0
0
0
0
1
1
1
1
0
128/64
03C000003DFFFF
01E000001EFFFF
SA31
0
0
0
0
1
1
1
1
1
128/64
03E00000EFFFFF
01F000001FFFFF
SA32
0
0
0
1
0
0
0
0
0
128/64
0400000041FFFF
0200000020FFFF
SA33
0
0
0
1
0
0
0
0
1
128/64
0420000043FFFF
0210000021FFFF
SA34
0
0
0
1
0
0
0
1
0
128/64
0440000045FFFF
0220000022FFFF
SA35
0
0
0
1
0
0
0
1
1
128/64
0460000047FFFF
0230000023FFFF
SA36
0
0
0
1
0
0
1
0
0
128/64
0480000049FFFF
0240000024FFFF
SA37
0
0
0
1
0
0
1
0
1
128/64
04A000004BFFFF
0250000025FFFF
SA38
0
0
0
1
0
0
1
1
0
128/64
04C000004DFFFF
0260000026FFFF
SA39
0
0
0
1
0
0
1
1
1
128/64
04E000004FFFFF
0270000027FFFF
SA40
0
0
0
1
0
1
0
0
0
128/64
0500000051FFFF
0280000028FFFF
SA41
0
0
0
1
0
1
0
0
1
128/64
0520000053FFFF
0290000029FFFF
SA42
0
0
0
1
0
1
0
1
0
128/64
0540000055FFFF
02A000002AFFFF
SA43
0
0
0
1
0
1
0
1
1
128/64
0560000057FFFF
02B000002BFFFF
SA44
0
0
0
1
0
1
1
0
0
128/64
0580000059FFFF
02C000002CFFFF
SA45
0
0
0
1
0
1
1
0
1
128/64
05A000005BFFFF
02D000002DFFFF
SA46
0
0
0
1
0
1
1
1
0
128/64
05C000005DFFFF
02E000002EFFFF
SA47
0
0
0
1
0
1
1
1
1
128/64
05E000005FFFFF
02F000002FFFFF
SA48
0
0
0
1
1
0
0
0
0
128/64
0600000061FFFF
0300000030FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
20
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA49
0
0
0
1
1
0
0
0
1
128/64
0620000063FFFF
0310000031FFFF
SA50
0
0
0
1
1
0
0
1
0
128/64
0640000065FFFF
0320000032FFFF
SA51
0
0
0
1
1
0
0
1
1
128/64
0660000067FFFF
0330000033FFFF
SA52
0
0
0
1
1
0
1
0
0
128/64
0680000069FFFF
0340000034FFFF
SA53
0
0
0
1
1
0
1
0
1
128/64
06A000006BFFFF
0350000035FFFF
SA54
0
0
0
1
1
0
1
1
0
128/64
06C000006DFFFF
0360000036FFFF
SA55
0
0
0
1
1
0
1
1
1
128/64
06E000006FFFFF
0370000037FFFF
SA56
0
0
0
1
1
1
0
0
0
128/64
0700000071FFFF
0380000038FFFF
SA57
0
0
0
1
1
1
0
0
1
128/64
0720000073FFFF
0390000039FFFF
SA58
0
0
0
1
1
1
0
1
0
128/64
0740000075FFFF
03A000003AFFFF
SA59
0
0
0
1
1
1
0
1
1
128/64
0760000077FFFF
03B000003BFFFF
SA60
0
0
0
1
1
1
1
0
0
128/64
0780000079FFFF
03C000003CFFFF
SA61
0
0
0
1
1
1
1
0
1
128/64
07A000007BFFFF
03D000003DFFFF
SA62
0
0
0
1
1
1
1
1
0
128/64
07C000007DFFFF
03E000003EFFFF
SA63
0
0
0
1
1
1
1
1
1
128/64
07E000007FFFFF
03F000003FFFFF
SA64
0
0
1
0
0
0
0
0
0
128/64
0800000081FFFF
0400000040FFFF
SA65
0
0
1
0
0
0
0
0
1
128/64
0820000083FFFF
0410000041FFFF
SA66
0
0
1
0
0
0
0
1
0
128/64
0840000085FFFF
0420000042FFFF
SA67
0
0
1
0
0
0
0
1
1
128/64
0860000087FFFF
0430000043FFFF
SA68
0
0
1
0
0
0
1
0
0
128/64
0880000089FFFF
0440000044FFFF
SA69
0
0
1
0
0
0
1
0
1
128/64
08A000008BFFFF
0450000045FFFF
SA70
0
0
1
0
0
0
1
1
0
128/64
08C000008DFFFF
0460000046FFFF
SA71
0
0
1
0
0
0
1
1
1
128/64
08E000008FFFFF
0470000047FFFF
SA72
0
0
1
0
0
1
0
0
0
128/64
0900000091FFFF
0480000048FFFF
SA73
0
0
1
0
0
1
0
0
1
128/64
0920000093FFFF
0490000049FFFF
SA74
0
0
1
0
0
1
0
1
0
128/64
0940000095FFFF
04A000004AFFFF
SA75
0
0
1
0
0
1
0
1
1
128/64
0960000097FFFF
04B000004BFFFF
SA76
0
0
1
0
0
1
1
0
0
128/64
0980000099FFFF
04C000004CFFFF
SA77
0
0
1
0
0
1
1
0
1
128/64
09A000009BFFFF
04D000004DFFFF
SA78
0
0
1
0
0
1
1
1
0
128/64
09C000009DFFFF
04E000004EFFFF
SA79
0
0
1
0
0
1
1
1
1
128/64
09E000009FFFFF
04F000004FFFFF
SA80
0
0
1
0
1
0
0
0
0
128/64
0A000000A1FFFF
0500000050FFFF
SA81
0
0
1
0
1
0
0
0
1
128/64
0A200000A3FFFF
0510000051FFFF
SA82
0
0
1
0
1
0
0
1
0
128/64
0A400000A5FFFF
0520000052FFFF
SA83
0
0
1
0
1
0
0
1
1
128/64
0A600000A7FFFF
0530000053FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
21
A d v a n c e I n f o r m a t i o n
SA84
0
0
1
0
1
0
1
0
0
128/64
0A800000A9FFFF
0540000054FFFF
SA85
0
0
1
0
1
0
1
0
1
128/64
0AA00000ABFFFF
0550000055FFFF
SA86
0
0
1
0
1
0
1
1
0
128/64
0AC00000ADFFFF
0560000056FFFF
SA87
0
0
1
0
1
0
1
1
1
128/64
0AE00000AFFFFF
0570000057FFFF
SA88
0
0
1
0
1
1
0
0
0
128/64
0B000000B1FFFF
0580000058FFFF
SA89
0
0
1
0
1
1
0
0
1
128/64
0B200000B3FFFF
0590000059FFFF
SA90
0
0
1
0
1
1
0
1
0
128/64
0B400000B5FFFF
05A000005AFFFF
SA91
0
0
1
0
1
1
0
1
1
128/64
0B600000B7FFFF
05B000005BFFFF
SA92
0
0
1
0
1
1
1
0
0
128/64
0B800000B9FFFF
05C000005CFFFF
SA93
0
0
1
0
1
1
1
0
1
128/64
0BA00000BBFFFF
05D000005DFFFF
SA94
0
0
1
0
1
1
1
1
0
128/64
0BC00000BDFFFF
05E000005EFFFF
SA95
0
0
1
0
1
1
1
1
1
128/64
0BE00000BFFFFF
05F000005FFFFF
SA96
0
0
1
1
0
0
0
0
0
128/64
0C000000C1FFFF
0600000060FFFF
SA97
0
0
1
1
0
0
0
0
1
128/64
0C200000C3FFFF
0610000061FFFF
SA98
0
0
1
1
0
0
0
1
0
128/64
0C400000C5FFFF
0620000062FFFF
SA99
0
0
1
1
0
0
0
1
1
128/64
0C600000C7FFFF
0630000063FFFF
SA100
0
0
1
1
0
0
1
0
0
128/64
0C800000C9FFFF
0640000064FFFF
SA101
0
0
1
1
0
0
1
0
1
128/64
0CA00000CBFFFF
0650000065FFFF
SA102
0
0
1
1
0
0
1
1
0
128/64
0CC00000CDFFFF
0660000066FFFF
SA103
0
0
1
1
0
0
1
1
1
128/64
0CE00000CFFFFF
0670000067FFFF
SA104
0
0
1
1
0
1
0
0
0
128/64
0D000000D1FFFF
0680000068FFFF
SA105
0
0
1
1
0
1
0
0
1
128/64
0D200000D3FFFF
0690000069FFFF
SA106
0
0
1
1
0
1
0
1
0
128/64
0D400000D5FFFF
06A000006AFFFF
SA107
0
0
1
1
0
1
0
1
1
128/64
0D600000D7FFFF
06B000006BFFFF
SA108
0
0
1
1
0
1
1
0
0
128/64
0D800000D9FFFF
06C000006CFFFF
SA109
0
0
1
1
0
1
1
0
1
128/64
0DA00000DBFFFF
06D000006DFFFF
SA110
0
0
1
1
0
1
1
1
0
128/64
0DC00000DDFFFF
06E000006EFFFF
SA111
0
0
1
1
0
1
1
1
1
128/64
0DE00000DFFFFF
06F000006FFFFF
SA112
0
0
1
1
1
0
0
0
0
128/64
0E000000E1FFFF
0700000070FFFF
SA113
0
0
1
1
1
0
0
0
1
128/64
0E200000E3FFFF
0710000071FFFF
SA114
0
0
1
1
1
0
0
1
0
128/64
0E400000E5FFFF
0720000072FFFF
SA115
0
0
1
1
1
0
0
1
1
128/64
0E600000E7FFFF
0730000073FFFF
SA116
0
0
1
1
1
0
1
0
0
128/64
0E800000E9FFFF
0740000074FFFF
SA117
0
0
1
1
1
0
1
0
1
128/64
0EA00000EBFFFF
0750000075FFFF
SA118
0
0
1
1
1
0
1
1
0
128/64
0EC00000EDFFFF
0760000076FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
22
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA119
0
0
1
1
1
0
1
1
1
128/64
0EE00000EFFFFF
0770000077FFFF
SA120
0
0
1
1
1
1
0
0
0
128/64
0F000000F1FFFF
0780000078FFFF
SA121
0
0
1
1
1
1
0
0
1
128/64
0F200000F3FFFF
0790000079FFFF
SA122
0
0
1
1
1
1
0
1
0
128/64
0F400000F5FFFF
07A000007AFFFF
SA123
0
0
1
1
1
1
0
1
1
128/64
0F600000F7FFFF
07B000007BFFFF
SA124
0
0
1
1
1
1
1
0
0
128/64
0F800000F9FFFF
07C000007CFFFF
SA125
0
0
1
1
1
1
1
0
1
128/64
0FA00000FBFFFF
07D000007DFFFF
SA126
0
0
1
1
1
1
1
1
0
128/64
0FC00000FDFFFF
07E000007EFFFF
SA127
0
0
1
1
1
1
1
1
1
128/64
0FE00000FFFFFF
07F000007FFFFF
SA128
0
1
0
0
0
0
0
0
0
128/64
1000000101FFFF
0800000080FFFF
SA129
0
1
0
0
0
0
0
0
1
128/64
1020000103FFFF
0810000081FFFF
SA130
0
1
0
0
0
0
0
1
0
128/64
1040000105FFFF
0820000082FFFF
SA131
0
1
0
0
0
0
0
1
1
128/64
1060000017FFFF
0830000083FFFF
SA132
0
1
0
0
0
0
1
0
0
128/64
1080000109FFFF
0840000084FFFF
SA133
0
1
0
0
0
0
1
0
1
128/64
10A000010BFFFF
0850000085FFFF
SA134
0
1
0
0
0
0
1
1
0
128/64
10C000010DFFFF
0860000086FFFF
SA135
0
1
0
0
0
0
1
1
1
128/64
10E000010FFFFF
0870000087FFFF
SA136
0
1
0
0
0
1
0
0
0
128/64
1100000111FFFF
0880000088FFFF
SA137
0
1
0
0
0
1
0
0
1
128/64
1120000113FFFF
0890000089FFFF
SA138
0
1
0
0
0
1
0
1
0
128/64
1140000115FFFF
08A000008AFFFF
SA139
0
1
0
0
0
1
0
1
1
128/64
1160000117FFFF
08B000008BFFFF
SA140
0
1
0
0
0
1
1
0
0
128/64
1180000119FFFF
08C000008CFFFF
SA141
0
1
0
0
0
1
1
0
1
128/64
11A000011BFFFF
08D000008DFFFF
SA142
0
1
0
0
0
1
1
1
0
128/64
11C000011DFFFF
08E000008EFFFF
SA143
0
1
0
0
0
1
1
1
1
128/64
11E000011FFFFF
08F000008FFFFF
SA144
0
1
0
0
1
0
0
0
0
128/64
1200000121FFFF
0900000090FFFF
SA145
0
1
0
0
1
0
0
0
1
128/64
1220000123FFFF
0910000091FFFF
SA146
0
1
0
0
1
0
0
1
0
128/64
1240000125FFFF
0920000092FFFF
SA147
0
1
0
0
1
0
0
1
1
128/64
1260000127FFFF
0930000093FFFF
SA148
0
1
0
0
1
0
1
0
0
128/64
1280000129FFFF
0940000094FFFF
SA149
0
1
0
0
1
0
1
0
1
128/64
12A000012BFFFF
0950000095FFFF
SA150
0
1
0
0
1
0
1
1
0
128/64
12C000012DFFFF
0960000096FFFF
SA151
0
1
0
0
1
0
1
1
1
128/64
12E000012FFFFF
0970000097FFFF
SA152
0
1
0
0
1
1
0
0
0
128/64
1300000131FFFF
0980000098FFFF
SA153
0
1
0
0
1
1
0
0
1
128/64
1320000133FFFF
0990000099FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
23
A d v a n c e I n f o r m a t i o n
SA154
0
1
0
0
1
1
0
1
0
128/64
1340000135FFFF
09A000009AFFFF
SA155
0
1
0
0
1
1
0
1
1
128/64
1360000137FFFF
09B000009BFFFF
SA156
0
1
0
0
1
1
1
0
0
128/64
1380000139FFFF
09C000009CFFFF
SA157
0
1
0
0
1
1
1
0
1
128/64
13A000013BFFFF
09D000009DFFFF
SA158
0
1
0
0
1
1
1
1
0
128/64
13C000013DFFFF
09E000009EFFFF
SA159
0
1
0
0
1
1
1
1
1
128/64
13E000013FFFFF
09F000009FFFFF
SA160
0
1
0
1
0
0
0
0
0
128/64
1400000141FFFF
0A000000A0FFFF
SA161
0
1
0
1
0
0
0
0
1
128/64
1420000143FFFF
0A100000A1FFFF
SA162
0
1
0
1
0
0
0
1
0
128/64
1440000145FFFF
0A200000A2FFFF
SA163
0
1
0
1
0
0
0
1
1
128/64
1460000147FFFF
0A300000A3FFFF
SA164
0
1
0
1
0
0
1
0
0
128/64
1480000149FFFF
0A400000A4FFFF
SA165
0
1
0
1
0
0
1
0
1
128/64
14A000014BFFFF
0A500000A5FFFF
SA166
0
1
0
1
0
0
1
1
0
128/64
14C000014DFFFF
0A600000A6FFFF
SA167
0
1
0
1
0
0
1
1
1
128/64
14E000014FFFFF
0A700000A7FFFF
SA168
0
1
0
1
0
1
0
0
0
128/64
1500000151FFFF
0A800000A8FFFF
SA169
0
1
0
1
0
1
0
0
1
128/64
1520000153FFFF
0A900000A9FFFF
SA170
0
1
0
1
0
1
0
1
0
128/64
1540000155FFFF
0AA00000AAFFFF
SA171
0
1
0
1
0
1
0
1
1
128/64
1560000157FFFF
0AB00000ABFFFF
SA172
0
1
0
1
0
1
1
0
0
128/64
1580000159FFFF
0AC00000ACFFFF
SA173
0
1
0
1
0
1
1
0
1
128/64
15A000015BFFFF
0AD00000ADFFFF
SA174
0
1
0
1
0
1
1
1
0
128/64
15C000015DFFFF
0AE00000AEFFFF
SA175
0
1
0
1
0
1
1
1
1
128/64
15E000015FFFFF
0AF00000AFFFFF
SA176
0
1
0
1
1
0
0
0
0
128/64
160000161FFFF
0B000000B0FFFF
SA177
0
1
0
1
1
0
0
0
1
128/64
1620000163FFFF
0B100000B1FFFF
SA178
0
1
0
1
1
0
0
1
0
128/64
1640000165FFFF
0B200000B2FFFF
SA179
0
1
0
1
1
0
0
1
1
128/64
1660000167FFFF
0B300000B3FFFF
SA180
0
1
0
1
1
0
1
0
0
128/64
1680000169FFFF
0B400000B4FFFF
SA181
0
1
0
1
1
0
1
0
1
128/64
16A000016BFFFF
0B500000B5FFFF
SA182
0
1
0
1
1
0
1
1
0
128/64
16C000016DFFFF
0B600000B6FFFF
SA183
0
1
0
1
1
0
1
1
1
128/64
16E000016FFFFF
0B700000B7FFFF
SA184
0
1
0
1
1
1
0
0
0
128/64
1700000171FFFF
0B800000B8FFFF
SA185
0
1
0
1
1
1
0
0
1
128/64
1720000173FFFF
0B900000B9FFFF
SA186
0
1
0
1
1
1
0
1
0
128/64
1740000175FFFF
0BA00000BAFFFF
SA187
0
1
0
1
1
1
0
1
1
128/64
1760000177FFFF
0BB00000BBFFFF
SA188
0
1
0
1
1
1
1
0
0
128/64
1780000179FFFF
0BC00000BCFFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
24
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA189
0
1
0
1
1
1
1
0
1
128/64
17A000017BFFFF
0BD00000BDFFFF
SA190
0
1
0
1
1
1
1
1
0
128/64
17C000017DFFFF
0BE00000BEFFFF
SA191
0
1
0
1
1
1
1
1
1
128/64
17E000017FFFFF
0BF00000BFFFFF
SA192
0
1
1
0
0
0
0
0
0
128/64
1800000181FFFF
0C000000C0FFFF
SA193
0
1
1
0
0
0
0
0
1
128/64
1820000183FFFF
0C100000C1FFFF
SA194
0
1
1
0
0
0
0
1
0
128/64
1840000185FFFF
0C200000C2FFFF
SA195
0
1
1
0
0
0
0
1
1
128/64
1860000187FFFF
0C300000C3FFFF
SA196
0
1
1
0
0
0
1
0
0
128/64
1880000189FFFF
0C400000C4FFFF
SA197
0
1
1
0
0
0
1
0
1
128/64
18A000018BFFFF
0C500000C5FFFF
SA198
0
1
1
0
0
0
1
1
0
128/64
18C000018DFFFF
0C600000C6FFFF
SA199
0
1
1
0
0
0
1
1
1
128/64
18E000018FFFFF
0C700000C7FFFF
SA200
0
1
1
0
0
1
0
0
0
128/64
1900000191FFFF
0C800000C8FFFF
SA201
0
1
1
0
0
1
0
0
1
128/64
1920000193FFFF
0C900000C9FFFF
SA202
0
1
1
0
0
1
0
1
0
128/64
1940000195FFFF
0CA00000CAFFFF
SA203
0
1
1
0
0
1
0
1
1
128/64
1960000197FFFF
0CB00000CBFFFF
SA204
0
1
1
0
0
1
1
0
0
128/64
1980000199FFFF
0CC00000CCFFFF
SA205
0
1
1
0
0
1
1
0
1
128/64
19A000019BFFFF
0CD00000CDFFFF
SA206
0
1
1
0
0
1
1
1
0
128/64
19C000019DFFFF
0CE00000CEFFFF
SA207
0
1
1
0
0
1
1
1
1
128/64
19E000019FFFFF
0CF00000CFFFFF
SA208
0
1
1
0
1
0
0
0
0
128/64
1A000001A1FFFF
0D000000D0FFFF
SA209
0
1
1
0
1
0
0
0
1
128/64
1A200001A3FFFF
0D100000D1FFFF
SA210
0
1
1
0
1
0
0
1
0
128/64
1A400001A5FFFF
0D200000D2FFFF
SA211
0
1
1
0
1
0
0
1
1
128/64
1A600001A7FFFF
0D300000D3FFFF
SA212
0
1
1
0
1
0
1
0
0
128/64
1A800001A9FFFF
0D400000D4FFFF
SA213
0
1
1
0
1
0
1
0
1
128/64
1AA00001ABFFFF
0D500000D5FFFF
SA214
0
1
1
0
1
0
1
1
0
128/64
1AC00001ADFFFF
0D600000D6FFFF
SA215
0
1
1
0
1
0
1
1
1
128/64
1AE00001AFFFFF
0D700000D7FFFF
SA216
0
1
1
0
1
1
0
0
0
128/64
1B000001B1FFFF
0D800000D8FFFF
SA217
0
1
1
0
1
1
0
0
1
128/64
1B200001B3FFFF
0D900000D9FFFF
SA218
0
1
1
0
1
1
0
1
0
128/64
1B400001B5FFFF
0DA00000DAFFFF
SA219
0
1
1
0
1
1
0
1
1
128/64
1B600001B7FFFF
0DB00000DBFFFF
SA220
0
1
1
0
1
1
1
0
0
128/64
1B800001B9FFFF
0DC00000DCFFFF
SA221
0
1
1
0
1
1
1
0
1
128/64
1BA00001BBFFFF
0DD00000DDFFFF
SA222
0
1
1
0
1
1
1
1
0
128/64
1BC00001BDFFFF
0DE00000DEFFFF
SA223
0
1
1
0
1
1
1
1
1
128/64
1BE00001BFFFFF
0DF00000DFFFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
25
A d v a n c e I n f o r m a t i o n
SA224
0
1
1
1
0
0
0
0
0
128/64
1C000001C1FFFF
0E000000E0FFFF
SA225
0
1
1
1
0
0
0
0
1
128/64
1C200001C3FFFF
0E100000E1FFFF
SA226
0
1
1
1
0
0
0
1
0
128/64
1C400001C5FFFF
0E200000E2FFFF
SA227
0
1
1
1
0
0
0
1
1
128/64
1C600001C7FFFF
0E300000E3FFFF
SA228
0
1
1
1
0
0
1
0
0
128/64
1C800001C9FFFF
0E400000E4FFFF
SA229
0
1
1
1
0
0
1
0
1
128/64
1CA00001CBFFFF
0E500000E5FFFF
SA230
0
1
1
1
0
0
1
1
0
128/64
1CC00001CDFFFF
0E600000E6FFFF
SA231
0
1
1
1
0
0
1
1
1
128/64
1CE00001CFFFFF
0E700000E7FFFF
SA232
0
1
1
1
0
1
0
0
0
128/64
1D000001D1FFFF
0E800000E8FFFF
SA233
0
1
1
1
0
1
0
0
1
128/64
1D200001D3FFFF
0E900000E9FFFF
SA234
0
1
1
1
0
1
0
1
0
128/64
1D400001D5FFFF
0EA00000EAFFFF
SA235
0
1
1
1
0
1
0
1
1
128/64
1D600001D7FFFF
0EB00000EBFFFF
SA236
0
1
1
1
0
1
1
0
0
128/64
1D800001D9FFFF
0EC00000ECFFFF
SA237
0
1
1
1
0
1
1
0
1
128/64
1DA00001DBFFFF
0ED00000EDFFFF
SA238
0
1
1
1
0
1
1
1
0
128/64
1DC00001DDFFFF
0EE00000EEFFFF
SA239
0
1
1
1
0
1
1
1
1
128/64
1DE00001DFFFFF
0EF00000EFFFFF
SA240
0
1
1
1
1
0
0
0
0
128/64
1E000001E1FFFF
0F000000F0FFFF
SA241
0
1
1
1
1
0
0
0
1
128/64
1E200001E3FFFF
0F100000F1FFFF
SA242
0
1
1
1
1
0
0
1
0
128/64
1E400001E5FFFF
0F200000F2FFFF
SA243
0
1
1
1
1
0
0
1
1
128/64
1E600001E7FFFF
0F300000F3FFFF
SA244
0
1
1
1
1
0
1
0
0
128/64
1E800001E9FFFF
0F400000F4FFFF
SA245
0
1
1
1
1
0
1
0
1
128/64
1EA00001EBFFFF
0F500000F5FFFF
SA246
0
1
1
1
1
0
1
1
0
128/64
1EC00001EDFFFF
0F600000F6FFFF
SA247
0
1
1
1
1
0
1
1
1
128/64
1EE00001EFFFFF
0F700000F7FFFF
SA248
0
1
1
1
1
1
0
0
0
128/64
1F000001F1FFFF
0F800000F8FFFF
SA249
0
1
1
1
1
1
0
0
1
128/64
1F200001F3FFFF
0F900000F9FFFF
SA250
0
1
1
1
1
1
0
1
0
128/64
1F400001F5FFFF
0FA00000FAFFFF
SA251
0
1
1
1
1
1
0
1
1
128/64
1F600001F7FFFF
0FB00000FBFFFF
SA252
0
1
1
1
1
1
1
0
0
128/64
1F800001F9FFFF
0FC00000FCFFFF
SA253
0
1
1
1
1
1
1
0
1
128/64
1FA00001FBFFFF
0FD00000FDFFFF
SA254
0
1
1
1
1
1
1
1
0
128/64
1FC00001FDFFFF
0FE00000FEFFFF
SA255
0
1
1
1
1
1
1
1
1
128/64
1FE00001FFFFFF
0FF00000FFFFFF
SA256
1
0
0
0
0
0
0
0
0
128/64
2000000201FFFF
1000000100FFFF
SA257
1
0
0
0
0
0
0
0
1
128/64
2020000203FFFF
1010000101FFFF
SA258
1
0
0
0
0
0
0
1
0
128/64
2040000205FFFF
1020000102FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
26
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA259
1
0
0
0
0
0
0
1
1
128/64
2060000207FFFF
1030000103FFFF
SA260
1
0
0
0
0
0
1
0
0
128/64
2080000209FFFF
1040000104FFFF
SA261
1
0
0
0
0
0
1
0
1
128/64
20A000020BFFFF
1050000105FFFF
SA262
1
0
0
0
0
0
1
1
0
128/64
20C000020DFFFF
1060000106FFFF
SA263
1
0
0
0
0
0
1
1
1
128/64
20E000020FFFFF
1070000107FFFF
SA264
1
0
0
0
0
1
0
0
0
128/64
2100000211FFFF
1080000108FFFF
SA265
1
0
0
0
0
1
0
0
1
128/64
2120000213FFFF
1090000109FFFF
SA266
1
0
0
0
0
1
0
1
0
128/64
2140000215FFFF
10A000010AFFFF
SA267
1
0
0
0
0
1
0
1
1
128/64
2160000217FFFF
10B000010BFFFF
SA268
1
0
0
0
0
1
1
0
0
128/64
2180000219FFFF
10C000010CFFFF
SA269
1
0
0
0
0
1
1
0
1
128/64
21A000021BFFFF
10D000010DFFFF
SA270
1
0
0
0
0
1
1
1
0
128/64
21C000021DFFFF
10E000010EFFFF
SA271
1
0
0
0
0
1
1
1
1
128/64
21E000021FFFFF
10F000010FFFFF
SA272
1
0
0
0
1
0
0
0
0
128/64
2200000221FFFF
1100000110FFFF
SA273
1
0
0
0
1
0
0
0
1
128/64
2220000223FFFF
1110000111FFFF
SA274
1
0
0
0
1
0
0
1
0
128/64
2240000225FFFF
1120000112FFFF
SA275
1
0
0
0
1
0
0
1
1
128/64
2260000227FFFF
1130000113FFFF
SA276
1
0
0
0
1
0
1
0
0
128/64
2280000229FFFF
1140000114FFFF
SA277
1
0
0
0
1
0
1
0
1
128/64
22A000022BFFFF
1150000115FFFF
SA278
1
0
0
0
1
0
1
1
0
128/64
22C000022DFFFF
1160000116FFFF
SA279
1
0
0
0
1
0
1
1
1
128/64
22E000022FFFFF
1170000117FFFF
SA280
1
0
0
0
1
1
0
0
0
128/64
2300000231FFFF
1180000118FFFF
SA281
1
0
0
0
1
1
0
0
1
128/64
2320000233FFFF
1190000119FFFF
SA282
1
0
0
0
1
1
0
1
0
128/64
2340000235FFFF
11A000011AFFFF
SA283
1
0
0
0
1
1
0
1
1
128/64
2360000237FFFF
11B000011BFFFF
SA284
1
0
0
0
1
1
1
0
0
128/64
2380000239FFFF
11C000011CFFFF
SA285
1
0
0
0
1
1
1
0
1
128/64
23A000023BFFFF
11D000011DFFFF
SA286
1
0
0
0
1
1
1
1
0
128/64
23C000023DFFFF
11E000011EFFFF
SA287
1
0
0
0
1
1
1
1
1
128/64
23E000023FFFFF
11F000011FFFFF
SA288
1
0
0
1
0
0
0
0
0
128/64
2400000241FFFF
1200000120FFFF
SA289
1
0
0
1
0
0
0
0
1
128/64
2420000243FFFF
1210000121FFFF
SA290
1
0
0
1
0
0
0
1
0
128/64
2440000245FFFF
1220000122FFFF
SA291
1
0
0
1
0
0
0
1
1
128/64
2460000247FFFF
1230000123FFFF
SA292
1
0
0
1
0
0
1
0
0
128/64
2480000249FFFF
1240000124FFFF
SA293
1
0
0
1
0
0
1
0
1
128/64
24A000024BFFFF
1250000125FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
27
A d v a n c e I n f o r m a t i o n
SA294
1
0
0
1
0
0
1
1
0
128/64
24C000024DFFFF
1260000126FFFF
SA295
1
0
0
1
0
0
1
1
1
128/64
24E000024FFFFF
1270000127FFFF
SA296
1
0
0
1
0
1
0
0
0
128/64
2500000251FFFF
1280000128FFFF
SA297
1
0
0
1
0
1
0
0
1
128/64
2520000253FFFF
1290000129FFFF
SA298
1
0
0
1
0
1
0
1
0
128/64
2540000255FFFF
12A000012AFFFF
SA299
1
0
0
1
0
1
0
1
1
128/64
2560000257FFFF
12B000012BFFFF
SA300
1
0
0
1
0
1
1
0
0
128/64
2580000259FFFF
12C000012CFFFF
SA301
1
0
0
1
0
1
1
0
1
128/64
25A000025BFFFF
12D000012DFFFF
SA302
1
0
0
1
0
1
1
1
0
128/64
25C000025DFFFF
12E000012EFFFF
SA303
1
0
0
1
0
1
1
1
1
128/64
25E000025FFFFF
12F000012FFFFF
SA304
1
0
0
1
1
0
0
0
0
128/64
2600000261FFFF
1300000130FFFF
SA305
1
0
0
1
1
0
0
0
1
128/64
2620000263FFFF
1310000131FFFF
SA306
1
0
0
1
1
0
0
1
0
128/64
2640000265FFFF
1320000132FFFF
SA307
1
0
0
1
1
0
0
1
1
128/64
2660000267FFFF
1330000133FFFF
SA308
1
0
0
1
1
0
1
0
0
128/64
2680000269FFFF
1340000134FFFF
SA309
1
0
0
1
1
0
1
0
1
128/64
26A000026BFFFF
1350000135FFFF
SA310
1
0
0
1
1
0
1
1
0
128/64
26C000026DFFFF
1360000136FFFF
SA311
1
0
0
1
1
0
1
1
1
128/64
26E000026FFFFF
1370000137FFFF
SA312
1
0
0
1
1
1
0
0
0
128/64
2700000271FFFF
1380000138FFFF
SA313
1
0
0
1
1
1
0
0
1
128/64
2720000273FFFF
1390000139FFFF
SA314
1
0
0
1
1
1
0
1
0
128/64
2740000275FFFF
13A000013AFFFF
SA315
1
0
0
1
1
1
0
1
1
128/64
2760000277FFFF
13B000013BFFFF
SA316
1
0
0
1
1
1
1
0
0
128/64
2780000279FFFF
13C000013CFFFF
SA317
1
0
0
1
1
1
1
0
1
128/64
27A000027BFFFF
13D000013DFFFF
SA318
1
0
0
1
1
1
1
1
0
128/64
27C000027DFFFF
13E000013EFFFF
SA319
1
0
0
1
1
1
1
1
1
128/64
27E000027FFFFF
13F000013FFFFF
SA320
1
0
1
0
0
0
0
0
0
128/64
2800000281FFFF
1400000140FFFF
SA321
1
0
1
0
0
0
0
0
1
128/64
2820000283FFFF
1410000141FFFF
SA322
1
0
1
0
0
0
0
1
0
128/64
2840000285FFFF
1420000142FFFF
SA323
1
0
1
0
0
0
0
1
1
128/64
2860000287FFFF
1430000143FFFF
SA324
1
0
1
0
0
0
1
0
0
128/64
2880000289FFFF
1440000144FFFF
SA325
1
0
1
0
0
0
1
0
1
128/64
28A000028BFFFF
1450000145FFFF
SA326
1
0
1
0
0
0
1
1
0
128/64
28C000028DFFFF
1460000146FFFF
SA327
1
0
1
0
0
0
1
1
1
128/64
28E000028FFFFF
1470000147FFFF
SA328
1
0
1
0
0
1
0
0
0
128/64
2900000291FFFF
1480000148FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
28
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA329
1
0
1
0
0
1
0
0
1
128/64
2920000293FFFF
1490000149FFFF
SA330
1
0
1
0
0
1
0
1
0
128/64
2940000295FFFF
14A000014AFFFF
SA331
1
0
1
0
0
1
0
1
1
128/64
2960000297FFFF
14B000014BFFFF
SA332
1
0
1
0
0
1
1
0
0
128/64
2980000299FFFF
14C000014CFFFF
SA333
1
0
1
0
0
1
1
0
1
128/64
29A000029BFFFF
14D000014DFFFF
SA334
1
0
1
0
0
1
1
1
0
128/64
29C000029DFFFF
14E000014EFFFF
SA335
1
0
1
0
0
1
1
1
1
128/64
29E000029FFFFF
14F000014FFFFF
SA336
1
0
1
0
1
0
0
0
0
128/64
2A000002A1FFFF
1500000150FFFF
SA337
1
0
1
0
1
0
0
0
1
128/64
2A200002A3FFFF
1510000151FFFF
SA338
1
0
1
0
1
0
0
1
0
128/64
2A400002A5FFFF
1520000152FFFF
SA339
1
0
1
0
1
0
0
1
1
128/64
2A600002A7FFFF
1530000153FFFF
SA340
1
0
1
0
1
0
1
0
0
128/64
2A800002A9FFFF
1540000154FFFF
SA341
1
0
1
0
1
0
1
0
1
128/64
2AA00002ABFFFF
1550000155FFFF
SA342
1
0
1
0
1
0
1
1
0
128/64
2AC00002ADFFFF
1560000156FFFF
SA343
1
0
1
0
1
0
1
1
1
128/64
2AE000002EFFFFF
1570000157FFFF
SA344
1
0
1
0
1
1
0
0
0
128/64
2B000002B1FFFF
1580000158FFFF
SA345
1
0
1
0
1
1
0
0
1
128/64
2B200002B3FFFF
1590000159FFFF
SA346
1
0
1
0
1
1
0
1
0
128/64
2B400002B5FFFF
15A000015AFFFF
SA347
1
0
1
0
1
1
0
1
1
128/64
2B600002B7FFFF
15B000015BFFFF
SA348
1
0
1
0
1
1
1
0
0
128/64
2B800002B9FFFF
15C000015CFFFF
SA349
1
0
1
0
1
1
1
0
1
128/64
2BA00002BBFFFF
15D000015DFFFF
SA350
1
0
1
0
1
1
1
1
0
128/64
2BC00002DFFFFF
15E000015EFFFF
SA351
1
0
1
0
1
1
1
1
1
128/64
2BE00002BFFFFF
15F000015FFFFF
SA352
1
0
1
1
0
0
0
0
0
128/64
2C000002C1FFFF
1600000160FFFF
SA353
1
0
1
1
0
0
0
0
1
128/64
2C200002C3FFFF
1610000161FFFF
SA354
1
0
1
1
0
0
0
1
0
128/64
2C400002C5FFFF
1620000162FFFF
SA355
1
0
1
1
0
0
0
1
1
128/64
2C600002C7FFFF
1630000163FFFF
SA356
1
0
1
1
0
0
1
0
0
128/64
2C800002C9FFFF
1640000164FFFF
SA357
1
0
1
1
0
0
1
0
1
128/64
2CA00002CBFFFF
1650000165FFFF
SA358
1
0
1
1
0
0
1
1
0
128/64
2CC00002CDFFFF
1660000166FFFF
SA359
1
0
1
1
0
0
1
1
1
128/64
2CE00002CFFFFF
1670000167FFFF
SA360
1
0
1
1
0
1
0
0
0
128/64
2D000002D1FFFF
1680000168FFFF
SA361
1
0
1
1
0
1
0
0
1
128/64
2D200002D3FFFF
1690000169FFFF
SA362
1
0
1
1
0
1
0
1
0
128/64
2D400002D5FFFF
16A000016AFFFF
SA363
1
0
1
1
0
1
0
1
1
128/64
2D600002D7FFFF
16B000016BFFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
29
A d v a n c e I n f o r m a t i o n
SA364
1
0
1
1
0
1
1
0
0
128/64
2D800002D9FFFF
16C000016CFFFF
SA365
1
0
1
1
0
1
1
0
1
128/64
2DA00002DBFFFF
16D000016DFFFF
SA366
1
0
1
1
0
1
1
1
0
128/64
2DC00002DDFFFF
16E000016EFFFF
SA367
1
0
1
1
0
1
1
1
1
128/64
2DE00002DFFFFF
16F000016FFFFF
SA368
1
0
1
1
1
0
0
0
0
128/64
2E000002E1FFFF
1700000170FFFF
SA369
1
0
1
1
1
0
0
0
1
128/64
2E200002E3FFFF
1710000171FFFF
SA370
1
0
1
1
1
0
0
1
0
128/64
2E400002E5FFFF
1720000172FFFF
SA371
1
0
1
1
1
0
0
1
1
128/64
2E600002E7FFFF
1730000173FFFF
SA372
1
0
1
1
1
0
1
0
0
128/64
2E800002E9FFFF
1740000174FFFF
SA373
1
0
1
1
1
0
1
0
1
128/64
2EA00002EBFFFF
1750000175FFFF
SA374
1
0
1
1
1
0
1
1
0
128/64
2EC00002EDFFFF
1760000176FFFF
SA375
1
0
1
1
1
0
1
1
1
128/64
2EE00002EFFFFF
1770000177FFFF
SA376
1
0
1
1
1
1
0
0
0
128/64
2F000002F1FFFF
1780000178FFFF
SA377
1
0
1
1
1
1
0
0
1
128/64
2F200002F3FFFF
1790000179FFFF
SA378
1
0
1
1
1
1
0
1
0
128/64
2F400002F5FFFF
17A000017AFFFF
SA379
1
0
1
1
1
1
0
1
1
128/64
2F600002F7FFFF
17B000017BFFFF
SA380
1
0
1
1
1
1
1
0
0
128/64
2F800002F9FFFF
17C000017CFFFF
SA381
1
0
1
1
1
1
1
0
1
128/64
2FA00002FBFFFF
17D000017DFFFF
SA382
1
0
1
1
1
1
1
1
0
128/64
2FC00002FDFFFF
17E000017EFFFF
SA383
1
0
1
1
1
1
1
1
1
128/64
3FE00003FFFFFF
17F000017FFFFF
SA384
1
1
0
0
0
0
0
0
0
128/64
3000000301FFFF
1800000180FFFF
SA385
1
1
0
0
0
0
0
0
1
128/64
3020000303FFFF
1810000181FFFF
SA386
1
1
0
0
0
0
0
1
0
128/64
3040000305FFFF
1820000182FFFF
SA387
1
1
0
0
0
0
0
1
1
128/64
3060000307FFFF
1830000183FFFF
SA388
1
1
0
0
0
0
1
0
0
128/64
3080000309FFFF
1840000184FFFF
SA389
1
1
0
0
0
0
1
0
1
128/64
30A000030BFFFF
1850000185FFFF
SA390
1
1
0
0
0
0
1
1
0
128/64
30C000030DFFFF
1860000186FFFF
SA391
1
1
0
0
0
0
1
1
1
128/64
30E000030FFFFF
1870000187FFFF
SA392
1
1
0
0
0
1
0
0
0
128/64
3100000311FFFF
1880000188FFFF
SA393
1
1
0
0
0
1
0
0
1
128/64
3120000313FFFF
1890000189FFFF
SA394
1
1
0
0
0
1
0
1
0
128/64
3140000315FFFF
18A000018AFFFF
SA395
1
1
0
0
0
1
0
1
1
128/64
3160000317FFFF
18B000018BFFFF
SA396
1
1
0
0
0
1
1
0
0
128/64
3180000319FFFF
18C000018CFFFF
SA397
1
1
0
0
0
1
1
0
1
128/64
31A000031BFFFF
18D000018DFFFF
SA398
1
1
0
0
0
1
1
1
0
128/64
31C000031DFFFF
18E000018EFFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
30
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA399
1
1
0
0
0
1
1
1
1
128/64
31E000031FFFFF
18F000018FFFFF
SA400
1
1
0
0
1
0
0
0
0
128/64
3200000321FFFF
1900000190FFFF
SA401
1
1
0
0
1
0
0
0
1
128/64
3220000323FFFF
1910000191FFFF
SA402
1
1
0
0
1
0
0
1
0
128/64
3240000325FFFF
1920000192FFFF
SA403
1
1
0
0
1
0
0
1
1
128/64
3260000327FFFF
1930000193FFFF
SA404
1
1
0
0
1
0
1
0
0
128/64
3280000329FFFF
1940000194FFFF
SA405
1
1
0
0
1
0
1
0
1
128/64
32A000032BFFFF
1950000195FFFF
SA406
1
1
0
0
1
0
1
1
0
128/64
32C000032DFFFF
1960000196FFFF
SA407
1
1
0
0
1
0
1
1
1
128/64
32E000032FFFFF
1970000197FFFF
SA408
1
1
0
0
1
1
0
0
0
128/64
3300000331FFFF
1980000198FFFF
SA409
1
1
0
0
1
1
0
0
1
128/64
3320000333FFFF
1990000199FFFF
SA410
1
1
0
0
1
1
0
1
0
128/64
3340000335FFFF
19A000019AFFFF
SA411
1
1
0
0
1
1
0
1
1
128/64
3360000337FFFF
19B000019BFFFF
SA412
1
1
0
0
1
1
1
0
0
128/64
3380000339FFFF
19C000019CFFFF
SA413
1
1
0
0
1
1
1
0
1
128/64
33A000033BFFFF
19D000019DFFFF
SA414
1
1
0
0
1
1
1
1
0
128/64
33C000033DFFFF
19E000019EFFFF
SA415
1
1
0
0
1
1
1
1
1
128/64
33E000033FFFFF
19F000019FFFFF
SA416
1
1
0
1
0
0
0
0
0
128/64
3400000341FFFF
1A000001A0FFFF
SA417
1
1
0
1
0
0
0
0
1
128/64
3420000343FFFF
1A100001A1FFFF
SA418
1
1
0
1
0
0
0
1
0
128/64
3440000345FFFF
1A200001A2FFFF
SA419
1
1
0
1
0
0
0
1
1
128/64
3460000347FFFF
1A300001A3FFFF
SA420
1
1
0
1
0
0
1
0
0
128/64
3480000349FFFF
1A400001A4FFFF
SA421
1
1
0
1
0
0
1
0
1
128/64
34A000034BFFFF
1A500001A5FFFF
SA422
1
1
0
1
0
0
1
1
0
128/64
34C000034DFFFF
1A600001A6FFFF
SA423
1
1
0
1
0
0
1
1
1
128/64
34E000034FFFFF
1A700001A7FFFF
SA424
1
1
0
1
0
1
0
0
0
128/64
3500000351FFFF
1A800001A8FFFF
SA425
1
1
0
1
0
1
0
0
1
128/64
3520000353FFFF
1A900001A9FFFF
SA426
1
1
0
1
0
1
0
1
0
128/64
3540000355FFFF
1AA00001AAFFFF
SA427
1
1
0
1
0
1
0
1
1
128/64
3560000357FFFF
1AB00001ABFFFF
SA428
1
1
0
1
0
1
1
0
0
128/64
3580000359FFFF
1AC00001ACFFFF
SA429
1
1
0
1
0
1
1
0
1
128/64
35A000035BFFFF
1AD00001ADFFFF
SA430
1
1
0
1
0
1
1
1
0
128/64
35C000035DFFFF
1AE00001AEFFFF
SA431
1
1
0
1
0
1
1
1
1
128/64
35E000035FFFFF
1AF00001AFFFFF
SA432
1
1
0
1
1
0
0
0
0
128/64
3600000361FFFF
1B000001B0FFFF
SA433
1
1
0
1
1
0
0
0
1
128/64
3620000363FFFF
1B100001B1FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
31
A d v a n c e I n f o r m a t i o n
SA434
1
1
0
1
1
0
0
1
0
128/64
3640000365FFFF
1B200001B2FFFF
SA435
1
1
0
1
1
0
0
1
1
128/64
3660000367FFFF
1B300001B3FFFF
SA436
1
1
0
1
1
0
1
0
0
128/64
3680000369FFFF
1B400001B4FFFF
SA437
1
1
0
1
1
0
1
0
1
128/64
36A000036BFFFF
1B500001B5FFFF
SA438
1
1
0
1
1
0
1
1
0
128/64
36C000036DFFFF
1B600001B6FFFF
SA439
1
1
0
1
1
0
1
1
1
128/64
36E000036FFFFF
1B700001B7FFFF
SA440
1
1
0
1
1
1
0
0
0
128/64
3700000371FFFF
1B800001B8FFFF
SA441
1
1
0
1
1
1
0
0
1
128/64
3720000373FFFF
1B900001B9FFFF
SA442
1
1
0
1
1
1
0
1
0
128/64
3740000375FFFF
1BA00001BAFFFF
SA443
1
1
0
1
1
1
0
1
1
128/64
3760000377FFFF
1BB00001BBFFFF
SA444
1
1
0
1
1
1
1
0
0
128/64
3780000379FFFF
1BC00001BCFFFF
SA445
1
1
0
1
1
1
1
0
1
128/64
37A000037BFFFF
1BD00001BDFFFF
SA446
1
1
0
1
1
1
1
1
0
128/64
37C000037DFFFF
1BE00001BEFFFF
SA447
1
1
0
1
1
1
1
1
1
128/64
37E000037FFFFF
1BF00001BFFFFF
SA448
1
1
1
0
0
0
0
0
0
128/64
3800000381FFFF
1C000001C0FFFF
SA449
1
1
1
0
0
0
0
0
1
128/64
3820000383FFFF
1C100001C1FFFF
SA450
1
1
1
0
0
0
0
1
0
128/64
3840000385FFFF
1C200001C2FFFF
SA451
1
1
1
0
0
0
0
1
1
128/64
3860000387FFFF
1C300001C3FFFF
SA452
1
1
1
0
0
0
1
0
0
128/64
3880000389FFFF
1C400001C4FFFF
SA453
1
1
1
0
0
0
1
0
1
128/64
38A000038BFFFF
1C500001C5FFFF
SA454
1
1
1
0
0
0
1
1
0
128/64
38C000038DFFFF
1C600001C6FFFF
SA455
1
1
1
0
0
0
1
1
1
128/64
38E000038FFFFF
1C700001C7FFFF
SA456
1
1
1
0
0
1
0
0
0
128/64
3900000391FFFF
1C800001C8FFFF
SA457
1
1
1
0
0
1
0
0
1
128/64
3920000393FFFF
1C900001C9FFFF
SA458
1
1
1
0
0
1
0
1
0
128/64
3940000395FFFF
1CA00001CAFFFF
SA459
1
1
1
0
0
1
0
1
1
128/64
3960000397FFFF
1CB00001CBFFFF
SA460
1
1
1
0
0
1
1
0
0
128/64
3980000399FFFF
1CC00001CCFFFF
SA461
1
1
1
0
0
1
1
0
1
128/64
39A000039BFFFF
1CD00001CDFFFF
SA462
1
1
1
0
0
1
1
1
0
128/64
39C000039DFFFF
1CE00001CEFFFF
SA463
1
1
1
0
0
1
1
1
1
128/64
39E000039FFFFF
1CF00001CFFFFF
SA464
1
1
1
0
1
0
0
0
0
128/64
3A000003A1FFFF
1D000001D0FFFF
SA465
1
1
1
0
1
0
0
0
1
128/64
3A200003A3FFFF
1D100001D1FFFF
SA466
1
1
1
0
1
0
0
1
0
128/64
3A400003A5FFFF
1D200001D2FFFF
SA467
1
1
1
0
1
0
0
1
1
128/64
3A600003A7FFFF
1D300001D3FFFF
SA468
1
1
1
0
1
0
1
0
0
128/64
3A800003A9FFFF
1D400001D4FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
32
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA469
1
1
1
0
1
0
1
0
1
128/64
3AA00003ABFFFF
1D500001D5FFFF
SA470
1
1
1
0
1
0
1
1
0
128/64
3AC00003ADFFFF
1D600001D6FFFF
SA471
1
1
1
0
1
0
1
1
1
128/64
3AE00003AFFFFF
1D700001D7FFFF
SA472
1
1
1
0
1
1
0
0
0
128/64
3B000003B1FFFF
1D800001D8FFFF
SA473
1
1
1
0
1
1
0
0
1
128/64
3B200003B3FFFF
1D900001D9FFFF
SA474
1
1
1
0
1
1
0
1
0
128/64
3B400003B5FFFF
1DA00001DAFFFF
SA475
1
1
1
0
1
1
0
1
1
128/64
3B600003B7FFFF
1DB00001DBFFFF
SA476
1
1
1
0
1
1
1
0
0
128/64
3B800003B9FFFF
1DC00001DCFFFF
SA477
1
1
1
0
1
1
1
0
1
128/64
3BA00003BBFFFF
1DD00001DDFFFF
SA478
1
1
1
0
1
1
1
1
0
128/64
3BC00003BDFFFF
1DE00001DEFFFF
SA479
1
1
1
0
1
1
1
1
1
128/64
3BE00003BFFFFF
1DF00001DFFFFF
SA480
1
1
1
1
0
0
0
0
0
128/64
3C000003C1FFFF
1E000001E0FFFF
SA481
1
1
1
1
0
0
0
0
1
128/64
3C200003C3FFFF
1E100001E1FFFF
SA482
1
1
1
1
0
0
0
1
0
128/64
3C400003C5FFFF
1E200001E2FFFF
SA483
1
1
1
1
0
0
0
1
1
128/64
3C600003C7FFFF
1E300001E3FFFF
SA484
1
1
1
1
0
0
1
0
0
128/64
3C800003C9FFFF
1E400001E4FFFF
SA485
1
1
1
1
0
0
1
0
1
128/64
3CA00003CBFFFF
1E500001E5FFFF
SA486
1
1
1
1
0
0
1
1
0
128/64
3CC00003CDFFFF
1E600001E6FFFF
SA487
1
1
1
1
0
0
1
1
1
128/64
3CE00003CFFFFF
1E700001E7FFFF
SA488
1
1
1
1
0
1
0
0
0
128/64
3D000003D1FFFFF
1E800001E8FFFF
SA489
1
1
1
1
0
1
0
0
1
128/64
3D200003D3FFFF
1E900001E9FFFF
SA490
1
1
1
1
0
1
0
1
0
128/64
3D400003D5FFFF
1EA00001EAFFFF
SA491
1
1
1
1
0
1
0
1
1
128/64
3D600003D7FFFF
1EB00001EBFFFF
SA492
1
1
1
1
0
1
1
0
0
128/64
3D800003D9FFFF
1EC00001ECFFFF
SA493
1
1
1
1
0
1
1
0
1
128/64
3DA00003DBFFFF
1ED00001EDFFFF
SA494
1
1
1
1
0
1
1
1
0
128/64
3DC00003DDFFFF
1EE00001EEFFFF
SA495
1
1
1
1
0
1
1
1
1
128/64
3DE00003DFFFFF
1EF00001EFFFFF
SA496
1
1
1
1
1
0
0
0
0
128/64
3E000003E1FFFF
1F000001F0FFFF
SA497
1
1
1
1
1
0
0
0
1
128/64
3E200003E3FFFF
1F100001F1FFFF
SA498
1
1
1
1
1
0
0
1
0
128/64
3E400003E5FFFF
1F200001F2FFFF
SA499
1
1
1
1
1
0
0
1
1
128/64
3E600003E7FFFF
1F300001F3FFFF
SA500
1
1
1
1
1
0
1
0
0
128/64
3E800003E9FFFF
1F400001F4FFFF
SA501
1
1
1
1
1
0
1
0
1
128/64
3EA00003EBFFFF
1F500001F5FFFF
SA502
1
1
1
1
1
0
1
1
0
128/64
3EC000003EDFFFF
1F600001F6FFFF
SA503
1
1
1
1
1
0
1
1
1
128/64
3EE00003EFFFFF
1F700001F7FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
33
A d v a n c e I n f o r m a t i o n
SA504
1
1
1
1
1
1
0
0
0
128/64
3F000003F1FFFF
1F800001F8FFFF
SA505
1
1
1
1
1
1
0
0
1
128/64
3F200003F3FFFF
1F900001F9FFFF
SA506
1
1
1
1
1
1
0
1
0
128/64
3F400003F5FFFF
1FA00001FAFFFF
SA507
1
1
1
1
1
1
0
1
1
128/64
3F600003F7FFFF
1FB00001FBFFFF
SA508
1
1
1
1
1
1
1
0
0
128/64
3F800003F9FFFF
1FC00001FCFFFF
SA509
1
1
1
1
1
1
1
0
1
128/64
3FA00003FBFFFF
1FD00001FDFFFF
SA510
1
1
1
1
1
1
1
1
0
128/64
3FC00003FDFFFF
1FE00001FEFFFF
SA511
1
1
1
1
1
1
1
1
1
128/64
3FE00003FFFFFF
1FF00001FFFFFF
Table 3. Sector Address TableS29GL256N
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
0
0
128/64
0000000001FFFF
0000000000FFFF
SA1
0
0
0
0
0
0
0
1
128/64
0020000003FFFF
0010000001FFFF
SA2
0
0
0
0
0
0
1
0
128/64
0040000005FFFF
0020000002FFFF
SA3
0
0
0
0
0
0
1
1
128/64
0060000007FFFF
0030000003FFFF
SA4
0
0
0
0
0
1
0
0
128/64
0080000009FFFF
0040000004FFFF
SA5
0
0
0
0
0
1
0
1
128/64
00A000000BFFFF
0050000005FFFF
SA6
0
0
0
0
0
1
1
0
128/64
00C000000DFFFF
0060000006FFFF
SA7
0
0
0
0
0
1
1
1
128/64
00E000000FFFFF
0070000007FFFF
SA8
0
0
0
0
1
0
0
0
128/64
0100000011FFFF
0080000008FFFF
SA9
0
0
0
0
1
0
0
1
128/64
0120000013FFFF
0090000009FFFF
SA10
0
0
0
0
1
0
1
0
128/64
0140000015FFFF
00A000000AFFFF
SA11
0
0
0
0
1
0
1
1
128/64
0160000017FFFF
00B000000BFFFF
SA12
0
0
0
0
1
1
0
0
128/64
0180000019FFFF
00C000000CFFFF
SA13
0
0
0
0
1
1
0
1
128/64
01A000001BFFFF
00D000000DFFFF
SA14
0
0
0
0
1
1
1
0
128/64
01C000001DFFFF
00E000000EFFFF
SA15
0
0
0
0
1
1
1
1
128/64
01E000001FFFFF
00F000000FFFFF
SA16
0
0
0
1
0
0
0
0
128/64
0200000021FFFF
0100000010FFFF
SA17
0
0
0
1
0
0
0
1
128/64
0220000023FFFF
0110000011FFFF
SA18
0
0
0
1
0
0
1
0
128/64
0240000025FFFF
0120000012FFFF
SA19
0
0
0
1
0
0
1
1
128/64
0260000027FFFF
0130000013FFFF
SA20
0
0
0
1
0
1
0
0
128/64
0280000029FFFF
0140000014FFFF
SA21
0
0
0
1
0
1
0
1
128/64
02A000002BFFFF
0150000015FFFF
Table 2. Sector Address TableS29GL512N (Continued)
Sector
A24A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
34
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA22
0
0
0
1
0
1
1
0
128/64
02C000002DFFFF
0160000016FFFF
SA23
0
0
0
1
0
1
1
1
128/64
02E000002FFFFF
0170000017FFFF
SA24
0
0
0
1
1
0
0
0
128/64
0300000031FFFF
0180000018FFFF
SA25
0
0
0
1
1
0
0
1
128/64
0320000033FFFF
0190000019FFFF
SA26
0
0
0
1
1
0
1
0
128/64
0340000035FFFF
01A000001AFFFF
SA27
0
0
0
1
1
0
1
1
128/64
0360000037FFFF
01B000001BFFFF
SA28
0
0
0
1
1
1
0
0
128/64
0380000039FFFF
01C000001CFFFF
SA29
0
0
0
1
1
1
0
1
128/64
03A000003BFFFF
01D000001DFFFF
SA30
0
0
0
1
1
1
1
0
128/64
03C000003DFFFF
01E000001EFFFF
SA31
0
0
0
1
1
1
1
1
128/64
03E000003FFFFF
01F000001FFFFF
SA32
0
0
1
0
0
0
0
0
128/64
0400000041FFFF
0200000020FFFF
SA33
0
0
1
0
0
0
0
1
128/64
0420000043FFFF
0210000021FFFF
SA34
0
0
1
0
0
0
1
0
128/64
0440000045FFFF
0220000022FFFF
SA35
0
0
1
0
0
0
1
1
128/64
0460000047FFFF
0230000023FFFF
SA36
0
0
1
0
0
1
0
0
128/64
0480000049FFFF
0240000024FFFF
SA37
0
0
1
0
0
1
0
1
128/64
04A000004BFFFF
0250000025FFFF
SA38
0
0
1
0
0
1
1
0
128/64
04C000004DFFFF
0260000026FFFF
SA39
0
0
1
0
0
1
1
1
128/64
04E000004FFFFF
0270000027FFFF
SA40
0
0
1
0
1
0
0
0
128/64
0500000051FFFF
0280000028FFFF
SA41
0
0
1
0
1
0
0
1
128/64
0520000053FFFF
0290000029FFFF
SA42
0
0
1
0
1
0
1
0
128/64
0540000055FFFF
02A000002AFFFF
SA43
0
0
1
0
1
0
1
1
128/64
0560000057FFFF
02B000002BFFFF
SA44
0
0
1
0
1
1
0
0
128/64
0580000059FFFF
02C000002CFFFF
SA45
0
0
1
0
1
1
0
1
128/64
05A000005BFFFF
02D000002DFFFF
SA46
0
0
1
0
1
1
1
0
128/64
05C000005DFFFF
02E000002EFFFF
SA47
0
0
1
0
1
1
1
1
128/64
05E000005FFFFF
02F000002FFFFF
SA48
0
0
1
1
0
0
0
0
128/64
0600000061FFFF
0300000030FFFF
SA49
0
0
1
1
0
0
0
1
128/64
0620000063FFFF
0310000031FFFF
SA50
0
0
1
1
0
0
1
0
128/64
0640000065FFFF
0320000032FFFF
SA51
0
0
1
1
0
0
1
1
128/64
0660000067FFFF
0330000033FFFF
SA52
0
0
1
1
0
1
0
0
128/64
0680000069FFFF
0340000034FFFF
SA53
0
0
1
1
0
1
0
1
128/64
06A000006BFFFF
0350000035FFFF
SA54
0
0
1
1
0
1
1
0
128/64
06C000006DFFFF
0360000036FFFF
SA55
0
0
1
1
0
1
1
1
128/64
06E000006FFFFF
0370000037FFFF
SA56
0
0
1
1
1
0
0
0
128/64
0700000071FFFF
0380000038FFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
35
A d v a n c e I n f o r m a t i o n
SA57
0
0
1
1
1
0
0
1
128/64
0720000073FFFF
0390000039FFFF
SA58
0
0
1
1
1
0
1
0
128/64
0740000075FFFF
03A000003AFFFF
SA59
0
0
1
1
1
0
1
1
128/64
0760000077FFFF
03B000003BFFFF
SA60
0
0
1
1
1
1
0
0
128/64
0780000079FFFF
03C000003CFFFF
SA61
0
0
1
1
1
1
0
1
128/64
07A00007BFFFF
03D000003DFFFF
SA62
0
0
1
1
1
1
1
0
128/64
07C000007DFFFF
03E000003EFFFF
SA63
0
0
1
1
1
1
1
1
128/64
07E000007FFFFF0
03F000003FFFFF
SA64
0
1
0
0
0
0
0
0
128/64
0800000081FFFF
0400000040FFFF
SA65
0
1
0
0
0
0
0
1
128/64
0820000083FFFF
0410000041FFFF
SA66
0
1
0
0
0
0
1
0
128/64
0840000085FFFF
0420000042FFFF
SA67
0
1
0
0
0
0
1
1
128/64
0860000087FFFF
0430000043FFFF
SA68
0
1
0
0
0
1
0
0
128/64
0880000089FFFF
0440000044FFFF
SA69
0
1
0
0
0
1
0
1
128/64
08A000008BFFFF
0450000045FFFF
SA70
0
1
0
0
0
1
1
0
128/64
08C000008DFFFF
0460000046FFFF
SA71
0
1
0
0
0
1
1
1
128/64
08E000008FFFFF
0470000047FFFF
SA72
0
1
0
0
1
0
0
0
128/64
0900000091FFFF
0480000048FFFF
SA73
0
1
0
0
1
0
0
1
128/64
0920000093FFFF
0490000049FFFF
SA74
0
1
0
0
1
0
1
0
128/64
0940000095FFFF
04A000004AFFFF
SA75
0
1
0
0
1
0
1
1
128/64
0960000097FFFF
04B000004BFFFF
SA76
0
1
0
0
1
1
0
0
128/64
0980000099FFFF
04C000004CFFFF
SA77
0
1
0
0
1
1
0
1
128/64
09A000009BFFFF
04D000004DFFFF
SA78
0
1
0
0
1
1
1
0
128/64
09C000009DFFFF
04E000004EFFFF
SA79
0
1
0
0
1
1
1
1
128/64
09E000009FFFFF
04F000004FFFFF
SA80
0
1
0
1
0
0
0
0
128/64
0A000000A1FFFF
0500000050FFFF
SA81
0
1
0
1
0
0
0
1
128/64
0A200000A3FFFF
0510000051FFFF
SA82
0
1
0
1
0
0
1
0
128/64
0A40000045FFFF
0520000052FFFF
SA83
0
1
0
1
0
0
1
1
128/64
0A600000A7FFFF
0530000053FFFF
SA84
0
1
0
1
0
1
0
0
128/64
0A800000A9FFFF
0540000054FFFF
SA85
0
1
0
1
0
1
0
1
128/64
0AA00000ABFFFF
0550000055FFFF
SA86
0
1
0
1
0
1
1
0
128/64
0AC00000ADFFFF
0560000056FFFF
SA87
0
1
0
1
0
1
1
1
128/64
0AE0000AEFFFFF
0570000057FFFF
SA88
0
1
0
1
1
0
0
0
128/64
0B000000B1FFFF
0580000058FFFF
SA89
0
1
0
1
1
0
0
1
128/64
0B200000B3FFFF
0590000059FFFF
SA90
0
1
0
1
1
0
1
0
128/64
0B400000B5FFFF
05A000005AFFFF
SA91
0
1
0
1
1
0
1
1
128/64
0B600000B7FFFF
05B000005BFFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
36
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA92
0
1
0
1
1
1
0
0
128/64
0B800000B9FFFF
05C000005CFFFF
SA93
0
1
0
1
1
1
0
1
128/64
0BA00000BBFFFF
05D000005DFFFF
SA94
0
1
0
1
1
1
1
0
128/64
0BC00000BDFFFF
05E000005EFFFF
SA95
0
1
0
1
1
1
1
1
128/64
0BE00000BFFFFF
05F000005FFFFF
SA96
0
1
1
0
0
0
0
0
128/64
0C000000C1FFFF
0600000060FFFF
SA97
0
1
1
0
0
0
0
1
128/64
0C200000C3FFFF
0610000061FFFF
SA98
0
1
1
0
0
0
1
0
128/64
0C400000C5FFFF
0620000062FFFF
SA99
0
1
1
0
0
0
1
1
128/64
0C600000C7FFFF
0630000063FFFF
SA100
0
1
1
0
0
1
0
0
128/64
0C800000C9FFFF
0640000064FFFF
SA101
0
1
1
0
0
1
0
1
128/64
0CA00000CBFFFF
0650000065FFFF
SA102
0
1
1
0
0
1
1
0
128/64
0CC00000CDFFFF
0660000066FFFF
SA103
0
1
1
0
0
1
1
1
128/64
0CE00000CFFFFF
0670000067FFFF
SA104
0
1
1
0
1
0
0
0
128/64
0D000000D1FFFF
0680000068FFFF
SA105
0
1
1
0
1
0
0
1
128/64
0D200000D3FFFF
0690000069FFFF
SA106
0
1
1
0
1
0
1
0
128/64
0D400000D5FFFF
06A000006AFFFF
SA107
0
1
1
0
1
0
1
1
128/64
0D600000D7FFFF
06B000006BFFFF
SA108
0
1
1
0
1
1
0
0
128/64
0D800000D9FFFF
06C000006CFFFF
SA109
0
1
1
0
1
1
0
1
128/64
0DA00000DBFFFF
06D000006DFFFF
SA110
0
1
1
0
1
1
1
0
128/64
0DC00000DDFFFF
06E000006EFFFF
SA111
0
1
1
0
1
1
1
1
128/64
0DE00000DFFFFF
06F000006FFFFF
SA112
0
1
1
1
0
0
0
0
128/64
0E000000E1FFFF
0700000070FFFF
SA113
0
1
1
1
0
0
0
1
128/64
0E200000E3FFFF
0710000071FFFF
SA114
0
1
1
1
0
0
1
0
128/64
0E400000E5FFFF
0720000072FFFF
SA115
0
1
1
1
0
0
1
1
128/64
0E600000E7FFFF
0730000073FFFF
SA116
0
1
1
1
0
1
0
0
128/64
0E800000E9FFFF
0740000074FFFF
SA117
0
1
1
1
0
1
0
1
128/64
0EA00000EBFFFF
0750000075FFFF
SA118
0
1
1
1
0
1
1
0
128/64
0EC00000EDFFFF
0760000076FFFF
SA119
0
1
1
1
0
1
1
1
128/64
0EE00000EFFFFF
0770000077FFFF
SA120
0
1
1
1
1
0
0
0
128/64
0F000000F1FFFF
0780000078FFFF
SA121
0
1
1
1
1
0
0
1
128/64
0F200000F3FFFF
0790000079FFFF
SA122
0
1
1
1
1
0
1
0
128/64
0F400000F5FFFF
07A000007AFFFF
SA123
0
1
1
1
1
0
1
1
128/64
0F600000F7FFFF
07B000007BFFFF
SA124
0
1
1
1
1
1
0
0
128/64
0F800000F9FFFF
07C000007CFFFF
SA125
0
1
1
1
1
1
0
1
128/64
0FA00000FBFFFF
07D000007DFFFF
SA126
0
1
1
1
1
1
1
0
128/64
0FC00000FDFFFF
07E000007EFFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
37
A d v a n c e I n f o r m a t i o n
SA127
0
1
1
1
1
1
1
1
128/64
0FE00000FFFFFF
07F000007FFFFF
SA128
1
0
0
0
0
0
0
0
128/64
1000000101FFFF
0800000080FFFF
SA129
1
0
0
0
0
0
0
1
128/64
1020000103FFFF
0810000081FFFF
SA130
1
0
0
0
0
0
1
0
128/64
1040000105FFFF
0820000082FFFF
SA131
1
0
0
0
0
0
1
1
128/64
1060000107FFFF
0830000083FFFF
SA132
1
0
0
0
0
1
0
0
128/64
1080000109FFFF
0840000084FFFF
SA133
1
0
0
0
0
1
0
1
128/64
10A000010BFFFF
0850000085FFFF
SA134
1
0
0
0
0
1
1
0
128/64
10C000010DFFFF
0860000086FFFF
SA135
1
0
0
0
0
1
1
1
128/64
10E000010FFFFF
0870000087FFFF
SA136
1
0
0
0
1
0
0
0
128/64
1100000111FFFF
0880000088FFFF
SA137
1
0
0
0
1
0
0
1
128/64
1120000113FFFF
0890000089FFFF
SA138
1
0
0
0
1
0
1
0
128/64
1140000115FFFF
08A000008AFFFF
SA139
1
0
0
0
1
0
1
1
128/64
1160000117FFFF
08B000008BFFFF
SA140
1
0
0
0
1
1
0
0
128/64
1180000119FFFF
08C000008CFFFF
SA141
1
0
0
0
1
1
0
1
128/64
11A000011BFFFF
08D000008DFFFF
SA142
1
0
0
0
1
1
1
0
128/64
11C000011DFFFF
08E000008EFFFF
SA143
1
0
0
0
1
1
1
1
128/64
11E000011FFFFF
08F000008FFFFF
SA144
1
0
0
1
0
0
0
0
128/64
1200000121FFFF
0900000090FFFF
SA145
1
0
0
1
0
0
0
1
128/64
1220000123FFFF
0910000091FFFF
SA146
1
0
0
1
0
0
1
0
128/64
1240000125FFFF
0920000092FFFF
SA147
1
0
0
1
0
0
1
1
128/64
1260000127FFFF
0930000093FFFF
SA148
1
0
0
1
0
1
0
0
128/64
1280000129FFFF
0940000094FFFF
SA149
1
0
0
1
0
1
0
1
128/64
12A000012BFFFF
0950000095FFFF
SA150
1
0
0
1
0
1
1
0
128/64
12C000012DFFFF
0960000096FFFF
SA151
1
0
0
1
0
1
1
1
128/64
12E000012FFFFF
0970000097FFFF
SA152
1
0
0
1
1
0
0
0
128/64
1300000131FFFF
0980000098FFFF
SA153
1
0
0
1
1
0
0
1
128/64
1320000133FFFF
0990000099FFFF
SA154
1
0
0
1
1
0
1
0
128/64
1340000135FFFF
09A000009AFFFF
SA155
1
0
0
1
1
0
1
1
128/64
1360000137FFFF
09B000009BFFFF
SA156
1
0
0
1
1
1
0
0
128/64
1380000139FFFF
09C000009CFFFF
SA157
1
0
0
1
1
1
0
1
128/64
13A000013BFFFF
09D000009DFFFF
SA158
1
0
0
1
1
1
1
0
128/64
13C000013DFFFF
09E000009EFFFF
SA159
1
0
0
1
1
1
1
1
128/64
13E000013FFFFF
09F000009FFFFF
SA160
1
0
1
0
0
0
0
0
128/64
1400000141FFFF
0A000000A0FFFF
SA161
1
0
1
0
0
0
0
1
128/64
1420000143FFFF
0A100000A1FFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
38
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA162
1
0
1
0
0
0
1
0
128/64
1440000145FFFF
0A200000A2FFFF
SA163
1
0
1
0
0
0
1
1
128/64
1460000147FFFF
0A300000A3FFFF
SA164
1
0
1
0
0
1
0
0
128/64
1480000149FFFF
0A400000A4FFFF
SA165
1
0
1
0
0
1
0
1
128/64
14A000014BFFFF
0A500000A5FFFF
SA166
1
0
1
0
0
1
1
0
128/64
14C000014DFFFF
0A600000A6FFFF
SA167
1
0
1
0
0
1
1
1
128/64
14E000014FFFFF
0A700000A7FFFF
SA168
1
0
1
0
1
0
0
0
128/64
1500000151FFFF
0A800000A8FFFF
SA169
1
0
1
0
1
0
0
1
128/64
1520000153FFFF
0A900000A9FFFF
SA170
1
0
1
0
1
0
1
0
128/64
1540000155FFFF
0AA00000AAFFFF
SA171
1
0
1
0
1
0
1
1
128/64
1560000157FFFF
0AB00000ABFFFF
SA172
1
0
1
0
1
1
0
0
128/64
1580000159FFFF
0AC00000ACFFFF
SA173
1
0
1
0
1
1
0
1
128/64
15A000015BFFFF
0AD00000ADFFFF
SA174
1
0
1
0
1
1
1
0
128/64
15C000015DFFFF
0AE00000AEFFFF
SA175
1
0
1
0
1
1
1
1
128/64
15E000015FFFFF
0AF00000AFFFFF
SA176
1
0
1
1
0
0
0
0
128/64
1600000161FFFF
0B000000B0FFFF
SA177
1
0
1
1
0
0
0
1
128/64
1620000163FFFF
0B100000B1FFFF
SA178
1
0
1
1
0
0
1
0
128/64
1640000165FFFFF
0B200000B2FFFF
SA179
1
0
1
1
0
0
1
1
128/64
1660000167FFFF
0B300000B3FFFF
SA180
1
0
1
1
0
1
0
0
128/64
1680000169FFFF
0B400000B4FFFF
SA181
1
0
1
1
0
1
0
1
128/64
16A000016BFFFF
0B500000B5FFFF
SA182
1
0
1
1
0
1
1
0
128/64
16C000016DFFFF
0B600000B6FFFF
SA183
1
0
1
1
0
1
1
1
128/64
16E000016FFFFF
0B700000B7FFFF
SA184
1
0
1
1
1
0
0
0
128/64
1700000171FFFF
0B800000B8FFFF
SA185
1
0
1
1
1
0
0
1
128/64
1720000173FFFF
0B900000B9FFFF
SA186
1
0
1
1
1
0
1
0
128/64
1740000175FFFF
0BA00000BAFFFF
SA187
1
0
1
1
1
0
1
1
128/64
1760000177FFFF
0BB00000BBFFFF
SA188
1
0
1
1
1
1
0
0
128/64
1780000179FFFF
0BC00000BCFFFF
SA189
1
0
1
1
1
1
0
1
128/64
17A000017BFFFF
0BD00000BDFFFF
SA190
1
0
1
1
1
1
1
0
128/64
17C000017DFFFF
0BE00000BEFFFF
SA191
1
0
1
1
1
1
1
1
128/64
17E000017FFFFF
0BF00000BFFFFF
SA192
1
1
0
0
0
0
0
0
128/64
1800000181FFFF
0C000000C0FFFF
SA193
1
1
0
0
0
0
0
1
128/64
1820000183FFFF
0C100000C1FFFF
SA194
1
1
0
0
0
0
1
0
128/64
1840000185FFFF
0C200000C2FFFF
SA195
1
1
0
0
0
0
1
1
128/64
1860000187FFFF
0C300000C3FFFF
SA196
1
1
0
0
0
1
0
0
128/64
1880000189FFFF
0C400000C4FFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
39
A d v a n c e I n f o r m a t i o n
SA197
1
1
0
0
0
1
0
1
128/64
18A000018BFFFF
0C500000C5FFFF
SA198
1
1
0
0
0
1
1
0
128/64
18C000018DFFFF
0C600000C6FFFF
SA199
1
1
0
0
0
1
1
1
128/64
18E000018FFFFF
0C700000C7FFFF
SA200
1
1
0
0
1
0
0
0
128/64
1900000191FFFF
0C800000C8FFFF
SA201
1
1
0
0
1
0
0
1
128/64
1920000193FFFF
0C900000C9FFFF
SA202
1
1
0
0
1
0
1
0
128/64
1940000195FFFF
0CA00000CAFFFF
SA203
1
1
0
0
1
0
1
1
128/64
1960000197FFFF
0CB00000CBFFFF
SA204
1
1
0
0
1
1
0
0
128/64
1980000199FFFF
0CC00000CCFFFF
SA205
1
1
0
0
1
1
0
1
128/64
19A000019BFFFF
0CD00000CDFFFF
SA206
1
1
0
0
1
1
1
0
128/64
19C000019DFFFF
0CE00000CEFFFF
SA207
1
1
0
0
1
1
1
1
128/64
19E000019FFFF
0CF00000CFFFFF
SA208
1
1
0
1
0
0
0
0
128/64
1A000001A1FFFF
0D000000D0FFFF
SA209
1
1
0
1
0
0
0
1
128/64
1A200001A3FFFF
0D100000D1FFFF
SA210
1
1
0
1
0
0
1
0
128/64
1A400001A5FFFF
0D200000D2FFFF
SA211
1
1
0
1
0
0
1
1
128/64
1A600001A7FFFF
0D300000D3FFFF
SA212
1
1
0
1
0
1
0
0
128/64
1A800001A9FFFF
0D400000D4FFFF
SA213
1
1
0
1
0
1
0
1
128/64
1AA00001ABFFFF
0D500000D5FFFF
SA214
1
1
0
1
0
1
1
0
128/64
1AC00001ADFFFF
0D600000D6FFFF
SA215
1
1
0
1
0
1
1
1
128/64
1AE00001AFFFFF
0D700000D7FFFF
SA216
1
1
0
1
1
0
0
0
128/64
1B000001B1FFFF
0D800000D8FFFF
SA217
1
1
0
1
1
0
0
1
128/64
1B200001B3FFFF
0D900000D9FFFF
SA218
1
1
0
1
1
0
1
0
128/64
1B400001B5FFFF
0DA00000DAFFFF
SA219
1
1
0
1
1
0
1
1
128/64
1B600001B7FFFF
0DB00000DBFFFF
SA220
1
1
0
1
1
1
0
0
128/64
1B800001B9FFFF
0DC00000DCFFFF
SA221
1
1
0
1
1
1
0
1
128/64
1BA00001BBFFFF
0DD00000DDFFFF
SA222
1
1
0
1
1
1
1
0
128/64
1BC00001BDFFFF
0DE00000DEFFFF
SA223
1
1
0
1
1
1
1
1
128/64
1BE00001BFFFFF
0DF00000DFFFFF
SA224
1
1
1
0
0
0
0
0
128/64
1C000001C1FFFF
0E000000E0FFFF
SA225
1
1
1
0
0
0
0
1
128/64
1C200001C3FFFF
0E100000E1FFFF
SA226
1
1
1
0
0
0
1
0
128/64
1C400001C5FFFF
0E200000E2FFFF
SA227
1
1
1
0
0
0
1
1
128/64
1C600001C7FFFF
0E300000E3FFFF
SA228
1
1
1
0
0
1
0
0
128/64
1C800001C9FFFF
0E400000E4FFFF
SA229
1
1
1
0
0
1
0
1
128/64
1CA00001CBFFFF
0E500000E5FFFF
SA230
1
1
1
0
0
1
1
0
128/64
1CC00001CDFFFF
0E600000E6FFFF
SA231
1
1
1
0
0
1
1
1
128/64
1CE00001CFFFFF
0E700000E7FFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
40
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA232
1
1
1
0
1
0
0
0
128/64
1D000001D1FFFF
0E800000E8FFFF
SA233
1
1
1
0
1
0
0
1
128/64
1D200001D3FFFF
0E900000E9FFFF
SA234
1
1
1
0
1
0
1
0
128/64
1D400001D5FFFF
0EA00000EAFFFF
SA235
1
1
1
0
1
0
1
1
128/64
1D600001D7FFFF
0EB00000EBFFFF
SA236
1
1
1
0
1
1
0
0
128/64
1D800001D9FFFF
0EC00000ECFFFF
SA237
1
1
1
0
1
1
0
1
128/64
1DA00001DBFFFF
0ED00000EDFFFF
SA238
1
1
1
0
1
1
1
0
128/64
1DC00001DDFFFF
0EE00000EEFFFF
SA239
1
1
1
0
1
1
1
1
128/64
1DE00001DFFFFF
0EF00000EFFFFF
SA240
1
1
1
1
0
0
0
0
128/64
1E000001E1FFFF
0F000000F0FFFF
SA241
1
1
1
1
0
0
0
1
128/64
1E200001E3FFFF
0F100000F1FFFF
SA242
1
1
1
1
0
0
1
0
128/64
1E400001E5FFFF
0F200000F2FFFF
SA243
1
1
1
1
0
0
1
1
128/64
1E60000137FFFF
0F300000F3FFFF
SA244
1
1
1
1
0
1
0
0
128/64
1E800001E9FFFF
0F400000F4FFFF
SA245
1
1
1
1
0
1
0
1
128/64
1EA00001EBFFFF
0F500000F5FFFF
SA246
1
1
1
1
0
1
1
0
128/64
1EC00001EDFFFF
0F600000F6FFFF
SA247
1
1
1
1
0
1
1
1
128/64
1EE00001EFFFFF
0F700000F7FFFF
SA248
1
1
1
1
1
0
0
0
128/64
1F000001F1FFFF
0F800000F8FFFF
SA249
1
1
1
1
1
0
0
1
128/64
1F200001F3FFFF
0F900000F9FFFF
SA250
1
1
1
1
1
0
1
0
128/64
1F400001F5FFFF
0FA00000FAFFFF
SA251
1
1
1
1
1
0
1
1
128/64
1F600001F7FFFF
0FB00000FBFFFF
SA252
1
1
1
1
1
1
0
0
128/64
1F800001F9FFFF
0FC00000FCFFFF
SA253
1
1
1
1
1
1
0
1
128/64
1FA00001FBFFFF
0FD00000FDFFFF
SA254
1
1
1
1
1
1
1
0
128/64
1FC00001FDFFFF
0FE00000FEFFFF
SA255
1
1
1
1
1
1
1
1
128/64
1FE00001FFFFFF
0FF00000FFFFFF
Table 4. Sector Address TableS29GL128N
Sector
A22A16
Sector Size
(Kbytes/
Kwords)
8-Bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
128/64
0000000001FFFF
0000000000FFFF
SA1
0
0
0
0
0
1
128/64
0020000003FFFF
0010000001FFFF
SA2
0
0
0
0
1
0
128/64
0040000005FFFF
0020000002FFFF
SA3
0
0
0
0
1
1
128/64
0060000007FFFF
0030000003FFFF
SA4
0
0
0
1
0
0
128/64
0080000009FFFF
0040000004FFFF
SA5
0
0
0
1
0
1
128/64
00A000000BFFFF
0050000005FFFF
Table 3. Sector Address TableS29GL256N (Continued)
Sector
A23A16
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
41
A d v a n c e I n f o r m a t i o n
SA6
0
0
0
1
1
0
128/64
00C000000DFFFF
0060000006FFFF
SA7
0
0
0
1
1
1
128/64
00E000000FFFFF
0070000007FFFF
SA8
0
0
1
0
0
0
128/64
0100000011FFFF
0080000008FFFF
SA9
0
0
1
0
0
1
128/64
0120000013FFFF
0090000009FFFF
SA10
0
0
1
0
1
0
128/64
0140000015FFFF
00A000000AFFFF
SA11
0
0
1
0
1
1
128/64
0160000017FFFF
00B000000BFFFF
SA12
0
0
1
1
0
0
128/64
0180000019FFFF
00C000000CFFFF
SA13
0
0
1
1
0
1
128/64
01A000001BFFFF
00D000000DFFFF
SA14
0
0
1
1
1
0
128/64
01C000001DFFFF
00E000000EFFFF
SA15
0
0
1
1
1
1
128/64
01E000001FFFFF
00F000000FFFFF
SA16
0
1
0
0
0
0
128/64
0200000021FFFF
0100000010FFFF
SA17
0
1
0
0
0
1
128/64
0220000023FFFF
0110000011FFFF
SA18
0
1
0
0
1
0
128/64
0240000025FFFF
0120000012FFFF
SA19
0
1
0
0
1
1
128/64
0260000027FFFF
0130000013FFFF
SA20
0
1
0
1
0
0
128/64
0280000029FFFF
0140000014FFFF
SA21
0
1
0
1
0
1
128/64
02A000002BFFFF
0150000015FFFF
SA22
0
1
0
1
1
0
128/64
02C000002DFFFF
0160000016FFFF
SA23
0
1
0
1
1
1
128/64
02E000002FFFFF
0170000017FFFF
SA24
0
1
1
0
0
0
128/64
0300000031FFFF
0180000018FFFF
SA25
0
1
1
0
0
1
128/64
0320000033FFFF
0190000019FFFF
SA26
0
1
1
0
1
0
128/64
0340000035FFFF
01A000001AFFFF
SA27
0
1
1
0
1
1
128/64
0360000037FFFF
01B000001BFFFF
SA28
0
1
1
1
0
0
128/64
0380000039FFFF
01C000001CFFFF
SA29
0
1
1
1
0
1
128/64
03A000003BFFFF
01D000001DFFFF
SA30
0
1
1
1
1
0
128/64
03C000003DFFFF
01E000001EFFFF
SA31
0
1
1
1
1
1
128/64
03E000003FFFFF
01F000001FFFFF
SA32
1
0
0
0
0
0
128/64
0400000041FFFF
0200000020FFFF
SA33
1
0
0
0
0
1
128/64
0420000043FFFF
0210000021FFFF
SA34
1
0
0
0
1
0
128/64
0440000045FFFF
0220000022FFFF
SA35
1
0
0
0
1
1
128/64
0460000047FFFF
0230000023FFFF
SA36
1
0
0
1
0
0
128/64
0480000049FFFF
0240000024FFFF
SA37
1
0
0
1
0
1
128/64
04A000004BFFFF
0250000025FFFF
SA38
1
0
0
1
1
0
128/64
04C000004DFFFF
0260000026FFFF
SA39
1
0
0
1
1
1
128/64
04E000004FFFFF
0270000027FFFF
SA40
1
0
1
0
0
0
128/64
0500000051FFFF
0280000028FFFF
Table 4. Sector Address TableS29GL128N (Continued)
Sector
A22A16
Sector Size
(Kbytes/
Kwords)
8-Bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
42
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
SA41
1
0
1
0
0
1
128/64
0520000053FFFF
0290000029FFFF
SA42
1
0
1
0
1
0
128/64
0540000055FFFF
02A000002AFFFF
SA43
1
0
1
0
1
1
128/64
0560000057FFFF
02B000002BFFFF
SA44
1
0
1
1
0
0
128/64
0580000059FFFF
02C000002CFFFF
SA45
1
0
1
1
0
1
128/64
05A000005BFFFF
02D000002DFFFF
SA46
1
0
1
1
1
0
128/64
05C000005DFFFF
02E000002EFFFF
SA47
1
0
1
1
1
1
128/64
05E000005FFFFF
02F000002FFFFF
SA48
1
1
0
0
0
0
128/64
0600000061FFFF
0300000030FFFF
SA49
1
1
0
0
0
1
128/64
0620000063FFFF
0310000031FFFF
SA50
1
1
0
0
1
0
128/64
0640000065FFFF
0320000032FFFF
SA51
1
1
0
0
1
1
128/64
0660000067FFFF
0330000033FFFF
SA52
1
1
0
1
0
0
128/64
0680000069FFFF
0340000034FFFF
SA53
1
1
0
1
0
1
128/64
06A000006BFFFF
0350000035FFFF
SA54
1
1
0
1
1
0
128/64
06C000006DFFFF
0360000036FFFF
SA55
1
1
0
1
1
1
128/64
06E000006FFFFF
0370000037FFFF
SA56
1
1
1
0
0
0
128/64
0700000071FFFF
0380000038FFFF
SA57
1
1
1
0
0
1
128/64
0720000073FFFF
0390000039FFFF
SA58
1
1
1
0
1
0
128/64
0740000075FFFF
03A000003AFFFF
SA59
1
1
1
0
1
1
128/64
0760000077FFFF
03B000003BFFFF
SA60
1
1
1
1
0
0
128/64
0780000079FFFF
03C000003CFFFF
SA61
1
1
1
1
0
1
128/64
07A000007BFFFF
03D000003DFFFF
SA62
1
1
1
1
1
0
128/64
07C000007DFFFF
03E000003EFFFF
SA63
1
1
1
1
1
1
128/64
07E000007FFFFF
03F000003FFFFF
SA64
0
0
0
0
0
0
128/64
0800000081FFFF
0400000040FFFF
SA65
0
0
0
0
0
1
128/64
0820000083FFFF
0410000041FFFF
SA66
0
0
0
0
1
0
128/64
0840000085FFFF
0420000042FFFF
SA67
0
0
0
0
1
1
128/64
0860000087FFFF
0430000043FFFF
SA68
0
0
0
1
0
0
128/64
0880000089FFFF
0440000044FFFF
SA69
0
0
0
1
0
1
128/64
08A000008BFFFF
0450000045FFFF
SA70
0
0
0
1
1
0
128/64
08C000008DFFFF
0460000046FFFF
SA71
0
0
0
1
1
1
128/64
08E000008FFFFF
0470000047FFFF
SA72
0
0
1
0
0
0
128/64
0900000091FFFF
0480000048FFFF
SA73
0
0
1
0
0
1
128/64
0920000093FFFF
0490000049FFFF
SA74
0
0
1
0
1
0
128/64
0940000095FFFF
04A000004AFFFF
SA75
0
0
1
0
1
1
128/64
0960000097FFFF
04B000004BFFFF
Table 4. Sector Address TableS29GL128N (Continued)
Sector
A22A16
Sector Size
(Kbytes/
Kwords)
8-Bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
43
A d v a n c e I n f o r m a t i o n
SA76
0
0
1
1
0
0
128/64
0980000099FFFF
04C000004CFFFF
SA77
0
0
1
1
0
1
128/64
09A000009BFFFF
04D000004DFFFF
SA78
0
0
1
1
1
0
128/64
09C000009DFFFF
04E000004EFFFF
SA79
0
0
1
1
1
1
128/64
09E000009FFFFF
04F000004FFFFF
SA80
0
1
0
0
0
0
128/64
0A000000A1FFFF
0500000050FFFF
SA81
0
1
0
0
0
1
128/64
0A200000A3FFFF
0510000051FFFF
SA82
0
1
0
0
1
0
128/64
0A400000A5FFFF
0520000052FFFF
SA83
0
1
0
0
1
1
128/64
0A600000A7FFFF
0530000053FFFF
SA84
0
1
0
1
0
0
128/64
0A800000A9FFFF
0540000054FFFF
SA85
0
1
0
1
0
1
128/64
0AA00000ABFFFF
0550000055FFFF
SA86
0
1
0
1
1
0
128/64
0AC00000ADFFFF
0560000056FFFF
SA87
0
1
0
1
1
1
128/64
0AE00000AFFFFF
0570000057FFFF
SA88
0
1
1
0
0
0
128/64
0B000000B1FFFF
0580000058FFFF
SA89
0
1
1
0
0
1
128/64
0B200000B3FFFF
0590000059FFFF
SA90
0
1
1
0
1
0
128/64
0B400000B5FFFF
05A000005AFFFF
SA91
0
1
1
0
1
1
128/64
0B600000B7FFFF
05B000005BFFFF
SA92
0
1
1
1
0
0
128/64
0B800000B9FFFF
05C000005CFFFF
SA93
0
1
1
1
0
1
128/64
0BA00000BBFFFF
05D000005DFFFF
SA94
0
1
1
1
1
0
128/64
0BC00000BDFFFF
05E000005EFFFF
SA95
0
1
1
1
1
1
128/64
0BE00000BFFFFF
05F000005FFFFF
SA96
1
0
0
0
0
0
128/64
0C000000C1FFFF
0600000060FFFF
SA97
1
0
0
0
0
1
128/64
0C200000C3FFFF
0610000061FFFF
SA98
1
0
0
0
1
0
128/64
0C400000C5FFFF
0620000062FFFF
SA99
1
0
0
0
1
1
128/64
0C600000C7FFFF
0630000063FFFF
SA100
1
0
0
1
0
0
128/64
0C800000C9FFFF
0640000064FFFF
SA101
1
0
0
1
0
1
128/64
0CA00000CBFFFF
0650000065FFFF
SA102
1
0
0
1
1
0
128/64
0CC00000CDFFFF
0660000066FFFF
SA103
1
0
0
1
1
1
128/64
0CE00000CFFFFF
0670000067FFFF
SA104
1
0
1
0
0
0
128/64
0D000000D1FFFF
0680000068FFFF
SA105
1
0
1
0
0
1
128/64
0D200000D3FFFF
0690000069FFFF
SA106
1
0
1
0
1
0
128/64
0D400000D5FFFF
06A000006AFFFF
SA107
1
0
1
0
1
1
128/64
0D600000D7FFFF
06B000006BFFFF
SA108
1
0
1
1
0
0
128/64
0D800000D9FFFF
06C000006CFFFF
SA109
1
0
1
1
0
1
128/64
0DA00000DBFFFF
06D000006DFFFF
SA110
1
0
1
1
1
0
128/64
0DC00000DDFFFF
06E000006EFFFF
Table 4. Sector Address TableS29GL128N (Continued)
Sector
A22A16
Sector Size
(Kbytes/
Kwords)
8-Bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
44
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment to automatically match a
device to be programmed with its corresponding programming algorithm. How-
ever, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VID on ad-
dress pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table
5
.
In addition, when verifying sector protection, the sector address must appear on
the appropriate highest order address bits (see Table
2
). Table
5
shows the re-
maining address bits that are don't care. When all necessary bits have been set
as required, the programming equipment may then read the corresponding iden-
tifier code on DQ7DQ0.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table
12
and Table
13
. This
method does not require V
ID
. Refer to the Autoselect Command Sequence section
for more information.
SA111
1
0
1
1
1
1
128/64
0DE00000DFFFFF
06F000006FFFFF
SA112
1
1
0
0
0
0
128/64
0E000000E1FFFF
0700000070FFFF
SA113
1
1
0
0
0
1
128/64
0E200000E3FFFF
0710000071FFFF
SA114
1
1
0
0
1
0
128/64
0E400000E5FFFF
0720000072FFFF
SA115
1
1
0
0
1
1
128/64
0E600000E7FFFF
0730000073FFFF
SA116
1
1
0
1
0
0
128/64
0E800000E9FFFF
0740000074FFFF
SA117
1
1
0
1
0
1
128/64
0EA00000EBFFFF
0750000075FFFF
SA118
1
1
0
1
1
0
128/64
0EC00000EDFFFF
0760000076FFFF
SA119
1
1
0
1
1
1
128/64
0EE00000EFFFFF
0770000077FFFF
SA120
1
1
1
0
0
0
128/64
0F000000F1FFFF
0780000078FFFF
SA121
1
1
1
0
0
1
128/64
0F200000F3FFFF
0790000079FFFF
SA122
1
1
1
0
1
0
128/64
0F400000F5FFFF
07A000007AFFFF
SA123
1
1
1
0
1
1
128/64
0F600000F7FFFF
07B000007BFFFF
SA124
1
1
1
1
0
0
128/64
0F800000F9FFFF
07C000007CFFFF
SA125
1
1
1
1
0
1
128/64
0FA00000FBFFFF
07D000007DFFFF
SA126
1
1
1
1
1
0
128/64
0FC00000FDFFFF
07E000007EFFFF
SA127
1
1
1
1
1
1
128/64
0FE00000FFFFFF
07F000007FFFFF
Table 4. Sector Address TableS29GL128N (Continued)
Sector
A22A16
Sector Size
(Kbytes/
Kwords)
8-Bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
45
A d v a n c e I n f o r m a t i o n
Table 5. Autoselect Codes, (High Voltage Method)
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don't care.
Sector Protection
The device features several levels of sector protection, which can disable both the
program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled pro-
tection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost
sectors.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method will be used. If the customer decides to continue
Description
CE# OE#
WE
#
A22
to
A15
A14
to
A10
A9
A8
to
A7
A6
A5
to
A4
A3
to
A2
A1
A0
DQ8 to DQ15
DQ7 to DQ0
BYTE#=
V
IH
BYTE#
= V
IL
Manufacturer ID:
Spansion Product
L
L
H
X
X
V
ID
X
L
X
L
L
L
00
X
01h
De
v
i
c
e
I
D
S29GL
5
12N
Cycle 1
L
L
H
X
X
V
ID
X
L
X
L
L
H
22
X
7Eh
Cycle 2
H
H
L
22
X
23h
Cycle 3
H
H
H
22
X
01h
De
v
i
c
e
I
D
S29GL
2
56N
Cycle 1
L
L
H
X
X
V
ID
X
L
X
L
L
H
22
X
7Eh
Cycle 2
H
H
L
22
X
22h
Cycle 3
H
H
H
22
X
01h
De
v
i
c
e
I
D
S29GL
1
2
8
N
Cycle 1
L
L
H
X
X
V
ID
X
L
X
L
L
H
22
X
7Eh
Cycle 2
H
H
L
22
X
21h
Cycle 3
H
H
H
22
X
01h
Sector Group
Protection Verification
L
L
H
SA
X
V
ID
X
L
X
L
H
L
X
X
01h (protected),
00h (unprotected)
SecSi Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
L
L
H
X
X
V
ID
X
L
X
L
H
H
X
X
98h (factory locked),
18h (not factory locked)
SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector
L
L
H
X
X
V
ID
X
L
X
L
H
H
X
X
88h (factory locked),
08h (not factory locked)
46
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
using the Persistent Sector Protection method, they must set the Persistent
Sector Protection Mode Locking Bit. This will permanently set the part to op-
erate only using Persistent Sector Protection. If the customer decides to use the
password method, they must set the Password Mode Locking Bit. This will
permanently set the part to operate only using password sector protection.
It is important to remember that setting either the Persistent Sector Protec-
tion Mode Locking Bit or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to switch between the two methods
once a locking bit has been set. It is important that one mode is explicitly
selected when the device is first programmed, rather than relying on the
default mode alone. This is so that it is not possible for a system program or
virus to later set the Password Mode Locking Bit, which would cause an unex-
pected shift from the default Persistent Sector Protection Mode into the Password
Protection Mode.
The device is shipped with all sectors unprotected. The factory offers the option
of programming and protecting sectors at the factory prior to shipping the device
through the ExpressFlashTM Service. Contact your sales representative for details.
It is possible to determine whether a sector is protected or unprotected. See "Au-
toselect Command Sequence" section on page 58 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can
disable both the program and erase operations in certain sectors.
Persistent Sector Protection is a method that replaces the old 12V controlled
protection method.
Password Sector Protection is a highly sophisticated protection method that
requires a password before changes to certain sectors are permitted.
Advanced Sector Protection is available when ACC = V
HH
.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0
bits of the Lock Register are programmable by the user. Users are not allowed to
program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user
tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device
will abort the Lock Register back to the default 11 state. The programming time
of the Lock Register is same as the typical word programming time without uti-
lizing the Write Buffer of the device. During a Lock Register programming
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
Lock Register has completed to indicate programming status. All Lock Register
bits are readable to allow users to verify Lock Register statuses. Initial access
delay is required to read the Lock Register.
The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock
Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all
users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be
1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Reg-
ister. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock
Register at the same time. This allows users to lock the SecSi Sector and then set
the device either permanently into Password Protection Mode or Persistent Pro-
tection Mode and then lock the SEcSi Sector at separate instances and time
frames.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
47
A d v a n c e I n f o r m a t i o n
SecSi Sector Protection allows the user to lock the SecSi Sector area
Persistent Protection Mode Lock Bit allows the user to set the device perma-
nently to operate in the Persistent Protection Mode
Password Protection Mode Lock Bit allows the user to set the device perma-
nently to operate in the Password Protection Mode
Table 6. Lock Register
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protec-
tion method while at the same time enhancing flexibility by providing three
different sector protection states:
Dynamically Locked-The sector is protected and can be changed by a sim-
ple command
Persistently Locked-A sector is protected and cannot be changed
Unlocked-The sector is unprotected and can be changed by a simple com-
mand
In order to achieve these states, three types of "bits" are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYB bits are in the "unprotected state" if the DYB Lock
Bit of the "Lock Register" is not programmed. If the DYB Lock Bit of the "Lock
Register" is programmed, all DYB bits will power-up or hardware reset to the
"protected state". Each DYB is individually modifiable through the DYB Set Com-
mand and DYB Clear Command. When the parts are first shipped, all of the
Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits
and PPB Lock bit are defaulted to power up in the cleared state or unprotected
state - meaning the all PPB bits are changeable.
The Protection State for each sector is determined by the logical OR of the PPB
and the DYB related to that sector. For the sectors that have the PPB bits cleared,
the DYB bits control whether or not the sector is protected or unprotected. By is-
suing the DYB Set and DYB Clear command sequences, the DYB bits will be
protected or unprotected, thus placing each sector in the protected or unpro-
tected state. These are the so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to switch back and forth be-
tween the protected and un-protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does not prevent the easy re-
moval of protection when changes are needed.
The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a
more static, and difficult to change, level of protection. The PPB bits retain their
state across power cycles because they are Non-Volatile. Individual PPB bits are
set with a program command but must all be cleared as a group through an erase
command.
The PPB Lock Bit adds an additional level of protection. Once all PPB bits are pro-
grammed to the desired settings, the PPB Lock Bit may be set to the "freeze
DQ15-3
DQ2
DQ1
DQ0
Don't Care
Password Protection
Mode Lock Bit
Persistent Protection
Mode Lock Bit
SecSi Sector
Protection Bit
48
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
state". Setting the PPB Lock Bit to the "freeze state" disables all program and
erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the
PPB bits into their current state. The only way to clear the PPB Lock Bit to the
"unfreeze state" is to go through a power cycle, or hardware reset. The Software
Reset command will not clear the PPB Lock Bit to the "unfreeze state". System
boot code can determine if any changes to the PPB bits are needed e.g. to allow
new system code to be downloaded. If no changes are needed then the boot code
can set the PPB Lock Bit to disable any further changes to the PPB bits during
system operation.
The WP# write protect pin adds a final level of hardware protection. When this
pin is low it is not possible to change the contents of the WP# protected sectors.
These sectors generally hold system boot code. So, the WP# pin can prevent any
changes to the boot code that could override the choices made while setting up
sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Set command sequence
is all that is necessary. The DYB Set and DYB Clear commands for the dynamic
sectors switch the DYB bits to signify protected and unprotected, respectively. If
there is a need to change the status of the persistently locked sectors, a few more
steps are required. First, the PPB Lock Bit must be disabled to the "unfreeze
state" by either putting the device through a power-cycle, or hardware reset. The
PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock
Bit once again to the "freeze state" will lock the PPB bits, and the device operates
normally again.
Note: to achieve the best protection, it's recommended to execute the PPB Lock
Bit Set command early in the boot code, and protect the boot code by holding
WP# = V
IL
.
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB
is programmed to the protected state through the "PPB Program" command, that
sector will be protected from program or erase operations will be read-only. If a
PPB requires erasure, all of the sector PPB bits must first be erased in parallel
through the "All PPB Erase" command. The "All PPB Erase" command will prepro-
grammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike
programming where individual PPB bits are programmable. The PPB bits have the
same endurance as the flash memory.
Programming the PPB bit requires the typical word programming time without uti-
lizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing
sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the
PPB bit or erasing of all PPB bits has completed to indicate programming and
erasing status. Erasing all of the PPB bits at once requires typical sector erase
time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output
a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all
PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate
that all PPB bits have been erased. Reading the PPB Status bit requires the initial
access time of the device.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
49
A d v a n c e I n f o r m a t i o n
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the "freeze state", the PPB bits cannot be
changed. When cleared to the "unfreeze state", the PPB bits are changeable.
There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the "un-
freeze state" after power-up or hardware reset. There is no command sequence
to unlock or "unfreeze" the PPB Lock Bit.
Configuring the PPB Lock Bit to the freeze state requires approximately 100ns.
Reading the PPB Lock Status bit requires the initial access time of the device.
Table 7. Sector Protection Schemes
Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock
Bit relating to the status of the sector. In summary, if the PPB bit is set, and the
PPB Lock Bit is set, the sector is protected and the protection cannot be removed
until the next power cycle or hardware reset clears the PPB Lock Bit to "unfreeze
state". If the PPB bit is cleared, the sector can be dynamically locked or unlocked.
The DYB bit then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sec-
tor enables status polling for approximately 1 s before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 s
after which the device returns to read mode without having erased the protected
sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sec-
tor can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock
Status Read commands to the device.
The Autoselect Sector Protection Verification outputs the OR function of the DYB
bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit
is a 1, the sector is either protected by DYB or PPB or both. When the OR function
of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB
and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit
exists to guarantee that the device remain in software sector protection. Once
programmed, the Persistent Protection Mode Lock Bit prevents programming of
Protection States
Sector State
DYB Bit
PPB Bit
PPB Lock Bit
Unprotect
Unprotect
Unfreeze
Unprotected PPB and DYB are changeable
Unprotect
Unprotect
Freeze
Unprotected PPB not changeable, DYB is
changeable
Unprotect
Protect
Unfreeze
Protected PPB and DYB are changeable
Unprotect
Protect
Freeze
Protected PPB not changeable, DYB is changeable
Protect
Unprotect
Unfreeze
Protected PPB and DYB are changeable
Protect
Unprotect
Freeze
Protected PPB not changeable, DYB is changeable
Protect
Protect
Unfreeze
Protected PPB and DYB are changeable
Protect
Protect
Freeze
Protected PPB not changeable, DYB is changeable
50
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
the Password Protection Mode Lock Bit. This guarantees that a hacker could not
place the device in Password Protection Mode. The Password Protection Mode
Lock Bit resides in the "Lock Register".
Password Sector Protection
The Password Sector Protection method allows an even higher level of security
than the Persistent Sector Protection method. There are two main differences be-
tween the Persistent Sector Protection and the Password Sector Protection
methods:
When the device is first powered on, or comes out of a reset cycle, the PPB
Lock Bit is set to the locked state, or the freeze state, rather than cleared to
the unlocked state, or the unfreeze state.
The only means to clear and unfreeze the PPB Lock Bit is by writing a unique
64-bit Password to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
The password is stored in a one-time programmable (OTP) region outside of the
flash memory. Once the Password Protection Mode Lock Bit is set, the password
is permanently set with no means to read, program, or erase it. The password is
used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must
be written to the flash, along with a password. The flash device internally com-
pares the given password with the pre-programmed password. If they match, the
PPB Lock Bit is cleared to the "unfreezed state", and the PPB bits can be altered.
If they do not match, the flash device does nothing. There is a built-in 2 s delay
for each "password check" after the valid 64-bit password has been entered for
the PPB Lock Bit to be cleared to the "unfreezed state". This delay is intended to
thwart any efforts to run a program that tries all possible combinations in order
to crack the password.
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first
program the password. The factory recommends that the password be somehow
correlated to the unique Electronic Serial Number (ESN) of the particular flash de-
vice. Each ESN is different for every flash device; therefore each password should
be different for every flash device. While programming in the password region,
the customer may perform Password Read operations. Once the desired pass-
word is programmed in, the customer must then set the Password Protection
Mode Lock Bit. This operation achieves two objectives:
1. It permanently sets the device to operate using the Password Protection Mode.
It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program, and
read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Sector Protec-
tion method is desired when programming the Password Protection Mode Lock
Bit. More importantly, the user must be sure that the password is correct when
the Password Protection Mode Lock Bit is programmed. Due to the fact that read
operations are disabled, there is no means to read what the password is after-
wards. If the password is lost after programming the Password Protection Mode
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
51
A d v a n c e I n f o r m a t i o n
Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Pass-
word Protection Mode Lock Bit, once programmed, prevents reading the 64-bit
password on the DQ bus and further password programming. The Password Pro-
tection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is
programmed, the Persistent Protection Mode Lock Bit is disabled from program-
ming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Password Read commands. The password
function works in conjunction with the Password Protection Mode Lock Bit, which
when programmed, prevents the Password Read command from reading the con-
tents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the
Password Protection Mode Lock Bit after power-up reset. If the Password Protec-
tion Mode Lock Bit is also programmed after programming the Password, the
Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit
after a hardware reset (RESET# asserted) or a power-up reset. Successful exe-
cution of the Password Unlock command clears and unfreezes the PPB Lock Bit,
allowing for sector PPB bits to be modified. Without issuing the Password Unlock
command, while asserting RESET#, taking the device through a power-on reset,
or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the "freeze
state".
If the Password Protection Mode Lock Bit is not programmed, the device defaults
to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit
is cleared to the "unfreeze state" after power-up or hardware reset. The PPB Lock
Bit is set to the "freeze state" by issuing the PPB Lock Bit Set command. Once set
to the "freeze state" the only means for clearing the PPB Lock Bit to the "unfreeze
state" is by issuing a hardware or power-up reset. The Password Unlock com-
mand is ignored in Persistent Protection Mode.
Reading the PPB Lock Bit requires a 200ns access time.
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator
Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field.
The factory offers the device with the SecSi Sector either customer lockable
(standard shipping option) or factory locked (contact an AMD sales representa-
tive for ordering information). The customer-lockable version is shipped with the
SecSi Sector unprotected, allowing customers to program the sector after receiv-
ing the device. The customer-lockable version also has the SecSi Sector Indicator
Bit permanently set to a "0." The factory-locked version is always protected when
shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit
permanently set to a "1." Thus, the SecSi Sector Indicator Bit prevents customer-
lockable devices from being used to replace devices that are factory locked. Note
52
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
that the ACC function and unlock bypass modes are not available when the SecSi
Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
The system accesses the SecSi Sector through a command sequence (see "Write
Protect (WP#)"). After the system has written the Enter SecSi Sector command
sequence, it may read the SecSi Sector by using the addresses normally occupied
by the first sector (SA0). This mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until power is removed from the de-
vice. On power-up, or following a hardware reset, the device reverts to sending
commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected
At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte SecSi sector.
The system may program the SecSi Sector using the write-buffer, accelerated
and/or unlock bypass methods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be used with caution since,
once protected, there is no procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory space can be modified in
any way.
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in
Figure 2
, ex-
cept that RESET# may be at either V
IH
or V
ID
. This allows in-system protec-
tion of the SecSi Sector without raising any device pin to a high voltage. Note
that this method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm shown in
Figure 1
.
Once the SecSi Sector is programmed, locked and verified, the system must write
the Exit SecSi Sector Region command sequence to return to reading and writing
within the remainder of the array.
Factory Locked: SecSi Sector Programmed and Protected At the
Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped
from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory
Locked device has an 16-byte random ESN at addresses 000000h000007h.
Please contact your sales representative for details on ordering ESN Factory
Locked devices.
Customers may opt to have their code programmed by the factory through the
ExpressFlash service (Express Flash Factory Locked). The devices are then
shipped from the factory with the SecSi Sector permanently locked. Contact your
sales representative for details on using the ExpressFlash service.
SecSi Sector Address Range
Customer Lockable
ESN Factory Locked
ExpressFlash
Factory Locked
000000h000007h
Determined by customer
ESN
ESN or determined by
customer
000008h00007Fh
Unavailable
Determined by customer
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
53
A d v a n c e I n f o r m a t i o n
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using V
ID
. Write Protect is one of two functions provided
by the WP#/ACC input.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected using the method described in"Ad-
vanced Sector Protection" section on page 46. Note that if WP#/ACC is at V
IL
when the device is in the standby mode, the maximum input load current is in-
creased. See the table in "DC Characteristics" section on page 86.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or un-
protected using the method described in "Sector Group Protection and
Unprotection". Note that WP# has an internal pullup; when uncon-
nected, WP# is at V
IH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Tables
16
and
17
for
command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V
CC
power-up and power-down
transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# =
V
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
54
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 811. The system must write the reset
command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alter-
natively, contact your sales representative for copies of these documents.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
55
A d v a n c e I n f o r m a t i o n
Table 8. CFI Query Identification String
Table 9. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string "QRY"
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Addresses
(x16)
Addresses
(x8)
Data
Description
1Bh
36h
0027h
V
CC
Min. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Ch
38h
0036h
V
CC
Max. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Dh
3Ah
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
3Ch
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
3Eh
0007h
Typical timeout per single byte/word write 2
N
s
20h
40h
0007h
Typical timeout for Min. size buffer write 2
N
s (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2
N
ms
22h
44h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
46h
0001h
Max. timeout for byte/word write 2
N
times typical
24h
48h
0005h
Max. timeout for buffer write 2
N
times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2
N
times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
56
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Table 10. Device Geometry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
27h
4Eh
001Ah
0019h
0018h
Device Size = 2
N
byte
1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
58h
0001h
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
57
A d v a n c e I n f o r m a t i o n
Table 11. Primary Vendor-Specific Extended Query
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table
12
and Table
13
define the valid register
command sequences. Writing incorrect address and data values or writing them
in the improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Addresses
(x16)
Addresses
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string "PRI"
43h
86h
0031h
Major version number, ASCII
44h
88h
0033h
Minor version number, ASCII
45h
8Ah
0010h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0008h
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
00B5h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh
9Ch
00C5h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh
9Eh
00xxh
WP# Protection
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors
top WP# protect
50h
A0h
0001h
Program Suspend
00h = Not Supported, 01h = Supported
58
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any non-
erase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same ex-
ception. See the Erase Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations sec-
tion for more information. The Read-Only Operations"AC Characteristics"
section on page 88 provides the read parameters, and Figure 11 shows the timing
diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don't cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command
returns the device to the read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the sys-
tem must write the Write-to-Buffer-Abort Reset command sequence to reset the
device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
Table
12
and Table
13
show the address and data requirements. This method is
an alternative to that shown in Table
5
, which is intended for PROM programmers
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
59
A d v a n c e I n f o r m a t i o n
and requires V
ID
on address pin A9. The autoselect command sequence may be
written to an address that is either in the read or erase-suspend-read mode. The
autoselect command may not be written while the device is actively programming
or erasing.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address any
number of times without initiating another autoselect command sequence:
A read cycle at address XX00h returns the manufacturer code.
Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code.
A read cycle to an address containing a sector address (SA), and the address
02h on A7A0 in word mode returns 01h if the sector is protected, or 00h if
it is unprotected.
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the device was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-word/16-
byte random Electronic Serial Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi Sector command sequence.
The device continues to access the SecSi Sector region until the system issues
the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal operation. Table
12
and Table
13
show the address and data requirements for both command sequences. See also
"SecSi (Secured Silicon) Sector Flash Memory Region" for further information.
Note that the ACC function and unlock bypass modes are not available when the
SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table
12
and Table
13
show the
address and data requirements for the word program command sequence.
When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Op-
eration Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that the SecSi Sector, autoselect, and CFI functions are
unavailable when a program operation is in progress. Note that a hard-
ware reset immediately terminates the program operation. The program
command sequence should be reinitiated once the device has returned to the
read mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without in-
tervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
60
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
compatibility with existing Flash driver software and for occassional writng of in-
dividual words. Use of Write Buffer Programming is strongly recommended for
general programming use when more than a few words are to be programmed.
The effective word programming time using Write Buffer Programming is much
shorter than the single word programming time. Any word cannot be pro-
grammed from "0" back to a "1." Attempting to do so may cause the device
to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation
was successful. However, a succeeding read will show that the data is still "0."
Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table
12
and Table
13
show the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table
12
and Table
13
).
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the
Sector Address in which programming will occur. The fourth cycle writes the sec-
tor address and the number of word locations, minus one, to be programmed. For
example, if the system will program 6 unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses
will be loaded with data and therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot exceed the size of the
write buffer or the operation will abort.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits A
MAX
A
4
. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer loca-
tions may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded
into the write buffer. (This means Write Buffer Programming cannot be performed
across multiple write-buffer pages. This also means that Write Buffer Program-
ming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation will
abort.)
May 13, 2004 27631A4
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61
A d v a n c e I n f o r m a t i o n
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter will be decremented for every data load operation. The host
system must therefore account for loading a write-buffer location more than
once. The counter decrements for each data load operation, not for each unique
write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations have been loaded, the system
must then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming oper-
ation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5,
and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one se-
lected by the Starting Address during the write buffer data loading stage of
the operation.
Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset com-
mand sequence must be written to reset the device for the next operation. Note
that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required
when using Write-Buffer-Programming features in Unlock Bypass mode.
Write buffer programming is allowed in any sequence. Note that the SecSi sector,
autoselect, and CFI functions are unavailable when a program operation is in
progress. This flash device is capable of handling multiple write buffer program-
ming operations on the same write buffer address range without intervening
erases. For applications requiring incremental bit programming, a modified pro-
gramming method is required, please contact your local Spansion representative.
Any bit in a write buffer address range cannot be programmed from "0"
back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or
cause the DQ7 and DQ6 status bits to indicate the operation was successful. How-
ever, a succeeding read will show that the data is still "0." Only erase operations
can convert a "0" to a "1."
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V
HH
on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
62
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
be at V
HH
for operations other than accelerated programming, or device damage
may result. WP# has an internal pullup; when unconnected, WP# is at V
IH
.
Figure 3 illustrates the algorithm for the program operation. Refer to the Erase
and Program Operations"AC Characteristics" section on page 88 section for pa-
rameters, and Figure 14 for timing diagrams.
May 13, 2004 27631A4
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63
A d v a n c e I n f o r m a t i o n
Figure 1. Write Buffer Programming Operation
Write "Write to Buffer"
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Write program buffer to
flash sector address
Write first address/data
Write to a different
sector address
FAIL or ABORT
PASS
Read DQ15 - DQ0 at
Last Loaded Address
Read DQ15 - DQ0 with
address = Last Loaded
Address
Write next address/data pair
WC = WC - 1
WC = 0 ?
Part of "Write to Buffer"
Command Sequence
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Abort Write to
Buffer Operation?
DQ7 = Data?
DQ7 = Data?
DQ5 = 1?
DQ1 = 1?
Write to buffer ABORTED.
Must write "Write-to-buffer
Abort Reset" command
sequence to return
to read mode.
(Note 1)
(Note 2)
(Note 3)
Notes:
1. When Sector Address is specified, any
address in the selected sector is acceptable.
However, when loading Write-Buffer
address locations with data, all addresses
must fall within the selected Write-Buffer
Page.
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached
because DQ5= "1", then the device FAILED.
If this flowchart location was reached
because DQ1= "1", then the Write to Buffer
operation was ABORTED. In either case, the
proper reset command must be written
before the device can begin another
operation. If DQ1=1, write the Write-
Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset
command.
4. See Tables
16
and
17
for command
sequences required for write buffer
programming.
64
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Figure 2. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the program operation within 15
s maximum (5s typical) and updates the status bits. Addresses are not re-
quired when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array
data from any non-suspended sector. The Program Suspend command may also
be issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the SecSi Sector area (One-time Program
area), then user must use the proper command sequences to enter and exit this
region. Note that the SecSi Sector autoselect, and CFI functions are unavailable
when program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to the
Program Suspend mode, and is ready for another valid operation. See Autoselect
Command Sequence for more information.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table
12
and Table
13
for program com-
mand sequence.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
65
A d v a n c e I n f o r m a t i o n
After the Program Resume command is written, the device reverts to program-
ming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Op-
eration Status for more information.
The system must write the Program Resume command (address bits are don't
care) to exit the Program Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device has resume programming.
Figure 3. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table
12
and Table
13
show the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation
Status section for information on these status bits.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Done
reading?
No
Yes
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Write address/data
XXXh/B0h
Wait 15
s
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Any commands written during the chip erase operation are ignored, including
erase suspend commands. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once the device has returned to reading array data, to en-
sure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable when an erase op-
eration in is progress. Refer to the Erase and Program Operations table in the
AC Characteristics section for parameters, and Figure 16 section for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12
and Table
13
shows
the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 s, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an erase operation
in is progress. The system must rewrite the command sequence and any addi-
tional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and
Program Operations table in the AC Characteristics section for parameters, and
Figure 16 section for timing diagrams.
May 13, 2004 27631A4
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67
A d v a n c e I n f o r m a t i o n
Figure 4. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, includ-
ing the 50 s time-out period during the sector erase command sequence. The
Erase Suspend command is ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 s
(maximum of 20 s) to suspend the erase
operation. However, when the Erase Suspend command is written during the sec-
tor erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device "erase suspends" all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the pro-
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table
12
and Table
13
for program command
sequence.
2. See the section on DQ3 for information on the sector
erase timer.
68
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
gram operation using the DQ7 or DQ6 status bits, just as in the standard word
program operation. Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. Refer to the Autoselect Mode section and "Autoselect Command
Sequence" section on page 58 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. The address of the erase-suspended sector is required when writing
this command. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has resumed erasing. It is
important to allow an intervalof at least 5 ns between Erase Resume and Erase
Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the SecSi
Sector Protection Bit, Persistent Protection Mode Lock Bit, and Password Protec-
tion Mode Lock Bit. The Lock Register bits are all readable after an initial access
delay.
The Lock Register Command Set Entry command sequence must be issued
prior to any of the following commands listed, to enable proper command
execution.
Note that issuing the Lock Register Command Set Entry command disables
reads and writes for the flash memory.
Lock Register Program Command
Lock Register Read Command
The Lock Register Command Set Exit command must be issued after the ex-
ecution of the commands to reset the device to read mode. Otherwise the device
will hang. If this happens, the flash device must be reset. Please refer to RESET#
for more information. It is important to note that the device will be in either Per-
sistent Protection mode or Password Protection mode depending on the mode
selected prior to the device hang.
For either the SecSi Sector to be locked, or the device to be permanently set to
the Persistent Protection Mode or the Password Protection Mode, the associated
Lock Register bits must be programmed. Note that the Persistent Protection
Mode Lock Bit and Password Protection Mode Lock Bit can never be pro-
grammed together at the same time. If so, the Lock Register Program
operation will abort.
The Lock Register Command Set Exit command must be initiated to re-
enable reads and writes to the main memory.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit
password, verify the programming of the 64-bit password, and then later unlock
the device by issuing the valid 64-bit password.
The Password Protection Command Set Entry command sequence must be
issued prior to any of the commands listed following to enable proper command
execution.
Note that issuing the Password Protection Command Set Entry command
disabled reads and writes the main memory.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
69
A d v a n c e I n f o r m a t i o n
Password Program Command
Password Read Command
Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the pass-
word. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the "Lock Register" must be programmed in order to prevent verification. The
Password Program command is only capable of programming "0"s. Programming
a "1" after a cell is programmed as a "0" results in a time-out by the Embedded
Program Algorithm
TM
with the cell remaining as a "0". The password is all F's when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the "Lock Register"
is not programmed. If the Password Protection Mode Lock Bit in the "Lock Regis-
ter" is programmed and the user attempts to read the Password, the device will
always drive all F's onto the DQ databus.
The lower two address bits (A1A0) for word mode and (A1A-1) for by byte
mode are valid during the Password Read, Password Program, and Password Un-
lock commands. Writing a "1" to any other address bits (A
MAX
-A2) will
abort the Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the "unfreeze
state" so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock com-
mand sequence will take at least 2 s to process each time to prevent a
hacker from running through the all 64-bit combinations in an attempt
to correctly match the password. If another password unlock is issued
before the 64-bit password check execution window is completed, the
command will be ignored. If the wrong address or data is given during
password unlock command cycle, the device may enter the write-to-
buffer abort state. In order to exit the write-to-abort state, the write-to-
buffer-abort-reset command must be given. Otherwise the device will
hang.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit to the
"unfreeze state". The password is 64 bits long. A1 and A0 are used for matching
in word mode and A1, A0, A-1 in byte mode. Writing the Password Unlock com-
mand does not need to be address order specific. An example sequence is
starting with the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10,
and A1-A0=11 if the device is configured to operate in word mode.
Approximately 2 s is required for unlocking the device after the valid
64-bit password is given to the device. It is the responsibility of the mi-
croprocessor to keep track of the entering the portions of the 64-bit
password with the Password Unlock command, the order, and when to
read the PPB Lock bit to confirm successful password unlock. In order to
re-lock the device into the Password Protection Mode, the PPB Lock Bit Set com-
mand can be re-issued.
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
The Password Protection Command Set Exit command must be issued after
the execution of the commands listed previously to reset the device to read
mode. Otherwise the device will hang.
Note that issuing the Password Protection Command Set Exit command re-
enables reads and writes for the main memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the
Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits
(PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits).
The Non-Volatile Sector Protection Command Set Entry command se-
quence must be issued prior to any of the commands listed following to enable
proper command execution.
Note that issuing the Non-Volatile Sector Protection Command Set Entry
command disables reads and writes for the main memory.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB bit. Each PPB
bit is individually programmed (but is bulk erased with the other PPB bits). The
specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22-
A16 for S29GL128N) is written at the same time as the program command. If the
PPB Lock Bit is set to the "freeze state", the PPB Program command will not exe-
cute and the command will time-out without programming the PPB bit.
All PPB Erase Command
The All PPB Erase command is used to erase all PPB bits in bulk. There is no
means for individually erasing a specific PPB bit. Unlike the PPB program, no spe-
cific sector address is required. However, when the All PPB Erase command is
issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to
"freeze state", the ALL PPB Erase command will not execute and the command
will time-out without erasing the PPB bits.
The device will preprogram all PPB bits prior to erasing when issuing the All PPB
Erase command. Also note that the total number of PPB program/erase cycles has
the same endurance as the flash memory array.
PPB Status Read Command
The programming state of the PPB for a given sector can be verified by writing a
PPB Status Read Command to the device. This requires an initial access time
latency.
The Non-Volatile Sector Protection Command Set Exit command must be
issued after the execution of the commands listed previously to reset the device
to read mode.
Note that issuing the Non-Volatile Sector Protection Command Set Exit
command re-enables reads and writes for the main memory.
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set
the PPB Lock Bit and reading the logic state of the PPB Lock Bit.
The Global Volatile Sector Protection Freeze Command Set Entry com-
mand sequence must be issued prior to any of the commands listed following to
enable proper command execution.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
71
A d v a n c e I n f o r m a t i o n
Reads and writes from the main memory are allowed.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock Bit to the "freeze state"
if it is cleared either at reset or if the Password Unlock command was successfully
executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set
to the "freeze state", it cannot be cleared unless the device is taken through a
power-on clear (for Persistent Protection Mode) or the Password Unlock command
is executed (for Password Protection Mode). If the Password Protection Mode Lock
Bit is programmed, the PPB Lock Bit status is reflected as set to the "freeze state",
even after a power-on reset cycle.
PPB Lock Bit Status Read Command
The programming state of the PPB Lock Bit can be verified by executing a PPB
Lock Bit Status Read command to the device.
The Global Volatile Sector Protection Freeze Command Set Exit command
must be issued after the execution of the commands listed previously to reset the
device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic
Protection Bit (DYB) to the "protected state", clear the Dynamic Protection Bit
(DYB) to the "unprotected state", and read the logic state of the Dynamic Protec-
tion Bit (DYB).
The Volatile Sector Protection Command Set Entry command sequence
must be issued prior to any of the commands listed following to enable proper
command execution.
Note that issuing the Volatile Sector Protection Command Set Entry com-
mand disables reads for the bank selected with the command. Reads and
Writes for other banks excluding that bank are allowed.
DYB Set Command
DYB Clear Command
The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for
a given sector. The high order address bits are issued at the same time as the
code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the
data write cycle. The DYB bits are modifiable at any time, regardless of the state
of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the "unprotected state"
at power-up or hardware reset.
--DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing
a DYB Status Read command to the device. This requires an initial access delay.
The Volatile Sector Protection Command Set Exit command must be issued
after the execution of the commands listed previously to reset the device to read
mode.
Note that issuing the Volatile Sector Protection Command Set Exit com-
mand re-enables reads and writes to the main memory.
SecSi Sector Entry Command
The SecSi Sector Entry command allows the following commands to be executed
Read from SecSi Sector
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Program to SecSi Sector
Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command
has to be issued to exit SecSi Sector Mode.
SecSi Sector Exit Command
The SecSi Sector Exit command may be issued to exit the SecSi Sector Mode.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
73
A d v a n c e I n f o r m a t i o n
Command Definitions
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16
Command (Notes)
Cycle
s
Bus Cycles (Notes 25)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr
Data Addr Data Addr Data
Addr
Data
Addr
Data
Read (6)
1
RA
RD
Reset (7)
1
XXX
F0
Aut
o
s
e
lec
t
(
N
o
t
e
8)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID
4
555
AA
2AA
55
555
90
X01
227E
X0E
Note
17
X0F
Note
17
Sector Protect Verify
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Secure Device Verify (9)
4
555
AA
2AA
55
555
90
X03
Note
10
CFI Query (11)
1
55
98
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer
3
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
1
SA
29
Write-to-Buffer-Abort Reset (16)
3
555
AA
2AA
55
555
F0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (12)
2
XXX
A0
PA
PD
Unlock Bypass Sector Erase (12)
2
XXX
80
SA
30
Unlock Bypass Chip Erase (12)
2
XXX
80
XXX
10
Unlock Bypass Reset (13)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend/Program Suspend (14)
1
XXX
B0
Erase Resume/Program Resume (15)
1
XXX
30
Sector Command Definitions
Se
c
S
i
TM
SEc
t
o
r
SecSi Sector Entry
3
555
AA
2AA
55
555
88
SecSi Sector Exit (18)
4
555
AA
2AA
55
555
90
XX
00
Lock Register Command Set Definitions
Loc
k
R
e
g
i
st
e
r
Lock Register Command Set Entry
3
555
AA
2AA
55
555
40
Lock Register Bits Program (22)
2
XXX
A0
XXX
Data
Lock Register Bits Read (22)
1
00
Data
Lock Register Command Set Exit (18, 23)
2
XXX
90
XXX
00
Password Protection Command Set Definitions
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S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Legend:
X = Don't care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A
max
A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
P
a
ssw
or
d
Password Protection Command Set Entry
3
555
AA
2AA
55
555
60
Password Program (20)
2
XXX
A0
PWA
x
PWD
x
Password Read (19)
4
XXX
PWD
0
01
PWD
1
02
PWD
2
03
PWD
3
Password Unlock (19)
7
00
25
00
03
00
PWD
0
01
PWD
1
02
PWD
2
03
PWD
3
00
29
Password Protection Command Set Exit (18,
23)
2
XXX
90
XXX
00
Non-Volatile Sector Protection Command Set Definitions
PPB
Nonvolatile Sector Protection Command Set
Entry
3
555
AA
2AA
55
555
C0
PPB Program (24, 25)
2
XXX
A0
SA
00
All PPB Erase
2
XXX
80
00
30
PPB Status Read (25)
1
SA
RD
(0)
Non-Volatile Sector Protection Command Set
Exit (18)
2
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
PPB L
o
ck
Bit
Global Non-Volatile Sector Protection Freeze
Command Set Entry
3
555
AA
2AA
55
555
50
PPB Lock Bit Set (25)
2
XXX
A0
XXX
00
PPB Lock Status Read (25)
1
XXX
RD
(0)
Global Non-Volatile Sector Protection Freeze
Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
DY
B
Volatile Sector Protection Command Set Entry
3
555
AA
2AA
55
555
E0
DYB Set (24, 25)
2
XXX
A0
SA
00
DYB Clear (25)
2
XXX
A0
SA
01
DYB Status Read (25)
1
SA
RD
(0)
Volatile Sector Protection Command Set Exit
(18)
2
XXX
90
XXX
00
Command (Notes)
Cy
cl
e
s
Bus Cycles (Notes 25)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr
Data Addr Data Addr Data
Addr
Data
Addr
Data
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
75
A d v a n c e I n f o r m a t i o n
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWD
x
= Password word0, word1, word2, and word3.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See
Table 1
for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits A
MAX
:A16 are don't cares for unlock and command cycles, unless SA or PA required. (A
MAX
is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is "1" for a serialized and protected OTP region and "0" for an unserialized and unprotected
SecSiTMSector region. See "SecSiTMSector Flash Memory Region" for more information. For S29GLVxxxNH: XX18h/18h = Not
Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory
Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command.
13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
17. S29GL512NH/L = 2223h/23h, 220h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/
01h.
18. The Exit command returns the device to reading the array.
19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
20. For PWDx, only one portion of the password can be programmed per each "A0" command.
21. The All PPB Erase command embeds programming of all PPB bits before erasure.
22. All Lock Register bits are one-time programmable. Note that the program state = "0" and the erase state = "1". Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that
are reserved for future use will default to "1's". The Lock Register is shipped out as "FFFF's" before Lock Register Bit program
execution.
23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device will hang.
24. If ACC = V
HH
, sector protection will match when ACC = V
IH
25. Protected State = "00h", Unprotected State = "01h".
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A d v a n c e I n f o r m a t i o n
Table 13. S29GL512N, S29GL256N, S29GL128N Command Definitions, x8
Command (Notes)
Cycle
s
Bus Cycles (Notes 25)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Addr
Data Addr Data
Read (6)
1
RA
RD
Reset (7)
1
XXX
F0
Au
t
o
s
e
l
e
c
t
Manufacturer ID
4
AAA
AA
555
55
AAA
90
X00
01
Device ID
4
AAA
AA
555
55
AAA
90
X02
XX7E
X1C
Note
17
X1E
Note
17
Sector Protect Verify
4
AAA
AA
555
55
AAA
90
(SA)
X04
00
01
Secure Device Verify (9)
4
AAA
AA
555
55
AAA
90
X06
Note
10
CFI Query (11)
1
AA
98
Write to Buffer
3
AAA
AA
555
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash (confirm)
1
SA
29
Write-to-Buffer-Abort Reset (16)
3
AAA
AA
PA
55
555
F0
Chip Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
Sector Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
Erase Suspend/Program Suspend (14)
1
XXX
B0
Erase Resume/Program Resume (15)
1
XXX
30
SecSi Sector Command Definitions
Se
c
S
i
TM
SEc
t
o
r
SecSi Sector Entry
3
AAA
AA
555
55
AAA
88
SecSi Sector Exit (18)
4
AAA
AA
555
55
AAA
90
XX
00
Lock Register Command Set Definitions
Loc
k
R
e
gi
st
e
r
Lock Register Command Set Entry
3
AAA
AA
555
55
AAA
40
Lock Register Bits Program (22)
2
XXX
A0
XXX
Data
Lock Register Bits Read (22)
1
00
Data
Lock Register Command Set Exit (18, 23)
2
XXX
90
XXX
00
Password Protection Command Set Definitions
Pa
s
s
w
o
r
d
Password Protection Command Set Entry
3
AAA
AA
555
55
AAA
60
Password Program (20)
2
XXX
A0
PWA
x
PWD
x
Password Read (19)
8
00
PWD
0
01
PWD
1
02
PWD
2
03
PWD
3
04
PWD
4
05
PWD
5
06
PWD
6
07
PWD
7
Password Unlock (19)
11
00
25
00
03
00
PWD
0
01
PWD
1
02
PWD
2
03
PWD
3
04
PWD
4
05
PWD
5
06
PWD
6
07
PWD
7
00
29
Password Protection Command Set Exit
(18, 23)
2
XXX
90
XXX
00
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S29GLxxxN MirrorBitTM Flash Family
77
A d v a n c e I n f o r m a t i o n
Legend:
X = Don't care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A
max
A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
PWD = Password
PWD
x
= Password word0, word1, word2, word3. word 4, word 5, word 6, and word 7.
DATA = Lock Register Contents: PD(0) = SecSi Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =
Password Protection Mode Lock Bit.
Notes:
1. See
Table 1
for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write
cycles.
Non-Volatile Sector Protection Command Set Definitions
PPB
Nonvolatile Sector Protection Command
Set Entry
3
AAA
AA
55
55
AAA
C0
PPB Program (24, 25)
2
XXX
A0
SA
00
All PPB Erase
2
XXX
80
00
30
PPB Status Read (25)
1
SA
RD
(0)
Non-Volatile Sector Protection Command
Set Exit (18)
2
XXX
90
XXX
00
Global Non-Volatile Sector Protection Freeze Command Set Definitions
PP
B L
o
c
k
Bit
Global Non-Volatile Sector Protection
Freeze Command Set Entry
3
AAA
AA
555
55
AAA
50
PPB Lock Bit Set (25)
2
XXX
A0
XXX
00
PPB Lock Status Read (25)
1
XXX
RD
(0)
Global Non-Volatile Sector Protection
Freeze Command Set Exit (18)
2
XXX
90
XXX
00
Volatile Sector Protection Command Set Definitions
DY
B
Volatile Sector Protection Command Set
Entry
3
AAA
AA
555
55
AAA
E0
DYB Set (24, 25)
2
XXX
A0
SA
00
DYB Clear (25)
2
XXX
A0
SA
01
DYB Status Read (25)
1
SA
RD
(0)
Volatile Sector Protection Command Set
Exit (18)
2
XXX
90
XXX
00
Command (Notes)
Cy
cl
e
s
Bus Cycles (Notes 25)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Addr
Data Addr Data
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4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles.
5. Address bits A
MAX
:A16 are don't cares for unlock and command cycles, unless SA or PA required. (A
MAX
is the Highest
Address pin.).
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here.
10. The data value for DQ7 is "1" for a serialized and protected OTP region and "0" for an unserialized and unprotected
SecSiTM Sector region. See "SecSiTM Sector Flash Memory Region" for more information. For S29GLxxxNH.: XX18h/18h = Not
Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory
Locked.
11. Command is valid when device is ready to read array data or when device is in autoselect mode.
12. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
13. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes.
14. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the
full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode.
15. S29GL512NH/L = 2223h/23h, 220h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/
01h.
16. The Exit command returns the device to reading the array.
17. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
18. For PWDx, only one portion of the password can be programmed per each "A0" command.
19. The All PPB Erase command embeds programming of all PPB bits before erasure.
20. All Lock Register bits are one-time programmable. Note that the program state = "0" and the erase state = "1". Also note
that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the
same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that
are reserved for future use will default to "1's". The Lock Register is shipped out as "FFFF's" before Lock Register Bit program
execution.
21. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise
the device will hang.
22. If ACC = V
HH
, sector protection will match when ACC = V
IH
Protected State = "00h", Unprotected State = "01h".
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 19 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.
Note that all Write Operation Status DQ bits are valid only after 4 s delay.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device is
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
May 13, 2004 27631A4
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79
A d v a n c e I n f o r m a t i o n
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 s, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must
provide an address within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 s, then the
device returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0DQ6 while Output Enable (OE#) is as-
serted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data outputs on DQ0DQ6 may
be still invalid. Valid data on DQ0DQ7 will appear on successive read cycles.
Table
14
shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#
Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#
Polling timing diagram.
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S29GLxxxN MirrorBitTM Flash Family
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A d v a n c e I n f o r m a t i o n
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V
CC
.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or in the erase-suspend-read
mode. Table
14
shows the outputs for RY/BY#.
DQ7 = Data?
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ15DQ0
Addr = VA
Read DQ15DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = "1" because
DQ7 may change simultaneously with DQ5.
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A d v a n c e I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 s, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 s after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table
14
shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit tim-
ing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical
form. See also the subsection on DQ2: Toggle Bit II.
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A d v a n c e I n f o r m a t i o n
Figure 6. Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7DQ0
Toggle Bit
= Toggle?
Read DQ7DQ0
Twice
Read DQ7DQ0
N o t e :
The system should recheck the toggle bit even if
DQ5 = "1" because the toggle bit may stop toggling
as DQ5 changes to "1." See the subsections on DQ6
and DQ2 for more information.
May 13, 2004 27631A4
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83
A d v a n c e I n f o r m a t i o n
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table
14
to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2:
Toggle Bit II" explains the algorithm. See also the RY/BY#: Ready/Busy# subsec-
tion. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the
differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5
produces a "1," indicating that the program or erase cycle was not successfully
completed.
The device may output a "1" on DQ5 if the system tries to program a "1" to a
location that was previously programmed to "0." Only an erase operation can
change a "0" back to a "1." Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a "1."
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
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When the time-out period is complete, DQ3 switches from a "0" to a "1." If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 s, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is "0," the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table
14
shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-Abort-
Reset command sequence to return the device to reading array data. See Write
Buffer section for more details.
Table 14. Write Operation Status
Notes:
1. DQ5 switches to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to `1' when the device has aborted the write-to-buffer operation
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
RY/
BY#
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Program
Suspend
Mode
Program-
Suspend
Read
Program-Suspended
Sector
Invalid (not allowed)
1
Non-Program
Suspended Sector
Data
1
Erase
Suspend
Mode
Erase-
Suspend
Read
Erase-Suspended
Sector
1
No toggle
0
N/A
Toggle
N/A
1
Non-Erase
Suspended Sector
Data
1
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
0
Write-to-
Buffer
Busy (Note 3)
DQ7#
Toggle
0
N/A
N/A
0
0
Abort (Note 4)
DQ7#
Toggle
0
N/A
N/A
1
0
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85
A d v a n c e I n f o r m a t i o n
ABSOLUTE MAXIMUM RATINGS
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . 65C to +150C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . 65C to +125C
Voltage with Respect to Ground:
V
CC
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
V
IO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
A9, OE#, ACC and RESET# (Note 2) . . . . . . . . . . . . . 0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.5 V
Output Short Circuit Current (Note 3)200 mA
Notes:
1. Minimum DC voltage on input or I/Os is 0.5 V. During voltage transitions, inputs
or I/Os may overshoot V
SS
to 2.0 V for periods of up to 20 ns. See
Figure 7
.
Maximum DC voltage on input or I/Os is V
CC
+ 0.5 V. During voltage transitions,
input or I/O pins may overshoot to V
CC
+ 2.0 V for periods up to 20 ns. See
Figure
8
.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is 0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot V
SS
to 2.0 V for
periods of up to 20 ns. See
Figure 7
. Maximum DC input voltage on pin A9, OE#,
ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20
ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
Operating Ranges
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C
Supply Voltages
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
V
IO
(Note 2) . . . . . . . . . . . . . . . . . . . +1.65 V to +1.95 V or +2.7 to + 3.6 V
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. See
Ordering Information (256 Mb)
section for valid V
CC
/V
IO
range combinations. The I/Os will not operate at 3 V
when V
IO
=1.8 V.
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
86
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Notes:
1. The I
CC
current listed is typically less than TBD mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor t
ACC
+ 30 ns.
5. V
IO
= 1.651.95 V or 2.73.6 V
6. V
CC
= 3 V and V
IO
= 3V or 1.8V. When V
IO
is at 1.8V, I/O pins cannot operate at 3V.
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current (1)
V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
1.0
A
I
LIT
A9 Input Load Current
V
CC
= V
CC max
; A9 = 12.5 V
35
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC max
1.0
A
I
IO1
V
IO
Active Read Current
(Switching Current)
V
IO
= 1.8 V, CE# = V
IL
, OE# = V
IL
, WE# = V
IL
,
f =
5 MHz
5
10
A
I
IO2
V
IO
Non-Active Output
CE# = V
IL,
OE# = V
IH
0.2
10
mA
I
CC1
V
CC
Active Read Current (1)
CE# = V
IL,
OE# = V
IH
, V
CC
= V
CCmax
,
f = 5 MHz, Byte Mode
25
30
mA
CE# = V
IL,
OE# = V
IH
, V
CC
= V
CCmax
,
f = 5 MHz, Word Mode
25
30
I
CC2
V
CC
Initial Page Read Current (1)
CE# = V
IL,
OE# = V
IH,
V
CC
= V
CCmax
50
60
mA
I
CC3
V
CC
Intra-Page Read Current (1)
CE# = V
IL,
OE# = V
IH,
V
CC
= V
CCmax
10
20
mA
I
CC4
V
CC
Active Erase/Program Current (2, 3) CE# = V
IL,
OE# = V
IH,
V
CC
= V
CCmax
50
70
mA
I
CC5
V
CC
Standby Current
CE#, RESET# = V
SS
0.3 V, OE# = V
IH,
V
CC
= V
CCmax
V
IL
= V
SS
+ 0.3 V/-0.1V,
1
5
A
I
CC6
V
CC
Reset Current
V
CC
= V
CCmax;
V
IL
= V
SS
+ 0.3 V/-0.1V,
RESET# = V
SS
0.3 V
1
5
A
I
CC7
Automatic Sleep Mode (4)
V
CC
= V
CCmax
V
IH
= V
CC
0.3 V,
V
IL
= V
SS
+ 0.3 V/-0.1V,
WP#/ACC = V
IH
1
5
A
I
ACC
ACC Accelerated Program Current
CE# = V
IL,
OE# = V
IH,
V
CC
= V
CCmax,
WP#/ACC = V
IH
WP#/ACC
pin
10
20
mA
V
CC
pin
30
60
V
IL
Input Low Voltage (5)
0.1
0.3 x V
IO
V
V
IH
Input High Voltage (5)
0.7 x V
IO
V
IO
+ 0.3
V
V
HH
Voltage for ACC Erase/Program
Acceleration
V
CC
= 2.7 3.6 V
11.5
12.5
V
V
ID
Voltage for Autoselect and Temporary
Sector Unprotect
V
CC
= 2.7 3.6 V
11.5
12.5
V
V
OL
Output Low Voltage (5)
I
OL
= 100 A
0.15 x
V
IO
V
V
OH
Output High Voltage (5)
I
OH
= 100 A
0.85 x V
IO
V
V
LKO
Low V
CC
Lock-Out Voltage (3)
2.3
2.5
V
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
87
A d v a n c e I n f o r m a t i o n
Test Conditions
Note: If V
IO
< V
CC
, the reference level is 0.5 V
IO
.
Key to Switching Waveforms
Note: Diodes are IN3064 or equivalent
Table 15. Test Specifications
2.7 k
CL
6.2 k
3.3 V
Device
Under
Test
Note:
Diodes are IN3064 or equivalent.
Figure 9. Test Setup
Test Condition
All Speeds
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0V
IO
V
Input timing measurement
reference levels (See Note)
0.5V
IO
V
Output timing measurement
reference levels
0.5 V
IO
V
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
V
IO
0.0 V
0.5 V
IO
0.5 V
IO
V
Output
Measurement Level
Input
Note: If V
IO
< V
CC
, the input measurement reference level is 0.5 V
IO
.
Figure 10. Input Waveforms and
Measurement Levels
88
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only OperationsS29GL512N Only
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and Table
15
for test specifications.
5. Unless otherwise indicated, AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= V
CC
= 3 V. AC
specifications for 100 ns and 110 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Description
Test Setup
Speed Options
JEDEC Std.
90 100 100 110 Unit
t
AVAV
t
RC
Read Cycle Time
V
IO
= V
CC
= 3 V
Min
90
100
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
100 110
V
IO
= 1.8 V, V
CC
= 3 V
100 110
ns
t
AVQV
t
ACC
Address to Output Delay
(Note 2)
V
IO
= V
CC
= 3 V
Max
90
100
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
100 110
V
IO
= 1.8 V, V
CC
= 3 V
100 110
ns
t
ELQV
t
CE
Chip Enable to Output Delay
(Note 3)
V
IO
= V
CC
= 3 V
Max
90
105
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
100 110
V
IO
= 1.8 V, V
CC
= 3 V
100 110
ns
t
PAC
C
Page Access Time
Max 25
25
35
35
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max 25
25
35
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
20
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
20
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
CEH
Chip Enable Hold Time
Read
Min
35
ns
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
89
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only OperationsS29GL256N Only
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and Table
15
for test specifications.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V. AC
specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Description
Test Setup
Speed Options
JEDEC Std.
80 90 90 100 Unit
t
AVAV
t
RC
Read Cycle Time
V
IO
= V
CC
= 3 V
Min
80 90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
AVQV
t
ACC
Address to Output Delay (Note 2)
V
IO
= V
CC
= 3 V
Max
80 90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
ELQV
t
CE
Chip Enable to Output Delay
(Note 3)
V
IO
= V
CC
= 3 V
Max
80 90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
PAC
C
Page Access Time
Max 25 25
35
35
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max 25 25
35
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z
(Note 1)
Max
20
ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Note 1)
Max
20
ns
t
AXQX
t
OH
Output Hold Time From Addresses,
CE# or OE#, Whichever Occurs
First
Min
0
ns
t
OEH
Output Enable
Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
CEH
Chip Enable Hold
Time
Read
Min
35
ns
90
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Read-Only OperationsS29GL128N Only
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and Table
15
for test specifications.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V. AC
specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Description
Test Setup
Speed Options
JEDEC Std.
80
90 90 100 Unit
t
AVAV
t
RC
Read Cycle Time
V
IO
= V
CC
= 3 V
Min
80
90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
AVQV
t
ACC
Address to Output Delay (Note 2)
V
IO
= V
CC
= 3 V
Max
80
90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
ELQV
t
CE
Chip Enable to Output Delay (Note 3)
V
IO
= V
CC
= 3 V
Max
80
90
ns
V
IO
= 2.5 V, V
CC
= 3 V (Note 1)
90 100
V
IO
= 1.8 V, V
CC
= 3 V
90 100
ns
t
PAC
C
Page Access Time
Max
25
25
35
35
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
25
35
35
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
20
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
20
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
tCEH
Chip Enable Hold
Time
Read
Min
35
ns
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
91
A d v a n c e I n f o r m a t i o n
AC Characteristics
* Figure shows word mode. Addresses are A2A-1 for byte mode.
Figure 12. Page Read Timings
Figure 11. Read Operation Timings
t
OH
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
t
CEH
A23-A2
CE#
OE#
A2-A0*
Data Bus
Same Page
Aa
Ab
Ac
Ad
Qa
Qb
Qc
Qd
t
ACC
t
PACC
t
PACC
t
PACC
92
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Hardware Reset (RESET#)
Note:
Not 100% tested. If ramp rate is equal to or faster than 1V/100s with a falling edge of the RESET# pin initiated,
the RESET# pin needs to be held low only for 100s for power-up..
Parameter
Description
All Speed Options
Unit
JEDEC
Std.
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
1
ms
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
1
ms
t
RP
RESET# Pulse Width
Min
1
ms
t
RH
Reset High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
s
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
Figure 13. Reset Timings
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
93
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program OperationsS29GL512N Only
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 100 ns and 110 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
90
100
100
110
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
90
100
100
110
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle
bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
240
s
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
15
s
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
t
VHH
V
HH
Rise and Fall Time (Note 1)
Min
250
ns
t
VCS
V
CC
Setup Time (Note 1)
Min
50
s
94
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program OperationsS29GL256N Only
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
80
90
90
100
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
90
100
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle
bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
240
s
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
15
s
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
t
VHH
V
HH
Rise and Fall Time (Note 1)
Min
250
ns
t
VCS
V
CC
Setup Time (Note 1)
Min
50
s
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
95
A d v a n c e I n f o r m a t i o n
AC Characteristics
Erase and Program OperationsS29GL128N Only
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
80
90
90
100
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
90
100
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle
bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
240
s
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Typ
15
s
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
t
VHH
V
HH
Rise and Fall Time (Note 1)
Min
250
ns
t
VCS
V
CC
Setup Time (Note 1)
Min
50
s
96
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Notes:
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 9 and
Table
15
for test specifications.
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0A0h
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
Notes:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
2. Illustration shows device in word mode.
Figure 14. Program Operation Timings
ACC
t
VHH
V
HH
V
IL
or V
IH
V
IL
or V
IH
t
VHH
Figure 15. Accelerated Program Timing Diagram
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
97
A d v a n c e I n f o r m a t i o n
AC Characteristics
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status".
2. These waveforms are for the word mode.
Figure 16. Chip/Sector Erase Operation Timings
98
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Figure 17. Data# Polling Timings
(During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
2. t
OE
for data polling is 45 ns when V
IO
= 1.65 to 2.7 V and is 35 ns when V
IO
= 2.7 to 3.6 V
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
99
A d v a n c e I n f o r m a t i o n
AC Characteristics
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read)
(second read)
(stops toggling)
t
CEPH
t
AHT
t
AS
DQ2 and DQ6
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command
sequence, last status read cycle, and array data read cycle
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#
or CE# to toggle DQ2 and DQ6.
Figure 19. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
100
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL512N Only
Notes:
1. Not 100% tested.
2. See the "AC Characteristics" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 100 ns and 110 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
90
100
100
110
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
90
100
100
110
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
45
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
45
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2,
3)
Typ
240
s
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
Typ
15
s
Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
101
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL256N Only
Notes:
1. Not 100% tested.
2. See the "AC Characteristics" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V. AC
specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
80
90
90
100
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
90
100
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
45
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
45
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2,
3)
Typ
240
s
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
Typ
15
s
Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
102
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL128N Only
Notes:
1. Not 100% tested.
2. See the "AC Characteristics" section for more information.
3. For 116 words/132 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V. AC
specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter
Speed Options
JEDEC
Std.
Description
80
90
90
100
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
90
100
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
ns
t
DVEH
t
DS
Data Setup Time
Min
45
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
45
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2,
3)
Typ
240
s
Effective Write Buffer
Program Operation (Notes
2, 4)
Per Word
Typ
15
s
Effective Accelerated Write
Buffer Program Operation
(Notes 2, 4)
Per Word
Typ
13.5
s
Program Operation (Note 2)
Word
Typ
60
s
Accelerated Programming
Operation (Note 2)
Word
Typ
54
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1.0
sec
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
103
A d v a n c e I n f o r m a t i o n
AC Characteristics
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
OUT
is the data written to the device.
4. Waveforms are for the word mode.
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
104
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25C, 3.0 V V
CC
, 10,000 cycles, checkerboard
pattern.
2. Under worst case conditions of 90C, V
CC
= 3.0 V, 1,000,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 17 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
1
3.5
sec
Excludes 00h programming
prior to erasure (Note 5)
Chip Erase Time
S29GL128N
128
256
sec
S29GL256N
256
512
S29GL512N
512
1024
Total Write Buffer Time
(Note 3)
240
s
Excludes system level
overhead (Note 6)
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
200
s
Chip Program Time
S29GL128N
123
sec
S29GL256N
246
S29GL512N
492
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
TSOP
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
TSOP
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
TSOP
7.5
9
pF
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
105
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TS056--56-Pin Standard Thin Small Outline Package (TSOP)
NOTES:
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
2
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
4
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
5
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
6
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
7
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING
PLANE.
8
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3160\38.10A
MO-142 (B) EC
TS 56
NOM.
---
---
1.00
1.20
0.15
1.05
MAX.
---
MIN.
0.95
0.20
0.23
0.17
0.22
0.27
0.17
---
0.16
0.10
---
0.21
0.10
20.00
20.20
19.80
14.00
14.10
13.90
0.60
0.70
0.50
-
8
0
---
0.20
0.08
56
18.40
18.50
18.30
0.05
0.50 BASIC
E
R
b1
JEDEC
PACKAGE
SYMBOL
A
A2
A1
D1
D
c1
c
b
e
L
N
O
106
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Physical Dimensions
LAA064--64-Ball Fortified Ball Grid Array (FBGA)
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
107
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A (September 2, 2003)
Initial Release.
Revision A+1 (October 16, 2003)
Global
Added LAA064 package.
Distinctive Characteristics, Performance Characteristics
Clarified fifth bullet information.
Added RTSOP to Package Options.
Distinctive Characteristics, Software and Hardware Features
Clarified "Password Sector Protection" to "Advanced Sector Protection"
Connection Diagrams
Removed Note.
Ordering Information
Modified Package codes
Device Bus Operations, Table 1
Modified Table, removed Note.
Sector Address Tables
All address ranges doubled in all sector address tables.
Sector Protection
Lock Register: Corrected text to reflect 3 bits instead of 4.
Table 6, Lock Register: Corrected address range from DQ15-5 to DQ15-3; re-
moved DQ4 and DQ3; Corrected DQ15-3 Lock Register to Don't Care.
Table 7, Sector Protection Schemes: Corrected Sector States.
Command Definitions
Table 12, Command Definitions, x16
Nonvolatile Sector Protection Command Set Entry Second Cycle Address cor-
rected from 55 to 2AA.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Table 13, Command Definitions, x8
Password Read and Unlock Addresses and Data corrected.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Test Conditions
Table 15, Test Specifications and Figure 10, Input Waveforms and Measurement
Levels: Corrected Input Pulse Levels to 0.0VIO; corrected Input timing mea-
surement reference levels to 0.5V
IO
.
108
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Revision A+2 (January 22, 2004)
Lock Register
Corrected and added new text for SecSi Sector Protection Bit, Persistent Protec-
tion Mode Lock Bit, and Password Protection Mode Lock Bit.
Persistent Sector Protection
Persistent Protection Bit (PPB): Added the second paragraph text about program-
ming the PPB bit.
Persistent Protection Bit Lock (PPB Lock Bit): Added the second paragraph text
about configuring the PPB Lock Bit, and fourth paragraph on Autoselect Sector
Protection Verification.
Added PPB Lock Bit requirement of 200ns access time.
Password Sector Protection
Corrected 1 s (built-in delay for each password check) to 2 s.
Lock Register Command Set Definitions
Added new information for this section.
Password Protection Command Set Definitions
Added new information for this section.
Non-Volatile Sector Protection Command Set Definitions
Added new information for this section.
Global Volatile Sector Protection Freeze Command Set
Added new information for this section.
Volatile Sector Protection Command Set
Added new information for this section.
SecSi Sector Entry Command
Added new information for this section.
SecSi Sector Exit Command
Added new information for this section.
Revision A+3 (March 2, 2004)
Connection Diagrams
Removed 56-pin reverse TSOP diagram.
Ordering Information
Updated the Standard Products for the S29GL512/256/128N devices and modi-
fied the valid combinations tables.
Word Program Command Sequence
Added new information to this section.
Lock Register Command Set Definitions
Added new information to this section.
Table 13
Updated this table.
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
109
A d v a n c e I n f o r m a t i o n
Revision A+4 (May 13, 2004)
Global
Removed references to RTSOP.
Distinctive Characteristics
Removed 16-word/32-byte page read buffer from Performance Characteristics.
Changed Low power consumption to 25 mA typical active read current and re-
moved 10 mA typical intrapage active read current.
Ordering Information
Changed formatting of pages.
Changed model numbers from 00,01,02,03 to 01, 02, V1, V2.
Table 1, "Device Bus Operations"
Combined WP# and ACC columns.
Table 8, "CFI Query Identification String", Table 9, "System Interface
String", Table 10, "Device Geometry Definition", and Table 11, "Primary
Vendor-Specific Extended Query
Added Address (x8) column.
Word Program Command Sequence
Added text to fourth paragraph.
Figure 1, "Write Buffer Programming Operation,"
Added note references and removed DQ15 and DQ13.
Figure 3, "Program Suspend/Program Resume,"
Changed field to read XXXh/B0h and XXXh/30h.
Password Protection Command Set Definitions
Replaced all text.
Table 12, "S29GL512N, S29GL256N, S29GL128N Command Definitions,
x16"
Changed the first cycle address of CFI Query to 55.
Table 13, "S29GL512N, S29GL256N, S29GL128N Command Definitions,
x8"
Changed the third cycle data Device ID to 90.
Removed Unlock Bypass Reset.
Removed Note 12 and 13.
Figure 5, "Data# Polling Algorithm,"
Removed DQ15 and DQ13.
Absoulte Maximum Ratings
Removed VCC from "All other pins" with respect to Ground.
CMOS Compatible
Changed the Max of I
CC4
to 70 mA
Added V
IL
to the Test conditions of I
CC5
, I
CC6
, and I
CC7
Change the Min of V
IL
to - 0.1 V.
Updated note 5.
Read-Only OperationsS29GL128N Only
Added t
CEH
parameter to table.
110
S29GLxxxN MirrorBitTM Flash Family
27631A4 May 13, 2004
A d v a n c e I n f o r m a t i o n
Figure 11, "Read Operation Timings,"
Added t
CEH
to figure.
Figure 12, "Page Read Timings,"
Change A1-A0 to A2-A0.
Erase and Program Operations
Updated t
WHWH1
and t
WHWH2
with values.
Figure 16, "Chip/Sector Erase Operation Timings,"
Changed 5555h to 55h and 3030h to 30h.
Figure 17, "Data# Polling Timings (During Embedded Algorithms),"
Removed DQ15 and DQ14-DQ8
Added Note 2
Figure 18, "Toggle Bit Timings (During Embedded Algorithms),"
Changed DQ6 & DQ14/DQ2 & DQ10 to DQ2 and DQ6.
Alternate CE# Controlled Erase and Program Operations
Updated t
WHWH1
and t
WHWH2
with values.
Latchup Characteristics
Removed Table.
Erase and Programming Performance
Updated TBD with values.
Updated Note 1 and 2.
Physical Dimensions
Removed the reverse pinout information and note 3.
Trademarks and Notice
The contents of this document are subject to change without notice.
This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work
on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness,
operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL
LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.
Copyright 2004 FASL LLC. All rights reserved.
Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this
publication are for identification purposes only and may be trademarks of their respective companies.
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