This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the

right to change or discontinue work on this proposed product without notice.

Publication Number S29JL064H Revision A Amendment 1 Issue Date March 26, 2004

PRELIMINARY

S29JL064H

64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory

Distinctive Characteristics

Architectural Advantages

Simultaneous Read/Write operations
-- Data can be continuously read from one bank while

executing erase/program functions in another bank.

-- Zero latency between read and write operations
Flexible Bank architecture
-- Read may occur in any of the three banks not being

written or erased.

-- Four banks may be grouped by customer to achieve

desired bank divisions.

Boot Sectors
-- Top and bottom boot sectors in the same device
-- Any combination of sectors can be erased
Manufactured on 0.13 µm process technology
SecSiTM (Secured Silicon) Sector: Extra 256 Byte
sector
-- Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function.

-- Customer lockable: One-time programmable only.

Once locked, data cannot be changed

Zero Power Operation
-- Sophisticated power management circuits reduce

power consumed during inactive periods to nearly
zero.

Compatible with JEDEC standards
-- Pinout and software compatible with single-power-

supply flash standard

Package options

63-ball Fine Pitch BGA
48-pin TSOP

Performance Characteristics

High performance
-- Access time as fast as 55 ns
-- Program time: 4 µs/word typical using accelerated

programming function

Ultra low power consumption (typical values)
-- 2 mA active read current at 1 MHz
-- 10 mA active read current at 5 MHz
-- 200 nA in standby or automatic sleep mode
Cycling Endurance: 1 million cycles per sector
typical
Data Retention: 20 years typical

Software Features

Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
-- Suspends erase operations to read data from, or

program data to, a sector that is not being erased,
then resumes the erase operation.

Data# Polling and Toggle Bits
-- Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command
-- Reduces overall programming time when issuing

multiple program command sequences

Hardware Features

Ready/Busy# output (RY/BY#)
-- Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)
-- Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin
-- Write protect (WP#) function protects sectors 0, 1,

140, and 141, regardless of sector protect status

-- Acceleration (ACC) function accelerates program

timing

Sector protection
-- Hardware method to prevent any program or erase

operation within a sector

-- Temporary Sector Unprotect allows changing data in

protected sectors in-system

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S29JL064HA1 March 26, 2004

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General Description

The S29JL064H is a 64 megabit, 3.0 volt-only flash memory device, organized as
4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode
data appears on DQ15DQ0; byte mode data appears on DQ7DQ0. The device
is designed to be programmed in-system with the standard 3.0 volt V

supply,

and can also be programmed in standard EPROM programmers.

The device is available with an access time of 55, 60, 70, or 90 ns and is offered
in 48-pin TSOP and 63-ball Fine Pitch BGA packages. Standard control pins--chip
enable (CE#), write enable (WE#), and output enable (OE#)--control normal
read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into four banks, two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed,
system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy banks may be
read from. Note that only two banks can operate simultaneously. The device can
improve overall system performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from the other
bank, with zero latency. This releases the system from waiting for the completion
of program or erase operations.

The S29JL064H can be organized as both a top and bottom boot sector
configuration.

S29JL064H Features

The SecSiTM (Secured Silicon) Sector is an extra 256 byte sector capable of
being permanently locked by FASL or customers. The SecSi Customer Indicator
Bit (DQ6) is permanently set to 1 if the part has been customer locked, perma-
nently set to 0 if the part has been factory locked, and is 0 if customer lockable.
This way, customer lockable parts can never be used to replace a factory locked
part.

Factory locked parts provide several options. The SecSi Sector may store a se-
cure, random 16 byte ESN (Electronic Serial Number), customer code
(programmed through Spansion programming services), or both. Customer Lock-
able parts may utilize the SecSi Sector as bonus space, reading and writing like
any other flash sector, or may permanently lock their own code there.

Bank

Megabits

Sector Sizes

Bank 1

8 Mb

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 2

24 Mb

Forty-eight 64 Kbyte/32 Kword

Bank 3

24 Mb

Forty-eight 64 Kbyte/32 Kword

Bank 4

8 Mb

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

March 26, 2004 S29JL064HA1

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P r e l i m i n a r y

DMS (Data Management Software) allows systems to easily take advantage
of the advanced architecture of the simultaneous read/write product line by al-
lowing removal of EEPROM devices. DMS will also allow the system software to
be simplified, as it will perform all functions necessary to modify data in file struc-
tures, as opposed to single-byte modifications. To write or update a particular
piece of data (a phone number or configuration data, for example), the user only
needs to state which piece of data is to be updated, and where the updated data
is located in the system. This is an advantage compared to systems where user-
written software must keep track of the old data location, status, logical to phys-
ical translation of the data onto the Flash memory device (or memory devices),
and more. Using DMS, user-written software does not need to interface with the
Flash memory directly. Instead, the user's software accesses the Flash memory
by calling one of only six functions.

The device offers complete compatibility with the JEDEC 42.4 sin-
gle-power-supply Flash command set standard. Commands are written to
the command register using standard microprocessor write timings. Reading data
out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by
using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2
(toggle bits). After a program or erase cycle has been completed, the device au-
tomatically returns to the read mode.

The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low V

detector that automat-

ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.

The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is greatly reduced in both modes.

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. S29JL064H Device Bus Operations ..........................10

Requirements for Reading Array Data ............................................11
Writing Commands/Command Sequences .................................... 11
Accelerated Program Operation ...................................................... 12
Autoselect Functions ............................................................................ 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Automatic Sleep Mode ......................................................................... 13
RESET#: Hardware Reset Pin ............................................................ 13
Output Disable Mode ........................................................................... 14

Table 2. S29JL064H Sector Architecture ...............................15
Table 3. Bank Address .......................................................18

Autoselect Mode ...................................................................................18

Table 5. S29JL064H Autoselect Codes, (High Voltage

Method) .........................................................................19

Sector/Sector Block Protection and Unprotection .................... 19

Table 6. S29JL064H Boot Sector/Sector Block Addresses for

Protection/Unprotection .....................................................20

Write Protect (WP#) ........................................................................... 21

Table 7. WP#/ACC Modes ..................................................21

Temporary Sector Unprotect ........................................................... 21

Figure 1. Temporary Sector Unprotect Operation................... 22
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 23

SecSiTM (Secured Silicon) Sector

Flash Memory Region .......................................................................... 24

Figure 3. SecSi Sector Protect Verify ................................... 25

Hardware Data Protection ................................................................ 25
Low VCC Write Inhibit ...................................................................... 25
Write Pulse "Glitch" Protection ...................................................... 26
Logical Inhibit ......................................................................................... 26
Power-Up Write Inhibit ..................................................................... 26

Common Flash Memory Interface (CFI) . . . . . . .26
Command Definitions . . . . . . . . . . . . . . . . . . . . . .30

Reading Array Data ............................................................................. 30
Reset Command ................................................................................... 30
Autoselect Command Sequence ....................................................... 31
Enter SecSiTM Sector/Exit SecSi Sector

Command Sequence ............................................................................. 31
Byte/Word Program Command Sequence .................................... 31
Unlock Bypass Command Sequence ............................................... 32

Figure 4. Program Operation .............................................. 33

Chip Erase Command Sequence .......................................................33
Sector Erase Command Sequence .................................................. 34

Figure 5. Erase Operation .................................................. 35

Erase Suspend/Erase Resume Commands .....................................35

Write Operation Status . . . . . . . . . . . . . . . . . . . . .38

DQ7: Data# Polling .............................................................................. 38

Figure 6. Data# Polling Algorithm ....................................... 39

DQ6: Toggle Bit I ..................................................................................40

Figure 7. Toggle Bit Algorithm ............................................ 41

DQ2: Toggle Bit II ................................................................................. 41
Reading Toggle Bits DQ6/DQ2 ........................................................ 42
DQ5: Exceeded Timing Limits .......................................................... 42
DQ3: Sector Erase Timer .................................................................. 42

Table 9. Write Operation Status ......................................... 43

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44

Figure 8. Maximum Negative Overshoot Waveform................ 44
Figure 9. Maximum Positive Overshoot Waveform ................. 44

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .44

Industrial (I) Devices ............................................................................ 44
Extended (N) Devices ......................................................................... 44
V

Supply Voltages ............................................................................ 44

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45

CMOS Compatible ............................................................................... 45

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ................................................. 46
Figure 11. Typical I

CC1

vs. Frequency .................................. 46

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Test Setup ....................................................... 47

Key To Switching Waveforms . . . . . . . . . . . . . . . .47

Figure 13. Input Waveforms and Measurement Levels............ 47

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .48

Read-Only Operations ......................................................................48

Figure 14. Read Operation Timings...................................... 48

Hardware Reset (RESET#) ................................................................49

Figure 15. Reset Timings ................................................... 49

Word/Byte Configuration (BYTE#) ................................................ 50

Figure 16. BYTE# Timings for Read Operations ..................... 51
Figure 17. BYTE# Timings for Write Operations..................... 51

Erase and Program Operations ........................................................ 52

Figure 18. Program Operation Timings ................................. 53
Figure 19. Accelerated Program Timing Diagram ................... 53
Figure 20. Chip/Sector Erase Operation Timings.................... 54
Figure 21. Back-to-back Read/Write Cycle Timings ................ 55
Figure 22. Data# Polling Timings (During Embedded

Algorithms)...................................................................... 55
Figure 23. Toggle Bit Timings (During Embedded

Algorithms)...................................................................... 56
Figure 24. DQ2 vs. DQ6..................................................... 56

Temporary Sector Unprotect .......................................................... 57

Figure 25. Temporary Sector Unprotect Timing Diagram......... 57
Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram ................................................. 58

Alternate CE# Controlled Erase and Program Operations .... 59

Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................. 60

Erase And Programming Performance . . . . . . . . 61
TSOP & BGA Pin Capacitance . . . . . . . . . . . . . . 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 62

FBE063--63-Ball Fine-Pitch Ball Grid Array (BGA)
12 x 11 mm package ............................................................................... 62
TS 048--48-Pin Standard TSOP ...................................................... 63

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64

S29JL064H

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Ordering Information

The order number (Valid Combination) is formed by the following:

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to con-
firm availability of specific valid combinations and to check on newly released combinations.

Note:Listed TSOP part numbers describe products based on Copper (Cu) leadframes. Contact your local sales office for
products based on Alloy-42 leadframes.

S29JL064H

PACKING TYPE
0

= Tray

= 7- inch Tape and Reel

= 13-inch Tape and Reel

MODEL NUMBER (ADDITIONAL ORDERING OPTIONS)
00

= Standard Configuration

TEMPERATURE RANGE
I =

Industrial

(40°C to +85°C)

N = Extended

(40°C to +125°C)

PACKAGE TYPE
TA

= 48-Pin Thin Small Outline Package (TSOP, TS048)

Not Lead (Pb)-free, Copper Leadframe

= 48-Pin Thin Small Outline Package (TSOP, TS048)

Lead (Pb)-Free, Copper Leadframe, Tin plating

= 63-ball Ball Grid Array (BGA, FBE063)

0.8 mm pitch, 12 x 11 mm Package

Not Lead (Pb)-Free

= 63-ball Ball Grid Array (BGA, FBE063)

0.8 mm pitch, 12 x 11 mm Package

Lead (Pb)-Free

SPEED OPTION
55

= 55 ns

= 60 ns

= 70 ns

= 90 ns

DEVICE FAMILY
S29JL064H

3.0 Volt-only, 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) Simultaneous Read/Write Flash Memory

Manufactured on 130 nm process technology

Valid Combinations for TSOP Packages

Order Number

Package Markings

Package

Speed

Temperature Range

S29JL064H55TAI00

Not Lead (Pb)- Free

-4085 °C

S29JL064H55TFI00

Lead (Pb)- Free

S29JL064H60TAI00

Not Lead (Pb)- Free

S29JL064H60TFI00

Lead (Pb)- Free

S29JL064H70TAI00

Not Lead (Pb)- Free

S29JL064H70TFI00

Lead (Pb)- Free

S29JL064H90TAI00

Not Lead (Pb)- Free

S29JL064H90TFI00

Lead (Pb)- Free

S29JL064H70TAN00

Not Lead (Pb)- Free

-40125 °C

S29JL064H70TFN00

Lead (Pb)- Free

S29JL064H90TAN00

Not Lead (Pb)- Free

S29JL064H90TFN00

Lead (Pb)- Free

S29JL064H

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Device Bus Operations

This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table

lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of
these operations in further detail.

Table 1. S29JL064H Device Bus Operations

Legend: L = Logic Low = V

, H = Logic High = V

, V

= 11.512.5 V, V

= 9.0 ± 0.5 V, X = Don't Care, SA = Sector

Address, A

= Address In, D

= Data In, D

OUT

= Data Out

Notes:
1. Addresses are A21:A0 in word mode (BYTE# = V

), A21:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

the "Sector/Sector Block Protection and Unprotection" section.

3. If WP#/ACC = V

, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V

, protection on sectors 0, 1, 140,

and 141 depends on whether they were last protected or unprotected using the method described in "Sector/Sector
Block Protection and Unprotection". If WP#/ACC = V

, all sectors will be unprotected.

Operation

CE#

OE# WE# RESET# WP#/ACC

Addresses

(Note 2)

DQ15DQ8

DQ7

DQ0

BYTE#

= V

BYTE#

= V

Read

L/H

OUT

DQ14DQ8 = High-

Z, DQ15 = A-1

OUT

Write

(Note 3)

Standby

0.3 V

L/H

High-Z

Output Disable

L/H

High-Z

Reset

L/H

High-Z

Sector Protect (Note 2)

L/H

SA, A6 = L,

A1 = H, A0 = L

Sector Unprotect (Note 2)

(Note 3)

SA, A6 = H,

A1 = H, A0 = L

Temporary Sector
Unprotect

(Note 3)

High-Z

March 26, 2004 S29JL064HA1

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P r e l i m i n a r y

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic `1', the device is in word con-
figuration, DQ15DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic `0', the device is in byte configuration, and only
data I/O pins DQ7DQ0 are active and controlled by CE# and OE#. The data I/
O pins DQ14DQ8 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE#
pins to V

. CE# is the power control and selects the device. OE# is the output

control and gates array data to the output pins. WE# should remain at V

. The

BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.

Refer to the AC Read-Only Operations table for timing specifications and to 14 for
the timing diagram. I

CC1

in the DC Characteristics table represents the active cur-

rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to "Word/Byte Configuration" for more
information.

The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The "Byte/Word Program Command
Sequence" section has details on programming data to the device using both
standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.
Table

indicates the address space that each sector occupies. Similarly, a "sector

address" is the address bits required to uniquely select a sector. The "Command
Definitions" section has details on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.

The device address space is divided into four banks. A "bank address" is the ad-
dress bits required to uniquely select a bank.

CC2

in the DC Characteristics table represents the active current specification for

the write mode. The AC Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.

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P r e l i m i n a r y

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V

from the WP#/ACC pin re-

turns the device to normal operation. Note that V

must not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result. See "Write Protect
(WP#)" on page 21. for related information.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while program-
ming or erasing in the other bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased).

Figure 21

shows how read and write cycles may be

initiated for simultaneous operation with zero latency. I

CC6

and I

CC7

in the DC

Characteristics table represent the current specifications for read-while-program
and read-while-erase, respectively.

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

Standby Mode

When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.

The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V

± 0.3 V. (Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at V

, but not within V

± 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t

) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.

CC3

in the DC Characteristics table represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t

ACC

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. I

CC5

in the DC Characteristics table represents the automatic sleep

mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t

, the

device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V

±0.3 V, the device draws CMOS standby current (I

CC4

). If RESET# is held

at V

but not within V

±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a "0" (busy) until the internal reset operation is complete, which requires
a time of t

READY

(during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is "1"), the reset
operation is completed within a time of t

READY

(not during Embedded Algorithms).

The system can read data t

after the RESET# pin returns to V

Refer to the AC Characteristics tables for RESET# parameters and to 15 for the
timing diagram.

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S29JL064HA1 March 26, 2004

P r e l i m i n a r y

Bank 2

SA23

0010000xxx

64/32

100000h10FFFFh

80000h87FFFh

SA24

0010001xxx

64/32

110000h11FFFFh

88000h8FFFFh

SA25

0010010xxx

64/32

120000h12FFFFh

90000h97FFFh

SA26

0010011xxx

64/32

130000h13FFFFh

98000h9FFFFh

SA27

0010100xxx

64/32

140000h14FFFFh

A0000hA7FFFh

SA28

0010101xxx

64/32

150000h15FFFFh

A8000hAFFFFh

SA29

0010110xxx

64/32

160000h16FFFFh

B0000hB7FFFh

SA30

0010111xxx

64/32

170000h17FFFFh

B8000hBFFFFh

SA31

0011000xxx

64/32

180000h18FFFFh

C0000hC7FFFh

SA32

0011001xxx

64/32

190000h19FFFFh

C8000hCFFFFh

SA33

0011010xxx

64/32

1A0000h1AFFFFh

D0000hD7FFFh

SA34

0011011xxx

64/32

1B0000h1BFFFFh

D8000hDFFFFh

SA35

0011000xxx

64/32

1C0000h1CFFFFh

E0000hE7FFFh

SA36

0011101xxx

64/32

1D0000h1DFFFFh

E8000hEFFFFh

SA37

0011110xxx

64/32

1E0000h1EFFFFh

F0000hF7FFFh

SA38

0011111xxx

64/32

1F0000h1FFFFFh

F8000hFFFFFh

SA39

0100000xxx

64/32

200000h20FFFFh

100000h107FFFh

SA40

0100001xxx

64/32

210000h21FFFFh

108000h10FFFFh

SA41

0100010xxx

64/32

220000h22FFFFh

110000h117FFFh

SA42

0101011xxx

64/32

230000h23FFFFh

118000h11FFFFh

SA43

0100100xxx

64/32

240000h24FFFFh

120000h127FFFh

SA44

0100101xxx

64/32

250000h25FFFFh

128000h12FFFFh

SA45

0100110xxx

64/32

260000h26FFFFh

130000h137FFFh

SA46

0100111xxx

64/32

270000h27FFFFh

138000h13FFFFh

SA47

0101000xxx

64/32

280000h28FFFFh

140000h147FFFh

SA48

0101001xxx

64/32

290000h29FFFFh

148000h14FFFFh

SA49

0101010xxx

64/32

2A0000h2AFFFFh

150000h157FFFh

SA50

0101011xxx

64/32

2B0000h2BFFFFh

158000h15FFFFh

SA51

0101100xxx

64/32

2C0000h2CFFFFh

160000h167FFFh

SA52

0101101xxx

64/32

2D0000h2DFFFFh

168000h16FFFFh

SA53

0101110xxx

64/32

2E0000h2EFFFFh

170000h177FFFh

SA54

0101111xxx

64/32

2F0000h2FFFFFh

178000h17FFFFh

SA55

0110000xxx

64/32

300000h30FFFFh

180000h187FFFh

SA56

0110001xxx

64/32

310000h31FFFFh

188000h18FFFFh

SA57

0110010xxx

64/32

320000h32FFFFh

190000h197FFFh

SA58

0110011xxx

64/32

330000h33FFFFh

198000h19FFFFh

SA59

0110100xxx

64/32

340000h34FFFFh

1A0000h1A7FFFh

SA60

0110101xxx

64/32

350000h35FFFFh

1A8000h1AFFFFh

SA61

0110110xxx

64/32

360000h36FFFFh

1B0000h1B7FFFh

SA62

0110111xxx

64/32

370000h37FFFFh

1B8000h1BFFFFh

SA63

0111000xxx

64/32

380000h38FFFFh

1C0000h1C7FFFh

SA64

0111001xxx

64/32

390000h39FFFFh

1C8000h1CFFFFh

SA65

0111010xxx

64/32

3A0000h3AFFFFh

1D0000h1D7FFFh

SA66

0111011xxx

64/32

3B0000h3BFFFFh

1D8000h1DFFFFh

SA67

0111100xxx

64/32

3C0000h3CFFFFh

1E0000h1E7FFFh

SA68

0111101xxx

64/32

3D0000h3DFFFFh

1E8000h1EFFFFh

SA69

0111110xxx

64/32

3E0000h3EFFFFh

1F0000h1F7FFFh

SA70

0111111xxx

64/32

3F0000h3FFFFFh

1F8000h1FFFFFh

Table 2. S29JL064H Sector Architecture (Continued)

Bank

Sector

Sector Address

A21A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

Bank 3

SA71

1000000xxx

64/32

400000h40FFFFh

200000h207FFFh

SA72

1000001xxx

64/32

410000h41FFFFh

208000h20FFFFh

SA73

1000010xxx

64/32

420000h42FFFFh

210000h217FFFh

SA74

1000011xxx

64/32

430000h43FFFFh

218000h21FFFFh

SA75

1000100xxx

64/32

440000h44FFFFh

220000h227FFFh

SA76

1000101xxx

64/32

450000h45FFFFh

228000h22FFFFh

SA77

1000110xxx

64/32

460000h46FFFFh

230000h237FFFh

SA78

1000111xxx

64/32

470000h47FFFFh

238000h23FFFFh

SA79

1001000xxx

64/32

480000h48FFFFh

240000h247FFFh

SA80

1001001xxx

64/32

490000h49FFFFh

248000h24FFFFh

SA81

1001010xxx

64/32

4A0000h4AFFFFh

250000h257FFFh

SA82

1001011xxx

64/32

4B0000h4BFFFFh

258000h25FFFFh

SA83

1001100xxx

64/32

4C0000h4CFFFFh

260000h267FFFh

SA84

1001101xxx

64/32

4D0000h4DFFFFh

268000h26FFFFh

SA85

1001110xxx

64/32

4E0000h4EFFFFh

270000h277FFFh

SA86

1001111xxx

64/32

4F0000h4FFFFFh

278000h27FFFFh

SA87

1010000xxx

64/32

500000h50FFFFh

280000h28FFFFh

SA88

1010001xxx

64/32

510000h51FFFFh

288000h28FFFFh

SA89

1010010xxx

64/32

520000h52FFFFh

290000h297FFFh

SA90

1010011xxx

64/32

530000h53FFFFh

298000h29FFFFh

SA91

1010100xxx

64/32

540000h54FFFFh

2A0000h2A7FFFh

SA92

1010101xxx

64/32

550000h55FFFFh

2A8000h2AFFFFh

SA93

1010110xxx

64/32

560000h56FFFFh

2B0000h2B7FFFh

SA94

1010111xxx

64/32

570000h57FFFFh

2B8000h2BFFFFh

SA95

1011000xxx

64/32

580000h58FFFFh

2C0000h2C7FFFh

SA96

1011001xxx

64/32

590000h59FFFFh

2C8000h2CFFFFh

SA97

1011010xxx

64/32

5A0000h5AFFFFh

2D0000h2D7FFFh

SA98

1011011xxx

64/32

5B0000h5BFFFFh

2D8000h2DFFFFh

SA99

1011100xxx

64/32

5C0000h5CFFFFh

2E0000h2E7FFFh

SA100

1011101xxx

64/32

5D0000h5DFFFFh

2E8000h2EFFFFh

SA101

1011110xxx

64/32

5E0000h5EFFFFh

2F0000h2FFFFFh

SA102

1011111xxx

64/32

5F0000h5FFFFFh

2F8000h2FFFFFh

SA103

1100000xxx

64/32

600000h60FFFFh

300000h307FFFh

SA104

1100001xxx

64/32

610000h61FFFFh

308000h30FFFFh

SA105

1100010xxx

64/32

620000h62FFFFh

310000h317FFFh

SA106

1100011xxx

64/32

630000h63FFFFh

318000h31FFFFh

SA107

1100100xxx

64/32

640000h64FFFFh

320000h327FFFh

SA108

1100101xxx

64/32

650000h65FFFFh

328000h32FFFFh

SA109

1100110xxx

64/32

660000h66FFFFh

330000h337FFFh

SA110

1100111xxx

64/32

670000h67FFFFh

338000h33FFFFh

SA111

1101000xxx

64/32

680000h68FFFFh

340000h347FFFh

SA112

1101001xxx

64/32

690000h69FFFFh

348000h34FFFFh

SA113

1101010xxx

64/32

6A0000h6AFFFFh

350000h357FFFh

SA114

1101011xxx

64/32

6B0000h6BFFFFh

358000h35FFFFh

SA115

1101100xxx

64/32

6C0000h6CFFFFh

360000h367FFFh

SA116

1101101xxx

64/32

6D0000h6DFFFFh

368000h36FFFFh

SA117

1101110xxx

64/32

6E0000h6EFFFFh

370000h377FFFh

SA118

1101111xxx

64/32

6F0000h6FFFFFh

378000h37FFFFh

Table 2. S29JL064H Sector Architecture (Continued)

Bank

Sector

Sector Address

A21A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

Note: The address range is A21:A-1 in byte mode (BYTE#=V

) or A21:A0 in word mode (BYTE#=V

Table 3. Bank Address

Table 4. SecSi

Sector Addresses

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.

Bank 4

SA119

1110000xxx

64/32

700000h70FFFFh

380000h387FFFh

SA120

1110001xxx

64/32

710000h71FFFFh

388000h38FFFFh

SA121

1110010xxx

64/32

720000h72FFFFh

390000h397FFFh

SA122

1110011xxx

64/32

730000h73FFFFh

398000h39FFFFh

SA123

1110100xxx

64/32

740000h74FFFFh

3A0000h3A7FFFh

SA124

1110101xxx

64/32

750000h75FFFFh

3A8000h3AFFFFh

SA125

1110110xxx

64/32

760000h76FFFFh

3B0000h3B7FFFh

SA126

1110111xxx

64/32

770000h77FFFFh

3B8000h3BFFFFh

SA127

1111000xxx

64/32

780000h78FFFFh

3C0000h3C7FFFh

SA128

1111001xxx

64/32

790000h79FFFFh

3C8000h3CFFFFh

SA129

1111010xxx

64/32

7A0000h7AFFFFh

3D0000h3D7FFFh

SA130

1111011xxx

64/32

7B0000h7BFFFFh

3D8000h3DFFFFh

SA131

1111100xxx

64/32

7C0000h7CFFFFh

3E0000h3E7FFFh

SA132

1111101xxx

64/32

7D0000h7DFFFFh

3E8000h3EFFFFh

SA133

1111110xxx

64/32

7E0000h7EFFFFh

3F0000h3F7FFFh

SA134

1111111000

8/4

7F0000h7F1FFFh

3F8000h3F8FFFh

SA135

1111111001

8/4

7F2000h7F3FFFh

3F9000h3F9FFFh

SA136

1111111010

8/4

7F4000h7F5FFFh

3FA000h3FAFFFh

SA137

1111111011

8/4

7F6000h7F7FFFh

3FB000h3FBFFFh

SA138

1111111100

8/4

7F8000h7F9FFFh

3FC000h3FCFFFh

SA139

1111111101

8/4

7FA000h7FBFFFh

3FD000h3FDFFFh

SA140

1111111110

8/4

7FC000h7FDFFFh

3FE000h3FEFFFh

SA141

1111111111

8/4

7FE000h7FFFFFh

3FF000h3FFFFFh

Bank

A21A19

000

001, 010, 011

100, 101, 110

111

Device

Sector Size

(x8)

Address Range

(x16)

Address Range

S29JL064H

256 bytes

000000h0000FFh

000000h00007Fh

Table 2. S29JL064H Sector Architecture (Continued)

Bank

Sector

Sector Address

A21A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

When using programming equipment, the autoselect mode requires

on ad-

dress pin A9. Address pins must be as shown in Table

. In addition, when

verifying sector protection, the sector address must appear on the appropriate
highest order address bits (see Table

). Table

shows the remaining address

bits that are don't care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on
DQ7DQ0. However, the autoselect codes can also be accessed in-system
through the command register, for instances when the S29JL064 is erased or pro-
grammed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in Table

. Note that if a Bank Address (BA) on address

bits A21, A20, and A19 is asserted during the third write cycle of the autoselect
command, the host system can read autoselect data from that bank and then im-
mediately read array data from another bank, without exiting the autoselect
mode.

To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table

. This method does

not require V

. Refer to the Autoselect Command Sequence section for more

information.

Table 5. S29JL064H Autoselect Codes, (High Voltage Method)

Legend: L = Logic Low = V

, H = Logic High = V

, BA = Bank Address, SA = Sector Address, X = Don't care.

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term "sector" applies to both sectors and
sector blocks. A sector block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table

The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors. Sector protection/
unprotection can be implemented via two methods.

Description

CE# OE# WE#

A21

A12

A11

A10

DQ15 to DQ8

DQ7

DQ0

BYTE#

= V

BYTE#

= V

Manufacturer ID:
Spansion Products

01h

Dev

i
c
e

Read Cycle 1

22h

7Eh

Read Cycle 2

22h

02h

Read Cycle 3

22h

01h

Sector Protection
Verification

01h (protected),

00h (unprotected)

SecSi Indicator Bit
(DQ6, DQ7)

80h (factory locked),

40h (customer

locked), 00h (not
factory/customer

locked)

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

Table 6. S29JL064H Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector

A21A12

Sector/

Sector Block Size

SA0

0000000000

8 Kbytes

SA1

0000000001

8 Kbytes

SA2

0000000010

8 Kbytes

SA3

0000000011

8 Kbytes

SA4

0000000100

8 Kbytes

SA5

0000000101

8 Kbytes

SA6

0000000110

8 Kbytes

SA7

0000000111

8 Kbytes

SA8SA10

0000001XXX,
0000010XXX,
0000011XXX,

192 (3x64) Kbytes

SA11SA14

00001XXXXX

256 (4x64) Kbytes

SA15SA18

00010XXXXX

256 (4x64) Kbytes

SA19SA22

00011XXXXX

256 (4x64) Kbytes

SA23SA26

00100XXXXX

256 (4x64) Kbytes

SA27-SA30

00101XXXXX

256 (4x64) Kbytes

SA31-SA34

00110XXXXX

256 (4x64) Kbytes

SA35-SA38

00111XXXXX

256 (4x64) Kbytes

SA39-SA42

01000XXXXX

256 (4x64) Kbytes

SA43-SA46

01001XXXXX

256 (4x64) Kbytes

SA47-SA50

01010XXXXX

256 (4x64) Kbytes

SA51-SA54

01011XXXXX

256 (4x64) Kbytes

SA55SA58

01100XXXXX

256 (4x64) Kbytes

SA59SA62

01101XXXXX

256 (4x64) Kbytes

SA63SA66

01110XXXXX

256 (4x64) Kbytes

SA67SA70

01111XXXXX

256 (4x64) Kbytes

SA71SA74

10000XXXXX

256 (4x64) Kbytes

SA75SA78

10001XXXXX

256 (4x64) Kbytes

SA79SA82

10010XXXXX

256 (4x64) Kbytes

SA83SA86

10011XXXXX

256 (4x64) Kbytes

SA87SA90

10100XXXXX

256 (4x64) Kbytes

SA91SA94

10101XXXXX

256 (4x64) Kbytes

SA95SA98

10110XXXXX

256 (4x64) Kbytes

SA99SA102

10111XXXXX

256 (4x64) Kbytes

SA103SA106

11000XXXXX

256 (4x64) Kbytes

SA107SA110

11001XXXXX

256 (4x64) Kbytes

SA111SA114

11010XXXXX

256 (4x64) Kbytes

SA115SA118

11011XXXXX

256 (4x64) Kbytes

SA119SA122

11100XXXXX

256 (4x64) Kbytes

SA123SA126

11101XXXXX

256 (4x64) Kbytes

SA127SA130

11110XXXXX

256 (4x64) Kbytes

SA131SA133

1111100XXX,
1111101XXX,

1111110XXX

192 (3x64) Kbytes

SA134

1111111000

8 Kbytes

SA135

1111111001

8 Kbytes

SA136

1111111010

8 Kbytes

SA137

1111111011

8 Kbytes

SA138

1111111100

8 Kbytes

SA139

1111111101

8 Kbytes

SA140

1111111110

8 Kbytes

SA141

1111111111

8 Kbytes

Sector

A21A12

Sector/

Sector Block Size

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

Sector protect/Sector Unprotect requires V

on the RESET# pin only, and can be

implemented either in-system or via programming equipment.

Figure 2

shows

the algorithms and

Figure 26

shows the timing diagram. For sector unprotect, all

unprotected sectors must first be protected prior to the first sector unprotect
write cycle. Note that the sector unprotect algorithm unprotects all sectors in par-
allel. All previously protected sectors must be individually re-protected. To
change data in protected sectors efficiently, the temporary sector unprotect func-
tion is available. See

"Temporary Sector Unprotect"

The device is shipped with all sectors unprotected. Optional Spansion program-
ming service enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See the
Autoselect Mode section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting without
using V

. This function is one of two provided by the WP#/ACC pin.

If the system asserts V

on the WP#/ACC pin, the device disables program and

erase functions in sectors 0, 1, 140, and 141, independently of whether those
sectors were protected or unprotected using the method described in "Sector/
Sector Block Protection and Unprotection".

If the system asserts V

on the WP#/ACC pin, the device reverts to whether sec-

tors 0, 1, 140, and 141 were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors depends on whether they were
last protected or unprotected using the method described in "Sector/Sector Block
Protection and Unprotection".

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent
behavior of the device may result.

Table 7. WP#/ACC Modes

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Temporary Sector Unprotect mode is activated by
setting the RESET# pin to

. During this mode, formerly protected sectors can

be programmed or erased by selecting the sector addresses. Once V

is removed

from the RESET# pin, all the previously protected sectors are protected again.
shows the algorithm, and 25 shows the timing diagrams, for this feature. If the
WP#/ACC pin is at V

, sectors 0, 1, 140, and 141 will remain protected during

the Temporary sector Unprotect mode.

WP# Input Voltage

Device

Mode

Disables programming and erasing in SA0, SA1, SA140, and SA141

Enables programming and erasing in SA0, SA1, SA140, and SA141, dependent on

whether they were last protected or unprotected.

Enables accelerated progamming (ACC). See "Accelerated Program Operation" on
page 12..

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

SecSiTM (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that
enables permanent part identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator
Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed,
which prevents cloning of a factory locked part. This ensures the security of the
ESN once the product is shipped to the field.

The product is available with the SecSi Sector either factory locked or customer
lockable. The factory-locked version is always protected when shipped from the
factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set
to a "1." The customer-lockable version is shipped with the SecSi Sector unpro-
tected, allowing customers to utilize the that sector in any manner they choose.
The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator
Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents cus-
tomer-lockable devices from being used to replace devices that are factory
locked. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part
has been customer locked, permanently set to 0 if the part has been factory
locked, and is 0 if customer lockable.

The system accesses the SecSi Sector Secure through a command sequence (see
"Enter SecSiTM Sector/Exit SecSi Sector Command Sequence"). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi
Sector by using the addresses normally occupied by the boot sectors. This mode
of operation continues until the system issues the Exit SecSi Sector command se-
quence, or until power is removed from the device. On power-up, or following a
hardware reset, the device reverts to sending commands to the first 256 bytes of
Sector 0. Note that the ACC function and unlock bypass modes are not available
when the SecSi Sector is enabled.

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In a factory locked device, the SecSi Sector is protected when the device is
shipped from the factory. The SecSi Sector cannot be modified in any way. The
device is preprogrammed with both a random number and a secure ESN. The 8-
word random number is at addresses 000000h000007h in word mode (or
000000h00000Fh in byte mode). The secure ESN is programmed in the next 8
words at addresses 000008h00000Fh (or 000010h00001Fh in byte mode). The
device is available preprogrammed with one of the following:

A random, secure ESN only
Customer code through Spansion programming services
Both a random, secure ESN and customer code through Spansion program-

ming services

Contact an your local sales office for details on using Spansion programming
services.

Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector can be treated as an ad-
ditional Flash memory space. The SecSi Sector can be read any number of times,
but can be programmed and locked only once. Note that the accelerated pro-
gramming (ACC) and unlock bypass functions are not available when
programming the SecSi Sector.

March 26, 2004 S29JL064HA1

S29JL064H

P r e l i m i n a r y

The SecSi Sector area can be protected using one of the following procedures:

Write the three-cycle Enter SecSi Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in

Figure 2

, ex-

cept that RESET# may be at either V

or V

. This allows in-system protec-

tion of the SecSi Sector Region without raising any device pin to a high

voltage. Note that this method is only applicable to the SecSi Sector.
To verify the protect/unprotect status of the SecSi Sector, follow the algo-
rithm shown in

Figure 3

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi
Sector Region command sequence to return to reading and writing the remainder
of the array.

The SecSi Sector lock must be used with caution since, once locked, there is no
procedure available for unlocking the SecSi Sector area and none of the bits in
the SecSi Sector memory space can be modified in any way.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table

for command

definitions). In addition, the following hardware data protection measures pre-
vent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during V

power-up and power-down transitions,

or from system noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept any write cycles. This pro-

tects data during V

power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

or V

Wait 1 ms

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,
SecSi Sector is

unprotected.

If data = 01h,
SecSi Sector is

protected.

Remove V

or V

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

S29JL064H

S29JL064HA1 March 26, 2004

P r e l i m i n a r y

mode. Subsequent writes are ignored until V

is greater than V

LKO

. The system

must provide the proper signals to the control pins to prevent unintentional writes
when V

is greater than V

LKO

Write Pulse "Glitch" Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = V

or WE# =

. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = V

during power up, the device does not accept

commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addresses given in Tables 13. To terminate reading CFI data, the system
must write the reset command.The CFI Query mode is not accessible when the
device is executing an Embedded Program or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 13. The system must write the reset
command to reading array data.

For further information, please refer to the CFI Specification and CFI Publication
100. Contact your local sales office for copies of these documents.

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Table 3. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode)

Data

Description

40h
41h

42h

80h
82h

84h

0050h
0052h

0049h

Query-unique ASCII string "PRI"

43h

86h

0031h

Major version number, ASCII (reflects modifications to the silicon)

44h

88h

0033h

Minor version number, ASCII (reflects modifications to the CFI table)

45h

8Ah

000Ch

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)

46h

8Ch

0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h

8Eh

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h

90h

0001h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h

92h

0004h

Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

4Ah

94h

0077h

Simultaneous Operation

00 = Not Supported, X = Number of Sectors (excluding Bank 1)

4Bh

96h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch

98h

0000h

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh

9Ah

0085h

ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh

9Ch

0095h

ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh

9Eh

0001h

Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom

Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot
Device, 04h= Both Top and Bottom

50h

A0h

0001h

Program Suspend
0 = Not supported, 1 = Supported

57h

AEh

0004h

Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks

58h

B0h

0017h

Bank 1 Region Information
X = Number of Sectors in Bank 1

59h

B2h

0030h

Bank 2 Region Information
X = Number of Sectors in Bank 2

5Ah

B4h

0030h

Bank 3 Region Information
X = Number of Sectors in Bank 3

5Bh

B6h

0017h

Bank 4 Region Information
X = Number of Sectors in Bank 4

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Command Definitions

Writing specific address and data commands or sequences into the command
register initiates device operations. Table

defines the valid register command

sequences. Writing incorrect address and data values or writing them in the im-
proper sequence may place the device in an unknown state. A reset command is
then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See the Erase Suspend/Erase Re-
sume Commands section for more information.

The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the next section, Reset
Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations sec-
tion for more information. The Read-Only Operations table provides the read
parameters, and 14 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don't cares for this command.

The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.

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If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in another
bank.

The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the au-
toselect command. The bank then enters the autoselect mode. The system may
read any number of autoselect codes without reinitiating the command sequence.

Table

shows the address and data requirements. To determine sector protection

information, the system must write to the appropriate bank address (BA) and
sector address (SA). Table

shows the address range and bank number associ-

ated with each sector.

The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).

Enter SecSiTM Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area containing a random, six-
teen-byte electronic serial number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi Sector command sequence.
The device continues to access the SecSi Sector region until the system issues
the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal operation. The SecSi Sector is not
accessible when the device is executing an Embedded Program or embedded
Erase algorithm. Table

shows the address and data requirements for both com-

mand se quences. See also "SecSiTM (Secu red Silicon) Sector
Flash Memory Region" for further information. Note that the ACC function and un-
lock bypass modes are not available when the SecSi Sector is enabled.

Byte/Word Program Command Sequence

The system may program the device by word or byte, depending on the state of
the BYTE# pin. Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically provides internally
generated program pulses and verifies the programmed cell margin. Table

shows the address and data requirements for the byte program command
sequence.

When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the
Write Operation Status section for information on these status bits.

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Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the SecSi Sec-
tor, autoselect, and CFI functions are unavailable when a program operation is in
progress.

Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from "0" back to a "1." Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read will show that the data
is still "0." Only erase operations can convert a "0" to a "1."

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to a bank
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle unlock bypass program com-
mand sequence is all that is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required
in the standard program command sequence, resulting in faster total program-
ming time. Table

shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (See Table
12).

The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V

on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at V

for any operation other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result.

4 illustrates the algorithm for the program operation. Refer to the Erase and Pro-
gram Operations table in the AC Characteristics section for parameters, and

Figure 18

for timing diagrams.

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Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table

shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write
Operation Status section for information on these status bits.

Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be reinitiated once that bank
has returned to reading array data, to ensure data integrity. Note that the SecSi
Sector, autoselect, and CFI functions are unavailable when an erase operation is
in progress.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table

for program command sequence.

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5 illustrates the algorithm for the erase operation. Refer to the Erase and Program
Operations tables in the AC Characteristics section for parameters, and

Figure 20

section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table

shows the address

and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 80 µs occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 80 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode. The system must rewrite the com-
mand sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# or CE# pulse (first rising edge) in the command
sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Sta-
tus section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when an erase operation is in progress.

5 illustrates the algorithm for the erase operation. Refer to the Erase and Program
Operations tables in the AC Characteristics section for parameters, and

Figure 20

section for timing diagrams.

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Figure 5. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writing this command. This com-
mand is valid only during the sector erase operation, including the 80 µs time-out
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation or Embedded Program
algorithm. The bank address must contain one of the sectors currently selected
for erase.

When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation.

After the erase operation has been suspended, the bank enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device "erase suspends" all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on these status bits.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

Notes:
1. See Table

for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

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Table 4. S29JL064H Command Definitions

Command

Sequence

(Note 1)

Cycle

Bus Cycles (Notes 25)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

XXX

Auto

s
e
lec

t

(N

e
8

)

Manufacturer ID

Word

555

2AA

(BA)555

(BA)X00

Byte

AAA

555

(BA)AAA

Device ID (Note 9)

Word

555

2AA

(BA)555

(BA)X01

(BA)X0E

(BA)X0F

Byte

AAA

555

(BA)AAA

(BA)X02

(BA)X1C

(BA)X1E

SecSi Sector Factory

Protect (Note 10)

Word

555

2AA

(BA)555

(BA)X03

80/

Byte

AAA

555

(BA)AAA

(BA)X06

Sector/Sector Block

Protect Verify

(Note 11)

Word

555

2AA

(BA)555

(SA)X02

00/

Byte

AAA

555

(BA)AAA

(SA)X04

Enter SecSi Sector Region

Word

555

2AA

555

Byte

AAA

555

AAA

Exit SecSi Sector Region

Word

555

2AA

555

XXX

Byte

AAA

555

AAA

Program

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass

Word

555

2AA

555

Byte

AAA

555

AAA

Unlock Bypass Program (Note 12)

XXX

Unlock Bypass Reset (Note 13)

XXX

Chip Erase

Word

555

2AA

555

2AA

555

Byte

AAA

555

AAA

555

AAA

Sector Erase

Word

555

2AA

555

2AA

Byte

AAA

555

AAA

555

Erase Suspend (Note 14)

Erase Resume (Note 15)

CFI Query (Note )

Word

Byte

Legend:

X = Don't care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21A12 uniquely select any sector. Refer to

Table

for information on sector addresses.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased. A21A19 uniquely select a bank.

Notes:

1. See Table

for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth, fifth, and sixth cycle of

the autoselect command sequence, all bus cycles are write

cycles.

4. Data bits DQ15DQ8 are don't care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A21A11 are don't cares for

unlock and command cycles, unless SA or PA is required.

6. No unlock or command cycles required when bank is reading

array data.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high

(while the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15DQ8 are don't care. While reading

the autoselect addresses, the bank address must be the same

until a reset command is given. See the Autoselect Command

Sequence section for more information.

9. The device ID must be read across the fourth, fifth, and sixth

cycles.

10. The data is 80h for factory locked, 40h for customer locked, and

00h for not factory/customer locked.

11. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

Command is valid when device is ready to read array data or when

device is in autoselect mode.

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Write Operation Status

The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table

and the following subsections

describe the function of these bits. DQ7 and DQ6 each offer a method for deter-
mining whether a program or erase operation is complete or in progress. The
device also provides a hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in progress or has been
completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse
in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15DQ0 (or DQ7DQ0 for x8-only device) on the fol-
lowing read cycles. Just prior to the completion of an Embedded Program or Erase
operation, DQ7 may change asynchronously with DQ15DQ8 (DQ7DQ0 for x8-
only device) while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read the status or valid data.
Even if the device has completed the program or erase operation and DQ7 has
valid data, the data outputs on DQ15DQ0 may be still invalid. Valid data on
DQ15DQ0 (or DQ7DQ0 for x8-only device) will appear on successive read
cycles.

Table

shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling

algorithm. 22 in the AC Characteristics section shows the Data# Polling timing
diagram.

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RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.

Table

shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.

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DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table

to compare outputs for DQ2 and DQ6.

7 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle
Bit II" explains the algorithm. See also the DQ6: Toggle Bit I subsection. 23
shows the toggle bit timing diagram. 24 shows the differences between DQ2 and
DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to 7 for the following discussion. Whenever the system initially begins read-
ing toggle bit status, it must read DQ15DQ0 (or DQ7DQ0 for x8-only device)
at least twice in a row to determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit after the first read. After
the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program
or erase operation. The system can read array data on DQ15DQ0 (or DQ7DQ0
for x8-only device) on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-
cessfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified in-
ternal pulse count limit. Under these conditions DQ5 produces a "1," indicating
that the program or erase cycle was not successfully completed.

The device may output a "1" on DQ5 if the system tries to program a "1" to a
location that was previously programmed to "0." Only an erase operation can
change a "0" back to a "1." Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a "1."

Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not

March 26, 2004 S29JL064HA1

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P r e l i m i n a r y

apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a "0" to a "1." If the
time between additional sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not monitor DQ3. See also the
Sector Erase Command Sequence section.

After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is "0," the device will accept addi-
tional sector erase commands. To ensure the command has been accepted, the
system software should check the status of DQ3 prior to and following each sub-
sequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.

Table

shows the status of DQ3 relative to the other status bits.

Table 9. Write Operation Status

Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

Status

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

RY/BY#

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector

No toggle

N/A

Toggle

Non-Erase
Suspended Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

S29JL064H

S29JL064HA1 March 26, 2004

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Absolute Maximum Ratings

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +150°C
Ambient Temperature

with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +125°C
Voltage with Respect to Ground
V

(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.5 V
WP#/ACC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +10.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+0.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may overshoot V

to 

2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V

+0.5 V. See

Figure 8

. During voltage

transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See

Figure 9

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is 0.5 V. During voltage transitions, A9, OE#, WP#/

ACC, and RESET# may overshoot V

to 2.0 V for periods of up to 20 ns. See

Figure 8

. Maximum DC input voltage on

pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is
+9.5 V which may overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one

second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods
may affect device reliability.

Operating Ranges

Industrial (I) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C

Extended (N) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C

Supply Voltages

for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is
guaranteed.

Figure 8. Maximum Negative

Overshoot Waveform

Figure 9. Maximum Positive

Overshoot Waveform

20 ns

+0.8 V

0.5 V

20 ns

2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

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DC Characteristics

CMOS Compatible

Notes:
1. The I

current listed is typically less than 2 mA/MHz, with OE# at V

2. Maximum I

specifications are tested with V

= V

max.

3. I

active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns. Typical sleep mode

current is 200 nA.

5. Not 100% tested.

Paramete

r Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Input Load Current

= V

to V

= V

max

±1.0

µA

LIT

A9, OE# and RESET# Input Load
Current

= V

CC max

, OE# = V

; A9 or

OE# or RESET# = 12.5 V

µA

Output Leakage Current

OUT

= V

to V

= V

CC max

, OE# = V

±1.0

µA

Reset Leakage Current

= V

CC max

; RESET# =

12.5 V

µA

CC1

Active Read Current

(Notes 1, 2)

CE# = V

OE#

Byte Mode

5 MHz

1 MHz

CE# = V

OE# =

, Word Mode

5 MHz

1 MHz

CC2

Active Write Current (Notes 2,

CE# = V

OE# = V

, WE# = V

CC3

Standby Current (Note 2)

CE#, RESET# = V

± 0.3 V

0.2

µA

CC4

Reset Current (Note 2)

RESET# = V

± 0.3 V

0.2

µA

CC5

Automatic Sleep Mode (Notes 2, 4)

= V

± 0.3 V;

= V

± 0.3 V

0.2

µA

CC6

Active Read-While-Program

Current (Notes 1, 2)

CE# = V

OE# = V

Byte

Word

CC7

Active Read-While-Erase

Current (Notes 1, 2)

CE# = V

, OE# = V

Byte

Word

CC8

Active Program-While-Erase-

Suspended Current (Notes 2, 5)

CE# = V

, OE# = V

Input Low Voltage

0.5

0.8

Input High Voltage

0.7 x V

+ 0.3

Voltage for WP#/ACC Sector
Protect/Unprotect and Program

Acceleration

= 3.0 V ± 10%

8.5

9.5

Voltage for Autoselect and
Temporary Sector Unprotect

= 3.0 V ± 10%

11.5

12.5

Output Low Voltage

= 2.0 mA, V

= V

CC min

0.45

OH1

Output High Voltage

= 2.0 mA, V

= V

CC min

0.85 V

OH2

= 100 µA, V

= V

CC min

0.4

LKO

Low V

Lock-Out Voltage (Note 5)

2.3

2.5

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Erase And Programming Performance

Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V

, 100,000 cycles; checkerboard data

pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table

for further information on command definitions.

6. The device has a minimum cycling endurance of 100,000 cycles per sector.
7. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.

TSOP & BGA Pin Capacitance

Notes:
1. Sampled, not 100% tested.
2. Test conditions T

= 25°C, f = 1.0 MHz.

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.4

sec

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

sec

Byte Program Time

150

µs

Excludes system level

overhead (Note 5)

Accelerated Byte/Word Program Time

120

µs

Accelerated Chip Programming Time

sec

Word Program Time

210

µs

Chip Program Time

(Note 3)

Byte Mode

126

sec

Word Mode

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

= 0

TSOP

7.5

Fine-pitch BGA

4.2

5.0

OUT

Output Capacitance

OUT

= 0

TSOP

8.5

Fine-pitch BGA

5.4

6.5

IN2

Control Pin Capacitance

= 0

TSOP

7.5

Fine-pitch BGA

3.9

4.7

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29JL064H90TAI000