Publication Number S29WS-N_00 Revision G Amendment 0 Issue Date January 25, 2005

General Description

The Spansion S29WS256/128/064N are Mirrorbit

Flash products fabricated on 110 nm process technology. These burst

mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. These products can operate up to 80 MHz and use a single V

1.7 V to 1.95 V that makes them ideal for today's demanding wireless applications requiring higher density, better per-
formance and lowered power consumption.

Distinctive Characteristics

Single 1.8 V read/program/erase (1.701.95 V)
110 nm MirrorBitTM Technology
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8/4
Mwords for WS256N/128N/064N, respectively
Four 16 Kword sectors at both top and bottom of
memory array
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Programmable burst read modes
-- Linear for 32, 16 or 8 words linear read with or

without wrap-around

-- Continuous sequential read mode
SecSiTM (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
RDY output indicates data available to system

Command set compatible with JEDEC (42.4)
standard
Hardware (WP#) protection of top and bottom
sectors
Dual boot sector configuration (top and bottom)
Offered Packages
-- WS064N: 80-ball FBGA (7 mm x 9 mm)
-- WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low V

write inhibit

Persistent and Password methods of Advanced
Sector Protection
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Industrial Temperature range (contact factory)

Performance Characteristics

S29WS-N MirrorBitTM Flash Family

S29WS256N, S29WS128N, S29WS064N

256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only

Simultaneous Read/Write, Burst Mode Flash Memory

Data Sheet

ADVANCE

INFORMATION

Read Access Times

Speed Option (MHz)

Max. Synch. Latency, ns (t

IACC

)

Max. Synch. Burst Access, ns (t

BACC

)

11.2

13.5

Max. Asynch. Access Time, ns (t

ACC

)

Max CE# Access Time, ns (t

)

Max OE# Access Time, ns (t

)

13.5

Current Consumption (typical values)

Continuous Burst Read @ 66 MHz

35 mA

Simultaneous Operation (asynchronous)

50 mA

Program (asynchronous)

19 mA

Erase (asynchronous)

19 mA

Standby Mode (asynchronous)

20 µA

Typical Program & Erase Times

Single Word Programming

40 µs

Effective Write Buffer Programming (V

) Per Word

9.4 µs

Effective Write Buffer Programming (V

ACC

) Per Word

6 µs

Sector Erase (16 Kword Sector)

150 ms

Sector Erase (64 Kword Sector)

600 ms

S29WS-N MirrorBitTM Flash Family

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

Contents

1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Related Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2.1 VBH084--84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 TLC080--80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 MCP Look-ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Synchronous (Burst) Read Mode &

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7.3.3 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.5 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5.1. Single Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.5.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5.7 Accelerated Program/Chip Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5.8 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

7.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.7.1. WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.2 ACC Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.7.3 Low V

Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.7.4 Write Pulse "Glitch Protection" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.7.5 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

January 25, 2005 S29WS-N_00_G0

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9.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

10.1 Factory Secured Silicon

Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10.3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . .61

11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.3 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.6 V

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.8.1. CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.8.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.8.4 AC Characteristics--Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.8.7 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.8.8 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

S29WS-N MirrorBitTM Flash Family

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

Figures

Figure 3.1.

S29WS-N Block Diagram..................................................................................................................... 8

Figure 4.1.

84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N).................................................................10

Figure 4.2.

VBH084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package .........................11

Figure 4.3.

80-ball Fine-Pitch Ball Grid Array (S29WS064N) ....................................................................................12

Figure 4.4.

TLC080--80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package...............................13

Figure 4.5.

MCP Look-ahead Diagram ..................................................................................................................15

Figure 7.1.

Synchronous/Asynchronous State Diagram...........................................................................................21

Figure 7.2.

Synchronous Read ............................................................................................................................23

Figure 7.3.

Single Word Program.........................................................................................................................29

Figure 7.4.

Write Buffer Programming Operation ...................................................................................................33

Figure 7.5.

Sector Erase Operation ......................................................................................................................36

Figure 7.6.

Write Operation Status Flowchart ........................................................................................................43

Figure 8.1.

Advanced Sector Protection/Unprotection .............................................................................................50

Figure 8.2.

PPB Program/Erase Algorithm .............................................................................................................53

Figure 8.3.

Lock Register Program Algorithm.........................................................................................................56

Figure 11.1. Maximum Negative Overshoot Waveform .............................................................................................64
Figure 11.2. Maximum Positive Overshoot Waveform...............................................................................................64
Figure 11.3. Test Setup .......................................................................................................................................64
Figure 11.4. Input Waveforms and Measurement Levels...........................................................................................66
Figure 11.5. V

Power-up Diagram ......................................................................................................................66

Figure 11.6. CLK Characterization .........................................................................................................................68
Figure 11.7. CLK Synchronous Burst Mode Read......................................................................................................70
Figure 11.8. 8-word Linear Burst with Wrap Around.................................................................................................71
Figure 11.9. 8-word Linear Burst without Wrap Around ............................................................................................71
Figure 11.10. Linear Burst with RDY Set One Cycle Before Data ..................................................................................72
Figure 11.11. Asynchronous Mode Read...................................................................................................................73
Figure 11.12. Reset Timings...................................................................................................................................74
Figure 11.13. Chip/Sector Erase Operation Timings ...................................................................................................76
Figure 11.14. Asynchronous Program Operation Timings............................................................................................77
Figure 11.15. Synchronous Program Operation Timings .............................................................................................78
Figure 11.16. Accelerated Unlock Bypass Programming Timing ...................................................................................79
Figure 11.17. Data# Polling Timings (During Embedded Algorithm) .............................................................................79
Figure 11.18. Toggle Bit Timings (During Embedded Algorithm) ..................................................................................80
Figure 11.19. Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................80
Figure 11.20. DQ2 vs. DQ6 ....................................................................................................................................81
Figure 11.21. Latency with Boundary Crossing when Frequency > 66 MHz....................................................................81
Figure 11.22. Latency with Boundary Crossing into Program/Erase Bank ......................................................................82
Figure 11.23. Example of Wait States Insertion ........................................................................................................83
Figure 11.24. Back-to-Back Read/Write Cycle Timings ...............................................................................................84

January 25, 2005 S29WS-N_00_G0

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Tables

Table 2.1. Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6.1. S29WS256N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6.2. S29WS128N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 6.3. S29WS064N Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7.1. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 7.2. Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.3. Address Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.4. Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.5. Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.6. Address/Boundary Crossing Latency (S29WS128N/S29WS064N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7.7. Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.8. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 7.9. Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.10. Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.11. Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.12. Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7.13. Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7.14. Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 7.15. Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 7.16. Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.17. Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.18. Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.19. Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.20. Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.21. Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 7.22. Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 7.23. DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 7.24. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 7.25. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 8.1. Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 8.2. Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 10.1. Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 10.2. Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 10.3. Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 10.4. Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 11.1. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 12.1. Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 12.2. Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12.3. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 12.4. System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 12.5. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 12.6. Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

S29WS-N MirrorBitTM Flash Family

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

1 Ordering

Information

The ordering part number is formed by a valid combination of the following:

S29WS

256

PACKING TYPE
0

= Tray (standard; see note 1)

= 7-inch Tape and Reel

= 13-inch Tape and Reel

MODEL NUMBER (Note 3)

(Package Ball Count, Package Dimensions, DYB Protect/Unprotect After

Power-up)
01

= 84-ball, 8 x 11.6 mm, DYB Unprotect

= 80-ball, 7 x 9 mm, DYB Protect

TEMPERATURE RANGE (Note 3)
W

= Wireless (25°C to +85°C)

I = Industrial

(40°C to +85°C, contact factory for availability)

PACKAGE TYPE AND MATERIAL
BA

= Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package

= Very Thin Fine-Pitch BGA, Lead (Pb)-free Package

SPEED OPTION (BURST FREQUENCY)
0S

= 80 MHz (contact factory for availability)

= 66 MHz

= 54 MHz

PROCESS TECHNOLOGY
N

= 110 nm MirrorBitTM Technology

FLASH DENSITY
256

= 256 Mb

128

= 128 Mb

064

= 64 Mb

DEVICE FAMILY
S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

S29WS-N Valid Combinations (Notes 1, 2, 3)

Range

DYB Power

Up State

Package Type

(Note 2)

Base Ordering

Part Number

Product

Status

Speed

Option

Package Type,

Material, &

Temperature Range

Model

Number

Packing

Type

S29WS256N

Preliminary

0S, 0P, 0L

BAW (Lead (Pb)-free

Compliant),

BFW (Lead (Pb)-free)

0, 2, 3

(Note 1)

1.701.95 V

Unprotect

8 mm x 11.6 mm

84-ball

MCP-Compatible

Protect

S29WS128N

Advance

Unprotect

Protect

S29WS064N

Advance

Unprotect

7 mm x 9 mm

80-ball

MCP-Compatible

Protect

Notes:

1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading "S29" and packing type

designator from ordering part number.

3. For 1.5 V

option, other boot options, or industrial temperature

range, contact your local sales office.

Valid Combinations

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

January 25, 2005 S29WS-N_00_G0

S29WS-N MirrorBitTM Flash Family

A d v a n c e I n f o r m a t i o n

2 Input/Output Descriptions & Logic Symbol

Table identifies the input and output package connections provided on the device.

Table 2.1. Input/Output Descriptions

Symbol

Type

Description

A23A0

Input

Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).

DQ15DQ0

I/O

Data input/output.

CE#

Input

Chip Enable. Asynchronous relative to CLK.

OE#

Input

Output Enable. Asynchronous relative to CLK.

WE#

Input

Write Enable.

Supply

Device Power Supply.

Input

VersatileIO Input. Should be tied to V

I/O

Ground.

No Connect

Not connected internally.

RDY

Output

Ready. Indicates when valid burst data is ready to be read.

CLK

Input

Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK

increment the internal address counter. Should be at V

or V

while in asynchronous

mode.

AVD#

Input

Address Valid. Indicates to device that the valid address is present on the address inputs.

When low during asynchronous mode, indicates valid address; when low during burst

mode, causes starting address to be latched at the next active clock edge.

When high, device ignores address inputs.

RESET#

Input

Hardware Reset. Low = device resets and returns to reading array data.

WP#

Input

Write Protect. At V

, disables program and erase functions in the four outermost sectors.

Should be at V

for all other conditions.

ACC

Input

Acceleration Input. At V

, accelerates programming; automatically places device in

unlock bypass mode. At V

, disables all program and erase functions. Should be at V

for

all other conditions.

RFU

Reserved

Reserved for future use (see MCP look-ahead pinout for use with MCP).

January 25, 2005 S29WS-N_00_G0

S29WS-N MirrorBitTM Flash Family

A d v a n c e I n f o r m a t i o n

4.2.1 VBH084--84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm

Note: BSC is an ANSI standard for Basic Space Centering

Figure 4.2. VBH084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package

3339 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE

VBH 084

JEDEC

N/A

11.60 mm x 8.00 mm NOM

PACKAGE

SYMBOL

MIN

NOM

MAX

NOTE

---

1.00

OVERALL THICKNESS

0.18

---

BALL HEIGHT

0.62

---

0.76

BODY THICKNESS

11.60 BSC.

BODY SIZE

8.00 BSC.

BODY SIZE

8.80 BSC.

BALL FOOTPRINT

7.20 BSC.

BALL FOOTPRINT

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

0.33

---

0.43

BALL DIAMETER

0.80 BSC.

BALL PITCH

SD / SE

0.40 BSC.

SOLDER BALL PLACEMENT

(A2-A9, B10-L10,

DEPOPULATED SOLDER BALLS

M2-M9, B1-L1)

BOTTOM VIEW

TOP VIEW

SIDE VIEW

A1 CORNER

0.05

(2X)

0.05

C A

0.15

0.08 M

0.10 C

0.08

SEATING PLANE

A1 CORNER

INDEX MARK

January 25, 2005 S29WS-N_00_G0

S29WS-N MirrorBitTM Flash Family

A d v a n c e I n f o r m a t i o n

4.2.2 TLC080--80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm

Note: BSC is an ANSI standard for Basic Space Centering

Figure 4.4. TLC080--80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package

3430 \ 16-038.22 \ 10.15.04

PACKAGE

TLC 080

JEDEC

N/A

D x E

9.00 mm x 7.00 mm

PACKAGE

SYMBOL

MIN

NOM

MAX

NOTE

---

1.20

PROFILE

0.17

---

BALL HEIGHT

0.81

---

0.97

BODY THICKNESS

9.00 BSC.

BODY SIZE

7.00 BSC.

BODY SIZE

7.20 BSC.

MATRIX FOOTPRINT

5.60 BSC.

MATRIX FOOTPRINT

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

0.35

0.40

0.45

BALL DIAMETER

0.80 BSC.

BALL PITCH

0.80 BSC

BALL PITCH

SD / SE

0.40 BSC.

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

NOTES:

DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.

ALL DIMENSIONS ARE IN MILLIMETERS.

BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

e REPRESENTS THE SOLDER BALL GRID PITCH.

SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.

N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

0.08

0.20 C

0.15

(2X)

0.15

(2X)

INDEX MARK

TOP VIEW

SIDE VIEW

CORNER

80X

0.15

M C

A B

0.08

PIN A1

CORNER

BOTTOM VIEW

January 25, 2005 S29WS-N_00_G0

S29WS-N MirrorBitTM Flash Family

A d v a n c e I n f o r m a t i o n

Figure 4.5. MCP Look-ahead Diagram

CE#f1

OE#

CE1#s1

DQ0

AVD#

VSSds

WP#

WE#

WP/ACC

LB#s

CE1#ds

A11

RY/BY#ds

CLKds

RESET#ds

VCCds

CE#f2

CLK

A15

A12

A19

A21

A13

A22

A14

A10

A16

A24

DQ6

CE2s1

A20

A23

CE2s2

RESET#f

UB#s

RDY

A18

CE1#s2

A17

VCCs2

DQ1

CREs

DQ15

DQ13

DQ4

DQ3

DQ9

DQ7

VCCs1

VCCf

DQ10

VSS

VCCnds

DQ8

A27

A26

VSS

DQ12

LOCK

or WP#/ACCds

DQ14

DQ5

A25

DQ11

DQ2

or VCCQds

VCCQs1

CE2#ds

VCCf

VSSnds

DNU

N10

Legend:

Data-storage Only

Shared

or NC (not connected)

Flash Shared Only

1st Flash Only

2nd Flash Only

B10

A10

P10

1st RAM Only

2nd RAM Only

RAM Shared Only

DoC Only

NC or ds

96-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

CE#f1

OE#

CE1#s1

DQ0

AVD#

VSSds

WP#

WE#

WP/ACC

LB#s

CE1#ds

A11

RY/BY#ds

CLKds

RESET#ds

VCCds

CE#f2

CLK

A15

A12

A19

A21

A13

A22

A14

A10

A16

A24

DQ6

CE2s1

A20

A23

CE2s2

RESET#f

UB#s

RDY

A18

CE1#s2

A17

VCCs2

DQ1

CREs

DQ15

DQ13

DQ4

DQ3

DQ9

DQ7

VCCs1

VCCf

DQ10

VSS

VCCnds

DQ8

A27

A26

VSS

DQ12

LOCK

or WP#/ACCds

DQ14

DQ5

A25

DQ11

DQ2

or VCCQds

VCCQs1

CE2#ds

VCCf

VSSnds

DNU

N10

Legend:

Data-storage Only

Shared

or NC (not connected)

Flash Shared Only

1st Flash Only

2nd Flash Only

B10

A10

P10

1st RAM Only

2nd RAM Only

RAM Shared Only

DoC Only

NC or ds

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

6 Product

Overview

The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write
burst mode Flash device optimized for today's wireless designs that demand a large storage array,
rich functionality, and low power consumption.

These devices are organized in 16, 8 or 4 Mwords of 16 bits each and are capable of continuous,
synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap
around. These products also offer single word programming or a 32-word buffer for programming
with program/erase and suspend functionality. Additional features include:

Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information.
The Secured Silicon Sector is One Time Programmable.

6.1

Memory Map

The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 6.16.3.

Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005SA017) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000hxxFFFFh.

Table 6.1. S29WS256N Sector & Memory Address Map

Bank

Size

Sector

Count

Sector Size

(KB)

Bank

Sector/

Sector Range

Address Range

Notes

2 MB

SA000

000000h003FFFh

Contains four smaller sectors at

bottom of addressable memory.

SA001

004000h007FFFh

SA002

008000h00BFFFh

SA003

00C000h00FFFFh

128

SA004 to SA018

010000h01FFFFh to 0F0000h0FFFFFh

All 128 KB sectors.

Pattern for sector address range

is xx0000hxxFFFFh.

(see note)

2 MB

128

SA019 to SA034

100000h10FFFFh to 1F0000h1FFFFFh

2 MB

128

SA035 to SA050

200000h20FFFFh to 2F0000h2FFFFFh

2 MB

128

SA051 to SA066

300000h30FFFFh to 3F0000h3FFFFFh

2 MB

128

SA067 to SA082

400000h40FFFFh to 4F0000h4FFFFFh

2 MB

128

SA083 to SA098

500000h50FFFFh to 5F0000h5FFFFFh

2 MB

128

SA099 to SA114

600000h60FFFFh to 6F0000h6FFFFFh

2 MB

128

SA115 to SA130

700000h70FFFFh to 7F0000h7FFFFFh

2 MB

128

SA131 to SA146

800000h80FFFFh to 8F0000h8FFFFFh

2 MB

128

SA147 to SA162

900000h90FFFFh to 9F0000h9FFFFFh

2 MB

128

SA163 to SA178

A00000hA0FFFFh to AF0000hAFFFFFh

2 MB

128

SA179 to SA194

B00000hB0FFFFh to BF0000hBFFFFFh

2 MB

128

SA195 to SA210

C00000hC0FFFFh to CF0000hCFFFFFh

2 MB

128

SA211 to SA226

D00000hD0FFFFh to DF0000hDFFFFFh

2 MB

128

SA227 to SA242

E00000hE0FFFFh to EF0000hEFFFFFh

2 MB

128

SA243 to SA257

F00000hF0FFFFh to FE0000hFEFFFFh

SA258

FF0000hFF3FFFh

Contains four smaller sectors at

top of addressable memory.

SA259

FF4000hFF7FFFh

SA260

FF8000hFFBFFFh

SA261

FFC000hFFFFFFh

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000hxxFFFFh.

Table 6.2. S29WS128N Sector & Memory Address Map

Bank Size

Sector

Count

Sector Size

(KB)

Bank

Sector/

Sector Range

Address Range

Notes

1 MB

SA000

000000h003FFFh

Contains four smaller sectors at

bottom of addressable memory.

SA001

004000h007FFFh

SA002

008000h00BFFFh

SA003

00C000h00FFFFh

128

SA004 to SA010

010000h01FFFFh to 070000h07FFFFh

All 128 KB sectors.

Pattern for sector address range

is xx0000hxxFFFFh.

(see note)

1 MB

128

SA011 to SA018

080000h08FFFFh to 0F0000h0FFFFFh

1 MB

128

SA019 to SA026

100000h10FFFFh to 170000h17FFFFh

1 MB

128

SA027 to SA034

180000h18FFFFh to 1F0000h1FFFFFh

1 MB

128

SA035 to SA042

200000h20FFFFh to 270000h27FFFFh

1 MB

128

SA043 to SA050

280000h28FFFFh to 2F0000h2FFFFFh

1 MB

128

SA051 to SA058

300000h30FFFFh to 370000h37FFFFh

1 MB

128

SA059 to SA066

380000h38FFFFh to 3F0000h3FFFFFh

1 MB

128

SA067 to SA074

400000h40FFFFh to 470000h47FFFFh

1 MB

128

SA075 to SA082

480000h48FFFFh to 4F0000h4FFFFFh

1 MB

128

SA083 to SA090

500000h50FFFFh to 570000h57FFFFh

1 MB

128

SA091 to SA098

580000h58FFFFh to 5F0000h5FFFFFh

1 MB

128

SA099 to SA106

600000h60FFFFh to 670000h67FFFFh

1 MB

128

SA107 to SA114

680000h68FFFFh to 6F0000h6FFFFFh

1 MB

128

SA115 to SA122

700000h70FFFFh to 770000h77FFFFh

1 MB

128

SA123 to SA129

780000h78FFFFh to 7E0000h7EFFFFh

SA130 7F0000h7F3FFFh

Contains four smaller sectors at

top of addressable memory.

SA131

7F4000h7F7FFFh

SA132

7F8000h7FBFFFh

SA133

7FC000h7FFFFFh

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Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA008SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000hxxFFFFh.

Table 6.3. S29WS064N Sector & Memory Address Map

Bank Size

Sector

Count

Sector Size

(KB)

Bank

Sector/

Sector Range

Address Range

Notes

0.5 MB

SA000

000000h003FFFh

Contains four smaller sectors at
bottom of addressable memory.

SA001

004000h007FFFh

SA002

008000h00BFFFh

SA003

00C000h00FFFFh

128

SA004

010000h01FFFFh

All 128 KB sectors.

Pattern for sector address range is

xx0000hxxFFFFh.

(see note)

SA005

020000h02FFFFh

SA006

030000h03FFFFh

0.5 MB

128

SA007SA010

040000h04FFFFh to 070000h07FFFFh

0.5 MB

128

SA011SA014

080000h08FFFFh to 0B0000h0BFFFFh

0.5 MB

128

SA015SA018

0C0000h0CFFFFh to 0F0000h0FFFFFh

0.5 MB

128

SA019SA022

100000h10FFFFh to 130000h13FFFFh

0.5 MB

128

SA023SA026

140000h14FFFFh to 170000h17FFFFh

0.5 MB

128

SA027SA030

180000h18FFFFh to 1B0000h1BFFFFh

0.5 MB

128

SA031SA034

1C0000h1CFFFFh to 1F0000h1FFFFFh

0.5 MB

128

SA035SA038

200000h20FFFFh to 230000h23FFFFh

0.5 MB

128

SA039SA042

240000h24FFFFh to 270000h27FFFFh

0.5 MB

128

SA043SA046

280000h28FFFFh to 2B0000h2BFFFFh

0.5 MB

128

SA047SA050

2C0000h2CFFFFh to 2F0000h2FFFFFh

0.5 MB

128

SA051SA054

300000h30FFFFh to 330000h33FFFFh

0.5 MB

128

SA055SA058

340000h34FFFFh to 370000h37FFFFh

0.5 MB

128

SA059SA062

380000h38FFFFh to 3B0000h3BFFFFh

0.5 MB

128

SA063

3C0000h3CFFFFh

SA064

3D0000h3DFFFFh

SA065

3E0000h3EFFFFh

SA066

3F0000h3F3FFFh

Contains four smaller sectors at top

of addressable memory.

SA067

3F4000h3F7FFFh

SA068

3F8000h3FBFFFh

SA069

3FC000h3FFFFFh

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7 Device

Operations

This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.

Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables

12.1

and

12.2

). The command register itself

does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.

7.1

Device Operation Table

The device must be setup appropriately for each operation.

Table 7.1

describes the required state

of each control pin for any particular operation.

Table 7.1. Device Operations

Legend: L = Logic 0, H = Logic 1, X = Don't Care, I/O = Input/Output.

7.2 Asynchronous

Read

All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.

The device defaults to reading array data asynchronously after device power-up or hardware re-
set. Asynchronous read requires that the CLK signal remain at V

during the entire memory read

operation. To read data from the memory array, the system must first assert a valid address on
A

max

A0, while driving AVD# and CE# to V

. WE# must remain at V

. The rising edge of AVD#

latches the address. The OE# signal must be driven to V

, once AVD# has been driven to V

Operation

CE#

OE#

WE#

Addresses

DQ150

RESET#

CLK

AVD#

Asynchronous Read - Addresses Latched

Addr In

Data Out

Asynchronous Read - Addresses Steady State

Addr In

Data Out

Asynchronous Write

Addr In

I/O

Synchronous Write

Addr In

I/O

Standby (CE#)

HIGH Z

Hardware Reset

HIGH Z

Burst Read Operations (Synchronous)

Load Starting Burst Address

Addr In

Advance Burst to next address with appropriate
Data presented on the Data Bus

Burst

Data Out

Terminate current Burst read cycle

HIGH Z

Terminate current Burst read cycle via RESET#

HIGH Z

Terminate current Burst read cycle and start new
Burst read cycle

Addr In

I/O

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Data is output on A/DQ15-A/DQ0 pins after the access time (t

) has elapsed from the falling

edge of OE#.

7.3

Synchronous (Burst) Read Mode &
Configuration Register

When a series of adjacent addresses needs to be read from the device (in order from lowest to
highest address), the synchronous (or burst read) mode can be used to significantly reduce the
overall time needed for the device to output array data. After an initial access time required for
the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.

The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 7.3.3 and 7.3.4, and 7.3.5.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Register
settings include the number of wait states to insert before the initial word (t

IACC

) of each burst

access, the burst mode in which to operate, and when RDY indicates data is ready to be read.
Prior to entering the burst mode, the system should first determine the configuration register set-
tings (and read the current register settings if desired via the Read Configuration Register
command sequence), and then write the configuration register command sequence. See

Section

7.3.6

Configuration Register

, and

Table 12.1

Memory Array Commands

for further details.

Figure 7.1. Synchronous/Asynchronous State Diagram

The device outputs the initial word subject to the following operational conditions:

IACC

specification: the time from the rising edge of the first clock cycle after addresses

are latched to valid data on the device outputs.
configuration register setting CR13CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that t

IACC

lengthened.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(CR15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(CR15 = 1)

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The device outputs subsequent words t

BACC

after the active edge of each successive clock cycle,

which also increments the internal address counter. The device outputs burst data at this rate sub-
ject to the following operational conditions:

starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-
ble-by-four address incurs the least number of additional wait states that occur after the
initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four
address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: There is a boundary at every 128 words due to the internal architec-
ture of the device. One additional wait state must be inserted when crossing this boundary
if the memory bus is operating at a high clock frequency. Please refer to the tables below.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.

In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.

Tables

7.2

7.6

reflect wait states required for S29WS256/128/064N devices. Refer to the

"Con-

figuration Register"

table (CR11 - CR14) and timing diagrams for more details.

Table 7.2. Address Latency (S29WS256N)

Table 7.3. Address Latency (S29WS128N/S29WS064N)

Table 7.4. Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)

Table 7.5. Address/Boundary Crossing Latency (S29WS256N @ 54MHz)

Word

Wait States

Cycle

x ws

1 ws

x ws

1 ws

x ws

1 ws

Word

Wait States

Cycle

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

Word

Wait States

Cycle

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

Word

Wait States

Cycle

5 ws

1 ws

5 ws

1 ws

5 ws

1 ws

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. Continuous burst mode can also be aborted by asserting AVD# low and providing a new ad-

dress to the device.

If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-
sequent word line is not being programmed or erased, additional latency cycles are required as
reflected by the configuration register table (

Table 7.8

If the address crosses a bank boundary while the subsequent bank is programming or erasing,
the device provides read status information and the clock is ignored. Upon completion of status
read or program or erase operation, the host can restart a burst read operation using a new ad-
dress and AVD# pulse.

7.3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around

In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-
secutive addresses that are determined by the group within which the starting address falls. The
groups are sized according to the number of words read in a single burst sequence for a given
mode (see

Table 7.7

For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device
outputs all words in that burst address group until all word are read, regardless of where the start-
ing address occurs in the address group, and then terminates the burst read.

In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on
the starting address provided to the device, then wrap back to the first address in the selected
address group.

Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no additional wait states are inserted due to boundary crossing.

Table 7.7. Burst Address Groups

7.3.5 8-, 16-, 32-Word Linear Burst without Wrap Around

If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word
burst executes up to the maximum memory address of the selected number of words. The burst
stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected
group.

For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around
is not enabled. The next address to be read requires a new address and AVD# pulse. Note that
in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,
which will incur the additional boundary crossing wait state.

7.3.6 Configuration Register

The configuration register sets various operational parameters associated with burst mode. Upon
power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-
uration register settings are in their default state. The host system should determine the proper
settings for the entire configuration register, and then execute the Set Configuration Register
command sequence, before attempting burst operations. The configuration register is not reset
after deasserting CE#. The Configuration Register can also be read using a command sequence
(see

Table 12.1

). The following list describes the register settings.

Mode

Group Size

Group Address Ranges

8-word

8 words

0-7h, 8-Fh, 10-17h,...

16-word

16 words

0-Fh, 10-1Fh, 20-2Fh,...

32-word

32 words

00-1Fh, 20-3Fh, 40-5Fh,...

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Table 7.8. Configuration Register

Reading the Configuration Table. The configuration register can be read with a four-cycle com-
mand sequence. See

Table 12.1

for sequence details. Once the data has been read from the

configuration register, a software reset command is required to set the device into the correct
state.

7.4 Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-
tion. This mode is primarily intended for programming equipment to automatically match a device
with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-
tem. When verifying sector protection, the sector address must appear on the appropriate highest
order address bits (see

Table 7.9

). The remaining address bits are don't care. The most significant

four bits of the address during the third write cycle selects the bank from which the Autoselect
codes are read by the host. All other banks can be accessed normally for data read without exiting
the Autoselect mode.

To access the Autoselect codes, the host system must issue the Autoselect command.

CR Bit

Function

Settings (Binary)

CR15

Set Device Read

Mode

0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Read Mode (default) Enabled

CR14

Boundary Crossing

54 MHz

66 Mhz

80 MHz

S29WS064N

S29WS128N

N/A

Default value is "0"

S29WS256N

0 = No extra boundary crossing latency

1 = With extra boundary crossing latency (default)

Must be set to "1" greater than 54 MHz.

CR13

Programmable

Wait State

S29WS064N

S29WS128N

011 = Data valid on 5th active CLK edge after addresses

latched

100 = Data valid on 6th active CLK edge after addresses

latched

101 = Data valid on 7th active CLK edge after addresses

latched (default)

110 = Reserved

111 = Reserved

Inserts wait states before initial data is available. Setting

greater number of wait states before initial data reduces

latency after initial data.

(Notes

)

S29WS256N

CR12

S29WS064N

S29WS128N

S29WS256N

CR11

S29WS064N

S29WS128N

S29WS256N

CR10

RDY Polarity

0 = RDY signal active low

1 = RDY signal active high (default)

CR9

Reserved

1 = default

CR8

RDY

0 = RDY active one clock cycle before data

1 = RDY active with data (default)

When CR13-CR11 are set to 000, RDY is active with data

regardless of CR8 setting.

CR7

Reserved

1 = default

CR6

Reserved

1 = default

CR5

Reserved

0 = default

CR4

Reserved

0 = default

CR3

Burst Wrap Around

0 = No Wrap Around Burst

1 = Wrap Around Burst (default)

CR2

CR1

CR0

Burst Length

000 = Continuous (default)

010 = 8-Word Linear Burst

011 = 16-Word Linear Burst

100 = 32-Word Linear Burst

(All other bit settings are reserved)

Notes:

1. Refer to

Tables

7.2

7.6

for wait states requirements.

2. Refer to Synchronous Burst Read timing diagrams
3. Configuration Register is in the default state upon power-up or hardware reset.

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The Autoselect command sequence may be written to an address within a bank that is
either in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing. Autoselect does not support simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).

See

Table 12.1

for command sequence details.

Table 7.9. Autoselect Addresses

Notes:
1. Any offset within the device works.
2. BA = Bank Address. The bank address is required.
3. base = base address.

Description

Address

Read Data

Manufacturer ID

(BA) + 00h

0001h

Device ID, Word 1

(BA) + 01h

227Eh

Device ID, Word 2

(BA) + 0Eh

2230 (WS256N)
2231 (WS128N)
2232 (WS064N)

Device ID, Word 3

(BA) + 0Fh

2200

Indicator Bits
(See Note)

(BA) + 03h

DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled

Sector Block Lock/
Unlock

(SA) + 02h

0001h = Locked, 0000h = Unlocked

Note: For WS128N and WS064, DQ1 and DQ0 are reserved.

Software Functions and Sample Code

Table 7.10. Autoselect Entry

(LLD Function = lld_AutoselectEntryCmd)

Cycle

Operation

Byte Address

Word Address

Data

Unlock Cycle 1

Write

BAxAAAh

BAx555h

0x00AAh

Unlock Cycle 2

Write

BAx555h

BAx2AAh

0x0055h

Autoselect Command

Write

BAxAAAh

BAx555h

0x0090h

Table 7.11. Autoselect Exit

(LLD Function = lld_AutoselectExitCmd)

Cycle

Operation

Byte Address

Word Address

Data

Unlock Cycle 1

Write

base + XXXh

0x00F0h

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7.5 Program/Erase

Operations

These devices are capable of several modes of programming and or erase operations which are
described in detail in the following sections. However, prior to any programming and or erase op-
eration, devices must be setup appropriately as outlined in the configuration register

(

Table 7.8

For any program and or erase operations, including writing command sequences, the system
must drive AVD# and CE# to V

, and OE# to V

when providing an address to the device, and

drive WE# and CE# to V

, and OE# to V

when writing commands or programming data.

Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#.

Note the following:

When the Embedded Program algorithm is complete, the device returns to the read
mode.
The system can determine the status of the program operation by using DQ7 or DQ6.
Refer to the Write Operation Status section for information on these status bits.
A "0" cannot be programmed back to a "1." Attempting to do so causes the device to set
DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding
read shows that the data is still "0." Only erase operations can convert a "0" to a "1."
Any commands written to the device during the Embedded Program Algorithm are ig-
nored except the Program Suspend command.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program op-
eration is in progress.
A hardware reset immediately terminates the program operation and the program com-
mand sequence should be reinitiated once the device has returned to the read mode, to
ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word
programming operation.

7.5.1.

Single Word Programming

Single word programming mode is the simplest method of programming. In this mode, four Flash
command write cycles are used to program an individual Flash address. The data for this pro-
gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all
Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-
gramming. See

Table 12.1

for the required bus cycles and

Figure 7.3

for the flowchart.

When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these
status bits.

During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program
operation is in progress.

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Note: Base = Base Address.

The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User's Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.

/* Example: Program Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (UINT16 *)pa ) = data; /* write data to be programmed */
/* Poll for program completion */

7.5.2 Write Buffer Programming

Write Buffer Programming allows the system to write a maximum of 32 words in one program-
ming operation. This results in a faster effective word programming time than the standard
"word" programming algorithms. The Write Buffer Programming command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer
Load command written at the Sector Address in which programming occurs. At this point, the sys-
tem writes the number of "word locations minus 1" that are loaded into the page buffer at the
Sector Address in which programming occurs. This tells the device how many write buffer ad-
dresses are loaded with data and therefore when to expect the "Program Buffer to Flash" confirm
command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts. (Number loaded = the number of locations to program minus 1. For example,
if the system programs 6 address locations, then 05h should be written to the device.)

The system then writes the starting address/data combination. This starting address is the first
address/data pair to be programmed, and selects the "write-buffer-page" address. All subsequent
address/data pairs must fall within the elected-write-buffer-page.

The "write-buffer-page" is selected by using the addresses A

MAX

- A5.

The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the
write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-
buffer-pages." This also means that Write Buffer Programming cannot be performed across mul-
tiple sectors. If the system attempts to load programming data outside of the selected "write-
buffer-page", the operation ABORTs.)

After writing the Starting Address/Data pair, the system then writes the remaining address/data
pairs into the write buffer.

Note that if a Write Buffer address location is loaded multiple times, the "address/data pair"
counter is decremented for every data load operation. Also, the last data loaded at a location be-
fore the "Program Buffer to Flash" confirm command is programmed into the device. It is the
software's responsibility to comprehend ramifications of loading a write-buffer location more than

Software Functions and Sample Code

Table 7.12. Single Word Program

(LLD Function = lld_ProgramCmd)

Cycle

Operation

Byte Address

Word Address

Data

Unlock Cycle 1

Write

Base + AAAh

Base + 555h

00AAh

Unlock Cycle 2

Write

Base + 554h

Base + 2AAh

0055h

Program Setup

Write

Base + AAAh

Base + 555h

00A0h

Program

Write

Word Address

Data Word

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once. The counter decrements for each data load operation, NOT for each unique write-buffer-
address location. Once the specified number of write buffer locations have been loaded, the sys-
tem must then write the "Program Buffer to Flash" command at the Sector Address. Any other
address/data write combinations abort the Write Buffer Programming operation. The device goes
"busy." The Data Bar polling techniques should be used while monitoring the last address location
loaded into the write buffer. This eliminates the need to store an address in memory because the
system can load the last address location, issue the program confirm command at the last loaded
address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1
should be monitored to determine the device status during Write Buffer Programming.

The write-buffer "embedded" programming operation can be suspended using the standard sus-
pend/resume commands. Upon successful completion of the Write Buffer Programming operation,
the device returns to READ mode.

The Write Buffer Programming Sequence is ABORTED under any of the following conditions:

Load a value that is greater than the page buffer size during the "Number of Locations to
Program" step.
Write to an address in a sector different than the one specified during the Write-Buffer-
Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
"Starting Address" during the "write buffer data loading" stage of the operation.
Write data other than the "Confirm Command" after the specified number of "data load"
cycles.

The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location
loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation
was ABORTED. A "Write-to-Buffer-Abort reset" command sequence is required when using the
write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,
autoselect, and CFI functions are unavailable when a program operation is in progress.

Write buffer programming is allowed in any sequence of memory (or address) locations. These
flash devices are capable of handling multiple write buffer programming operations on the same
write buffer address range without intervening erases.

Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed. Write buffer programming is approximately eight times faster than programming
one word at a time.

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Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of

words written, the total number of cycles may be from 6 to 37.

3. For maximum efficiency, it is recommended that the write buffer be loaded with

the highest number of words (N words) possible.

The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User's Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.

/* Example: Write Buffer Programming Command */
/* NOTES: Write buffer programming limited to 16 words. */
/* All addresses to be written to the flash in */
/* one operation must be within the same flash */
/* page. A flash page begins at addresses */
/* evenly divisible by 0x20. */
UINT16 *src = source_of_data; /* address of source data */
UINT16 *dst = destination_of_data; /* flash destination address */
UINT16 wc = words_to_program -1; /* word count (minus 1) */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */
*( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++; /* increment destination pointer */
src++; /* increment source pointer */
if (wc == 0) goto confirm /* done when word count equals zero */
wc--; /* decrement word count */
goto loop; /* do it again */
confirm:
*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */
/* poll for completion */

/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write buffer abort reset */

Software Functions and Sample Code

Table 7.13. Write Buffer Program

(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Write Buffer Load Command

Write

Program Address

0025h

Write Word Count

Write

Program Address

Word Count (N1)h

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

5 to 36

Load Buffer Word N

Write

Program Address, Word N

Word N

Last

Write Buffer to Flash

Write

Sector Address

0029h

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After the command sequence is written, a sector erase time-out of no less than t

SEA

occurs. Dur-

ing the time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these additional cycles must be less than t

SEA

Any sector erase address and command following the exceeded time-out (t

SEA

) may or may not

be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period
resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase
timer has timed out (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the
rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the
system can read data from the non-erasing banks. The system can determine the status of the
erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to "Write Operation Sta-
tus" for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once that
bank has returned to reading array data, to ensure data integrity.

Figure

7.5

illustrates the algorithm for the erase operation. Refer to the "Erase/Program Opera-

tions" section for parameters and timing diagrams.

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7.5.4 Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by

Table 12.1

. These commands invoke the

Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these oper-
ations. The "Command Definition" section in the appendix shows the address and data
requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to "Write Operation Status" for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.

The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.

/* Example: Chip Erase Command */
/* Note: Cannot be suspended */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */

7.5.5 Erase Suspend/Erase Resume Commands

When the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation. The Erase Suspend
command allows the system to interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the min-
imum t

SEA

time-out period during the sector erase command sequence. The Erase Suspend

command is ignored if written during the chip erase operation.

When the Erase Suspend command is written after the t

SEA

time-out period has expired and dur-

ing the sector erase operation, the device requires a maximum of t

ESL

(erase suspend latency) to

suspend the erase operation.

Software Functions and Sample Code

Table 7.15. Chip Erase

(LLD Function = lld_ChipEraseCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Setup Command

Write

Base + AAAh

Base + 555h

0080h

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Chip Erase Command

Write

Base + AAAh

Base + 555h

0010h

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After the erase operation has been suspended, the bank enters the erase-suspend-read mode.
The system can read data from or program data to any sector not selected for erasure. (The de-
vice "erase suspends" all sectors selected for erasure.) Reading at any address within erase-
suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,
and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to

Table

7.24

for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-
read mode. The system can determine the status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.

In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.
Refer to the "Write Buffer Programming Operation" section and the "Autoselect Command Se-
quence" section for details.

To resume the sector erase operation, the system must write the Erase Resume command. The
bank address of the erase-suspended bank is required when writing this command. Further writes
of the Resume command are ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.

/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */

The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.

/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */
/* The flash needs adequate time in the resume state */

7.5.6 Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming op-
eration or a "Write to Buffer" programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming pro-
cess, the device halts the programming operation within t

PSL

(program suspend latency) and

updates the status bits. Addresses are "don't-cares" when writing the Program Suspend
command.

Software Functions and Sample Code

Table 7.16. Erase Suspend

(LLD Function = lld_EraseSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

Write

Bank Address

00B0h

Table 7.17. Erase Resume

(LLD Function = lld_EraseResumeCmd)

Cycle

Operation

Byte Address

Word Address

Data

Write

Bank Address

0030h

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After the programming operation has been suspended, the system can read array data from any
non-suspended sector. The Program Suspend command may also be issued during a program-
ming operation while an erase is suspended. In this case, data may be read from any addresses
not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.

The system may also write the Autoselect command sequence when the device is in Program Sus-
pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes
are not stored in the memory array. When the device exits the Autoselect mode, the device re-
verts to Program Suspend mode, and is ready for another valid operation. See "Autoselect
Command Sequence" for more information.

After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See "Write Operation Status" for more information.

The system must write the Program Resume command (address bits are "don't care") to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the de-
vice has resumed programming.

The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.

/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */

The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.

/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */

7.5.7 Accelerated Program/Chip Erase

Accelerated single word programming, write buffer programming, sector erase, and chip erase
operations are enabled through the ACC function. This method is faster than the standard chip
program and erase command sequences.

The accelerated chip program and erase functions must not be used more than 10 times
per sector. In addition, accelerated chip program and erase should be performed at room tem-
perature (25

C).

Software Functions and Sample Code

Table 7.18. Program Suspend

(LLD Function = lld_ProgramSuspendCmd)

Cycle

Operation

Byte Address

Word Address

Data

Write

Bank Address

00B0h

Table 7.19. Program Resume

(LLD Function = lld_ProgramResumeCmd)

Cycle

Operation

Byte Address

Word Address

Data

Write

Bank Address

0030h

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If the system asserts V

on this input, the device automatically enters the aforementioned Un-

lock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used
to reset the device. Removing V

from the ACC input, upon completion of the embedded pro-

gram or erase operation, returns the device to normal operation.

Sectors must be unlocked prior to raising ACC to V

The ACC pin must not be at V

for operations other than accelerated programming and

accelerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
ACC locks all sector if set to V

; ACC should be set to V

for all other conditions.

7.5.8 Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster word programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead
of the normal four cycles.

This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. The "Command Definition Summary" sec-
tion shows the requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the bank address and the data 90h.
The second cycle need only contain the data 00h. The bank then returns to the read mode.

The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.

/* Example: Unlock Bypass Entry Command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */
/* At this point, programming only takes two write cycles. */
/* Once you enter Unlock Bypass Mode, do a series of like */
/* operations (programming or sector erase) and then exit */
/* Unlock Bypass Mode before beginning a different type of */
/* operations. */

Software Functions and Sample Code

Table 7.20. Unlock Bypass Entry

(LLD Function = lld_UnlockBypassEntryCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Unlock

Write

Base + AAAh

Base + 555h

00AAh

Unlock

Write

Base + 554h

Base + 2AAh

0055h

Entry Command

Write

Base + AAAh

Base + 555h

0020h

Table 7.21. Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Program Setup Command

Write

Base + xxxh

Base +xxxh

00A0h

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/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (UINT16 *)pa ) = data; /* write data to be programmed */
/* Poll until done or error. */
/* If done and more to program, */
/* do above two cycles again. */

/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

7.5.9 Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.

DQ7: Data# Polling.

The Data# Polling bit, DQ7, indicates to the host system whether an Em-

bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately t

PSP

, then that bank returns to the read mode.

During the Embedded Erase Algorithm, Data# polling produces a "0" on DQ7. When the Embed-
ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling
produces a "1" on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately t

ASP

, then the bank returns to the read mode.

If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it may read the status or valid data. Even if the device has completed

Program Command

Write

Program Address

Program Data

Table 7.22. Unlock Bypass Reset

(LLD Function = lld_UnlockBypassResetCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

Reset Cycle 1

Write

Base + xxxh

Base +xxxh

0090h

Reset Cycle 2

Write

Base + xxxh

Base +xxxh

0000h

Table 7.21. Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle

Description

Operation

Byte Address

Word Address

Data

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DQ6: Toggle Bit I .

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-

rithm is in progress or complete, or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of
the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-
ing the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately t

ASP

[all sectors protected toggle time], then returns to reading array

data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately t

PAP

after the

program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program Algorithm is complete.

See the following for additional information:

Figure 7.6

Write Operation Status Flowchart

;

Figure

11.18

Toggle Bit Timings (During Embedded Algorithm)

, and

Tables

7.23

and

7.24

Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.

DQ2: Toggle Bit II .

The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a par-

ticular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse
in the command sequence. DQ2 toggles when the system reads at addresses within those sectors
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to

Table 7.23

to compare

outputs for DQ2 and DQ6. See the following for additional information:

Figure 7.6

, the "DQ6: Tog-

gle Bit I" section, and

Figures

11.17

11.20

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Table 7.23. DQ6 and DQ2 Indications

Reading Toggle Bits DQ6/DQ2.

Whenever the system initially begins reading toggle bit status,

it must read DQ7DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typ-
ically, the system would note and store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erases operation. The system can
read array data on DQ7DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-
mine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just
as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erases operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data. The
remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5
has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-
sive read cycles, determining the status as described in the previous paragraph. Alternatively, it
may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation. Refer to

Figure 7.6

for

more details.

DQ5: Exceeded Timing Limits.

DQ5 indicates whether the program or erase time has exceeded

a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that
the program or erase cycle was not successfully completed. The device may output a "1" on DQ5
if the system tries to program a "1" to a location that was previously programmed to "0." Only an
erase operation can change a "0" back to a "1." Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a "1."Under both these
conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timeout State Indicator.

After writing a sector erase command sequence,

the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase
commands from the system can be assumed to be less than t

SEA

, the system need not monitor

DQ3. See Sector Erase Command Sequence for more details.

After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and

If device is

and the system reads

then DQ6

and DQ2

programming,

at any address,

toggles,

does not toggle.

actively erasing,

at an address within a sector

selected for erasure,

toggles,

also toggles.

at an address within sectors not

selected for erasure,

toggles,

does not toggle.

erase suspended,

at an address within a sector

selected for erasure,

does not toggle,

toggles.

at an address within sectors not

selected for erasure,

returns array data,

returns array data. The system can

read from any sector not selected for

erasure.

programming in

erase suspend

at any address,

toggles,

is not applicable.

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then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted.

Table 7.24

shows the status of DQ3 relative to the other status bits.

DQ1: Write to Buffer Abort.

DQ1 indicates whether a Write to Buffer operation was aborted.

Under these conditions DQ1 produces a "1". The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Program-
ming Operation for more details.

Table 7.24. Write Operation Status

Notes:

1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming

indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.

Status

DQ7

(Note 2)

DQ6

DQ5

(Note 1)

DQ3

DQ2

(Note 2)

DQ1

(Note 4)

Standard

Mode

Embedded Program Algorithm

DQ7#

Toggle

N/A

No toggle

Embedded Erase Algorithm

Toggle

N/A

Program
Suspend

Mode

(Note 3)

Reading within Program Suspended Sector

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

Reading within Non-Program Suspended
Sector

Data

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase
Suspended Sector

No toggle

N/A

Toggle

N/A

Non-Erase Suspended
Sector

Data

Erase-Suspend-Program

DQ7#

Toggle

N/A

Write to

Buffer

(Note 5)

BUSY State

DQ7#

Toggle

N/A

Exceeded Timing Limits

DQ7#

Toggle

N/A

ABORT State

DQ7#

Toggle

N/A

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7.6 Simultaneous

Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of mem-
ory while programming or erasing another bank of memory. An erase operation may also be
suspended to read from or program another location within the same bank (except the sector
being erased).

Figure 11.24

Back-to-Back Read/Write Cycle Timings

, shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the

DC Character-

istics (CMOS Compatible)

table for read-while-program and read-while-erase current

specification.

7.7 Writing

Commands/Command

Sequences

When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able
to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address
latches are supported in the Synchronous programming mode. During a synchronous write oper-
ation, to write a command or command sequence (which includes programming data to the
device and erasing sectors of memory), the system must drive AVD# and CE# to V

, and OE#

to V

when providing an address to the device, and drive WE# and CE# to V

, and OE# to V

when writing commands or data. During an asynchronous write operation, the system must drive
CE# and WE# to V

and OE# to V

when providing an address, command, and data. Addresses

are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of
WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.

Tables

6.1

6.3

indicate the address space that each sector occupies. The device address space is

divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and
15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A "bank address" is the
set of address bits required to uniquely select a bank. Similarly, a "sector address" is the address
bits required to uniquely select a sector. I

CC2

in "DC Characteristics" represents the active current

specification for the write mode. "AC Characteristics-Synchronous" and "AC Characteristics-Asyn-
chronous" contain timing specification tables and timing diagrams for write operations.

7.8 Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply
monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.

When the device is configured to operate in synchronous mode, and OE# is low (active), the initial
word of burst data becomes available after either the falling or rising edge of the RDY pin (de-
pending on the setting for bit 10 in the Configuration Register). It is recommended that the host
system set CR13CR11 in the Configuration Register to the appropriate number of wait states to
ensure optimal burst mode operation (see

Table 7.8

Configuration Register

Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.

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7.9 Hardware

Reset

The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t

, the device immediately terminates any

To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.

When RESET# is held at V

, the device draws CMOS standby current (I

CC4

). If RESET# is held

at V

, but not at V

, the standby current is greater.

RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.

See

Figures

11.5

and

11.12

for timing diagrams.

7.10 Software

Reset

Software reset is part of the command set (see

Table 12.1

) that also returns the device to array

read mode and must be used for the following conditions:

to exit Autoselect mode

when DQ5 goes high during write status operation that indicates program or erase cycle
was not successfully completed

exit sector lock/unlock operation.

to return to erase-suspend-read mode if the device was previously in Erase Suspend
mode.

after any aborted operations

Note: Base = Base Address.

The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.

/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

The following are additional points to consider when using the reset command:

This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is
complete
The reset command may be written between the cycles in a program command sequence
before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode.

Software Functions and Sample Code

Table 7.25. Reset

(LLD Function = lld_ResetCmd)

Cycle

Operation

Byte Address

Word Address

Data

Reset Command

Write

Base + xxxh

00F0h

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8 Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase
operations in any or all sectors and can be implemented through software and/or hardware meth-
ods, which are independent of each other. This section describes the various methods of
protecting data stored in the memory array. An overview of these methods in shown in

Figure 8.1

Figure 8.1. Advanced Sector Protection/Unprotection

Hardware Methods

Software Methods

ACC = V

(

All sectors locked)

WP# = V

(All boot

sectors locked)

Password Method

(DQ2)

Persistent Method

(DQ1)

Lock Register

(One Time Programmable)

PPB Lock Bit

1,2,3

64-bit Password

(One Time Protect)

1 = PPBs Unlocked

0 = PPBs Locked

Memory Array

Sector 0

Sector 1

Sector 2

Sector N-2

Sector N-1

Sector N

PPB 0

PPB 1

PPB 2

PPB N-2

PPB N-1

PPB N

Persistent

Protection Bit

(PPB)

4,5

DYB 0

DYB 1

DYB 2

DYB N-2

DYB N-1

DYB N

Dynamic

Protection Bit

(PPB)

6,7,8

6. 0 = Sector Protected,

1 = Sector Unprotected.

7. Protect effective only if PPB Lock Bit

is unlocked and corresponding PPB
is "1" (unprotected).

8. Volatile Bits: defaults to user choice

upon power-up (see ordering
options).

4. 0 = Sector Protected,

1 = Sector Unprotected.

5. PPBs programmed individually,

but cleared collectively

1. Bit is volatile, and defaults to "1" on

reset.

2. Programming to "0" locks all PPBs to

their current state.

3. Once programmed to "0", requires

hardware reset to unlock.

3. N = Highest Address Sector.

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8.1

Lock Register

As shipped from the factory, all devices default to the persistent mode when power is applied, and
all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see

Or-

dering Information

). The device programmer or host system must then choose which sector

protection method to use. Programming (setting to "0") any one of the following two one-time
programmable, non-volatile bits locks the part permanently in that mode:

Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)

Table 8.1. Lock Register

For programming lock register bits refer to

Table 12.2

Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-

responding lock register bit.

2. After the Lock Register Bits Command Set Entry command sequence is written, reads and

writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.

3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation

aborts.

4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently

disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.

After selecting a sector protection method, each sector can operate in any of the following three
states:

Constantly locked. The selected sectors are protected and can not be reprogrammed
unless PPB lock bit is cleared via a password, hardware reset, or power cycle.

Dynamically locked. The selected sectors are protected and can be altered via software
commands.

3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 8.28.6.

8.2 Persistent

Protection

Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-
durances as the Flash memory. Preprogramming and verification prior to erasure are handled by
the device, and therefore do not require system monitoring.

Notes
1.

Each PPB is individually programmed and all are erased in parallel.

While programming PPB for a sector, array data can be read from any other bank, ex-
cept Bank 0 (used for Data# Polling) and the bank in which sector PPB is being
programmed.

Device

DQ15-05 DQ4

DQ3

DQ2

DQ1

DQ0

S29WS256N

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

Customer

SecSi Sector

Protection Bit

S29WS128N/

S29WS064N

Undefined

DYB Lock Boot Bit

0 = sectors

power up

protected

1 = sectors

power up

unprotected

PPB One-Time

Programmable Bit

0 = All PPB erase

command disabled

1 = All PPB Erase

command enabled

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

SecSi Sector

Protection Bit

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Notes
1.

The DYBs can be set (programmed to "0") or cleared (erased to "1") as often as needed.

When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset,
the DYBs can be set or cleared depending upon the ordering option chosen.

If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectors
may be modified depending upon the PPB state of that sector (see

Table 8.2

The sectors would be in the protected state If the option to set the DYBs after power up
is chosen (programmed to "0").

It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.

The DYB Set or Clear commands for the dynamic sectors signify protected or unpro-
tectedstate of the sectors respectively. However, if there is a need to change the status
of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit
must be cleared by either putting the device through a power-cycle, or hardware reset.
The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit
once again locks the PPBs, and the device operates normally again.

To achieve the best protection, it is recommended to execute the PPB Lock Bit Set com-
mand early in the boot code and protect the boot code by holding WP# = V

. Note that

the PPB and DYB bits have the same function when ACC = V

as they do when ACC

8.4 Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed
to "0"), it locks all PPBs and when cleared (programmed to "1"), allows the PPBs to be changed.
There is only one PPB Lock Bit per device.

Notes
1.

No software command sequence unlocks this bit unless the device is in the password
protection mode; only a hardware reset or a power-up clears this bit.

The PPB Lock Bit must be set (programmed to "0") only after all PPBs are configured to
the desired settings.

8.5 Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector
Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition
to this password requirement, after power up and reset, the PPB Lock Bit is set "0" to maintain
the password mode of operation. Successful execution of the Password Unlock command by en-
tering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

Notes
1.

There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to
prevent access.

The Password Program Command is only capable of programming "0"s. Programming a
"1" after a cell is programmed as a "0" results in a time-out with the cell as a "0".

The password is all "1"s when shipped from the factory.

All 64-bit password combinations are valid as a password.

There is no means to verify what the password is after it is set.

The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the
data bus and further password programming.

The Password Mode Lock Bit is not erasable.

The lower two address bits (A1A0) are valid during the Password Read, Password Pro-
gram, and Password Unlock.

The exact password must be entered in order for the unlocking function to occur.

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8.6 Advanced Sector Protection Software Examples

Table 8.2

contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-

tus of the sector. In summary, if the PPB Lock Bit is locked (set to "0"), no changes to the PPBs
are allowed. The PPB Lock Bit can only be unlocked (reset to "1") through a hardware reset or
power cycle. See also

Figure 8.1

for an overview of the Advanced Sector Protection feature.

8.7

Hardware Data Protection Methods

The device offers two main types of data protection at the sector level via hardware control:

When WP# is at V

, the four outermost sectors are locked (device specific).

When ACC is at V

, all sectors are locked.

There are additional methods by which intended or accidental erasure of any sectors can be pre-
vented via hardware means. The following subsections describes these methods:

8.7.1.

WP# Method

The Write Protect feature provides a hardware method of protecting the four outermost sectors.
This function is provided by the WP# pin and overrides the previously discussed Sector Protec-
tion/Unprotection method.

If the system asserts V

on the WP# pin, the device disables program and erase functions in the

"outermost" boot sectors. The outermost boot sectors are the sectors containing both the lower
and upper set of sectors in a dual-boot-configured device.

If the system asserts V

on the WP# pin, the device reverts to whether the boot sectors were

last set to be protected or unprotected. That is, sector protection or unprotection for these sectors
depends on whether they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the
device may result.

The WP# pin must be held stable during a command sequence execution

8.7.2 ACC Method

This method is similar to above, except it protects all sectors. Once ACC input is set to V

, all

program and erase functions are disabled and hence all sectors are protected.

8.7.3 Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept any write cycles. This protects data during

power-up and power-down.

Table 8.2. Sector Protection Schemes

Unique Device PPB Lock Bit

0 = locked

1 = unlocked

Sector PPB

0 = protected

1 = unprotected

Sector DYB

0 = protected

1 = unprotected

Sector Protection Status

Any Sector

Protected through PPB

Any Sector

Protected through PPB

Any Sector

Unprotected

Any Sector

Protected through DYB

Any Sector

Protected through PPB

Any Sector

Protected through PPB

Any Sector

Protected through DYB

Any Sector

Unprotected

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9 Power Conservation Modes

9.1

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at V

± 0.2 V. The device requires standard

access time (t

) for read access, before it is ready to read data. If the device is deselected during

erasure or programming, the device draws active current until the operation is completed. I

CC3

"DC Characteristics" represents the standby current specification

9.2 Automatic

Sleep

Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t

ACC

+ 20

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the auto-
matic sleep mode is disabled. Note that a new burst operation is required to provide new data.
I

CC6

in "DC Characteristics" represents the automatic sleep mode current specification.

9.3

Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t

, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.

When RESET# is held at V

± 0.2 V, the device draws CMOS standby current (I

CC4

). If RESET#

is held at V

but not within V

± 0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

9.4 Output

Disable

(OE#)

When the OE# input is at V

, output from the device is disabled. The outputs are placed in the

high impedance state.

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10 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words
in length that consists of 128 words for factory data and 128 words for customer-secured areas.
All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Se-
cured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6)
is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped
from the factory.

Please note the following general conditions:

While Secured Silicon Sector access is enabled, simultaneous operations are allowed ex-
cept for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to
the normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within Secured Silicon Sector wrap from address FFh back to address
00h.
Reads outside of sector 0 return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit
command must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded
Program or Embedded Erase algorithm.

Table 10.1. Secured Silicon Sector Addresses

10.1

Factory Secured Silicon

Sector

The Factory Secured Silicon Sector is always protected when shipped from the factory and has
the Factory Indicator Bit (DQ7) permanently set to a "1". This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the
field.

These devices are available pre programmed with one of the following:

A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
Customer code within the Customer Secured Silicon Sector through the Spansion

pro-

gramming service.
Both a random, secure ESN and customer code through the Spansion programming ser-
vice.

Customers may opt to have their code programmed through the Spansion programming services.
Spansion programs the customer's code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured
Silicon Sector permanently locked. Contact your local representative for details on using Spansion
programming services.

Sector

Sector Size

Address Range

Customer

128 words

000080h-0000FFh

Factory

128 words

000000h-00007Fh

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10.2 Customer Secured Silicon Sector

The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to "0"), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer Secured Silicon Sector can be treated as an additional Flash memory space.

Please note the following:

Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit
is permanently set to "1."
The Customer Secured Silicon Sector can be read any number of times, but can be pro-
grammed and locked only once. The Customer Secured Silicon Sector lock must be used
with caution as once locked, there is no procedure available for unlocking the Customer
Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector
memory space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when
programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is
available.
Once the Customer Secured Silicon Sector is locked and verified, the system must write
the Exit Secured Silicon Sector Region command sequence which return the device to the
memory array at sector 0.

10.3 Secured Silicon Sector Entry and Secured Silicon Sector

Exit Command Sequences

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured
Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-
gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.

See Command Definition Table [Secured Silicon Sector Command Table, Appendix

Table 12.1

for address and data requirements for both command sequences.

The Secured Silicon Sector Entry Command allows the following commands to be executed

Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector

After the system has written the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the
memory array. This mode of operation continues until the system issues the Exit Secured Silicon
Sector command sequence, or until power is removed from the device.

The following are C functions and source code examples of using the Secured Silicon Sector
Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User's Guide
(available soon on www.amd.com and www.fujitsu.com) for general information on Spansion
Flash memory software development guidelines.

Note: Base = Base Address.

Software Functions and Sample Code

Table 10.2. Secured Silicon Sector Entry

(LLD Function = lld_SecSiSectorEntryCmd)

Cycle

Operation

Byte Address

Word Address

Data

Unlock Cycle 1

Write

Base + AAAh

Base + 555h

00AAh

Unlock Cycle 2

Write

Base + 554h

Base + 2AAh

0055h

Entry Cycle

Write

Base + AAAh

Base + 555h

0088h

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11 Electrical

Specifications

11.1

Absolute Maximum Ratings

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V

+ 0.5 V

(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +2.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +2.5 V

ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1.

Minimum DC voltage on input or I/Os is 0.5 V. During voltage transitions, inputs or
I/Os may undershoot V

to 2.0 V for periods of up to 20 ns. See

Figure 11.1

Maximum DC voltage on input or I/Os is V

+ 0.5 V. During voltage transitions

outputs may overshoot to V

+ 2.0 V for periods up to 20 ns. See

Figure 11.2

Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot V

to 2.0 V for periods of up to 20 ns. See

Figure 11.1

. Maximum DC

voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.

No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.

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11.7 DC Characteristics (CMOS Compatible)

Notes:
1. Maximum I

specifications are tested with V

= V

max.

2. V

= V

3. CE# must be set high when measuring the RDY pin.
4. The I

current listed is typically less than 3 mA/MHz, with OE# at V

5. I

active while Embedded Erase or Embedded Program is in progress.

6. Device enters automatic sleep mode when addresses are stable for t

ACC

+ 20 ns.

Typical sleep mode current is equal to I

CC3

7. V

= V

± 0.2 V and V

> 0.1 V.

8. Total current during accelerated programming is the sum of V

ACC

and V

currents.

9. V

ACC

= V

on ACC input.

10.The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Parameter

Description (Notes)

Test Conditions (Notes 1, 2, 9)

Min

Typ

Max

Unit

Input Load Current

= V

to V

, V

= V

max

±1

µA

Output Leakage Current (3)

OUT

= V

to V

, V

= V

max

±1

µA

CCB

Active burst Read Current

CE# = V

, OE# = V

, WE#

= V

, burst length = 8

54 MHz

66 MHz

80 MHz

CE# = V

, OE# = V

, WE#

= V

, burst length = 16

54 MHz

66 MHz

80 MHz

CE# = V

, OE# = V

, WE#

= V

, burst length = 32

54 MHz

66 MHz

80 MHz

CE# = V

, OE# = V

, WE#

= V

, burst length =

Continuous

54 MHz

66 MHz

80 MHz

IO1

Non-active Output

OE# = V

µA

CC1

Active Asynchronous

Read Current (4)

CE# = V

, OE# = V

, WE#

= V

10 MHz

5 MHz

1 MHz

CC2

Active Write Current (5)

CE# = V

, OE# = V

, ACC

= V

ACC

µA

52.5

CC3

Standby Current (6, 7)

CE# = RESET# =

± 0.2 V

ACC

µA

CC4

Reset Current (7)

RESET# = V

IL,

CLK = V

150

µA

CC5

Active Current

(Read While Write) (7)

CE# = V

, OE# = V

, ACC = V

5 MHz

CC6

Sleep Current (7)

CE# = V

, OE# = V

µA

ACC

Accelerated Program Current (8)

CE# = V

, OE# = V

IH,

ACC

= 9.5 V

ACC

Input Low Voltage

= 1.8 V

0.5

0.4

Input High Voltage

= 1.8 V

0.4

+ 0.4

Output Low Voltage

= 100 µA, V

= V

min

= V

0.1

Output High Voltage

= 100 µA, V

= V

min

= V

0.1

Voltage for Accelerated Program

8.5

9.5

LKO

Low V

Lock-out Voltage

1.0

1.4

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven

cycles.

2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated

by RDY.

3. The device is in synchronous mode with wrap around.
4. D8DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure

is the 4th address in range (0-F).

Figure 11.8. 8-word Linear Burst with Wrap Around

Notes:

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven

cycles. Clock is set for active rising edge.

2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated

by RDY.

3. The device is in asynchronous mode with out wrap around.
4. DCD13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure

is the 1st address in range (c-13).

Figure 11.9. 8-word Linear Burst without Wrap Around

OE#

Data

Addresses

AVD#

RDY

CLK

CE#

CES

ACS

AVC

AVD

ACH

IACC

AOE

BDH

7 cycles for initial access shown.

Hi-Z

RACC

RDYS

BACC

RACC

OE#

Data

Addresses

AVD#

RDY

CLK

CE#

CES

ACS

AVC

AVD

ACH

IACC

BDH

D13

Hi-Z

RACC

RDYS

BACC

D10

RACC

AOE

7 cycles for initial access shown.

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

11.8.6 Erase/Program Timing

Notes:

1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and

Synchronous program operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,

addresses are latched on the rising edge of CLK.

4. See the

"Erase and Programming Performance"

section for more information.

5. Does not include the preprogramming time.
6. The content in this document is Advance information for the S29WS064N and S29WS128N. Content in this document is Preliminary for the

S29W256N.

Parameter

Description

54 MHz

66 MHz

80 MHz

Unit

JEDEC

Standard

AVAV

Write Cycle Time (Note 1)

Min

AVWL

Address Setup Time (Notes 2, 3)

Synchronous

Min

Asynchronous

WLAX

Address Hold Time (Notes 2, 3)

Synchronous

Min

Asynchronous

AVDP

AVD# Low Time

Min

DVWH

Data Setup Time

Min

WHDX

Data Hold Time

Min

GHWL

Read Recovery Time Before Write

Min

CAS

CE# Setup Time to AVD#

Min

WHEH

CE# Hold Time

Min

WLWH

Write Pulse Width

Min

WHWL

WPH

Write Pulse Width High

Min

SR/W

Latency Between Read and Write Operations

Min

VID

ACC

Rise and Fall Time

Min

500

VIDS

ACC

Setup Time (During Accelerated Programming)

Min

µs

VCS

Setup Time

Min

µs

ELWL

CE# Setup Time to WE#

Min

AVSW

AVD# Setup Time to WE#

Min

AVHW

AVD# Hold Time to WE#

Min

AVSC

AVD# Setup Time to CLK

Min

AVHC

AVD# Hold Time to CLK

Min

CSW

Clock Setup Time to WE#

Min

WEP

Noise Pulse Margin on WE#

Max

SEA

Sector Erase Accept Time-out

Max

µs

ESL

Erase Suspend Latency

Max

µs

PSL

Program Suspend Latency

Max

µs

ASP

Toggle Time During Sector Protection

Typ

100

µs

PSP

Toggle Time During Programming Within a Protected Sector

Typ

µs

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

11.8.7 Erase and Programming Performance

Notes:
1.

Typical program and erase times assume the following conditions: 25°C, 1.8 V V

, 10,000

cycles; checkerboard data pattern.

2. Under worst case conditions of 90°C, V

= 1.70 V, 100,000 cycles.

3. Typical chip programming time is considerably less than the maximum chip programming

time listed, and is based on utilizing the Write Buffer.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed

to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence

for the program command. See the

Appendix

for further information on command

definitions.

6. Contact the local sales office for minimum cycling endurance values in specific applications

and operating conditions.

7. Refer to Application Note "Erase Suspend/Resume Timing" for more details.
8. Word programming specification is based upon a single word programming operation not

utilizing the write buffer.

9. The content in this document is Advance information for the S29WS064N and S29WS128N.

Content in this document is Preliminary for the S29W256N.

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

64 Kword

0.6

3.5

Excludes 00h
programming prior
to erasure (Note 4)

16 Kword

<0.15

Chip Erase Time

153.6 (WS256N)

77.4 (WS128N)
39.3 (WS064N)

308 (WS256N)
154 (WS128N)

78 (WS064N)

ACC

130.6 (WS256N)

65.8 (WS128N)
33.4 (WS064N)

262 (WS256N)
132 (WS128N)

66 (WS064N)

Single Word Programming Time
(Note 8)

400

µs

ACC

240

Effective Word Programming Time
utilizing Program Write Buffer

9.4

µs

ACC

Total 32-Word Buffer Programming
Time

300

3000

µs

ACC

192

1920

Chip Programming Time (Note 3)

157.3 (WS256N)

78.6 (WS128N)
39.3 (WS064N)

314.6 (WS256N)
157.3 (WS128N)

78.6 (WS064N)

Excludes system
level overhead

(Note 5)

ACC

100.7 (WS256N)

50.3 (WS128N)
25.2 (WS064N)

201.3 (WS256N)
100.7 (WS128N)

50.3 (WS064N)

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

Table 12.1. Memory Array Commands

Command Sequence

(Notes)

c
l
es

Bus Cycles (Notes 15)

First

Second

Third Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Asynchronous Read (6)

Reset (7)

XXX

Aut

o
-

sel

e
ct (8)

Manufacturer ID

555

2AA

[BA]555

[BA]X00

0001

Device ID (9)

555

2AA

[BA]555

[BA]X01

227E

BA+X0E

Data

BA+X0F 2200

Indicator Bits (10)

555

2AA

[BA]555

[BA]X03

Data

Program

555

2AA

555

Write to Buffer (11)

555

2AA

WBL

Program Buffer to Flash

Write to Buffer Abort Reset (12)

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

Sector Erase

555

2AA

555

2AA

Erase/Program Suspend (13)

Erase/Program Resume (14)

Set Configuration Register (18)

555

2AA

555

X00

Read Configuration Register

555

2AA

555

X00

CFI Query (15)

[BA]555

Unlock Byp

a
ss

Mode

Entry 3

555

2AA

555

Program (16)

XXX

CFI (16)

XXX

Reset

XXX

SecSi S

e
ct

o
r

Entry

555

2AA

555

Program (17)

555

2AA

555

Read (17)

Data

Exit (17)

555

2AA

555

XXX

Legend:
X = Don't care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the

AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE#

pulse, whichever occurs first.

SA = Sector Address. WS256N = A23A14; WS128N = A22A14;

WS064N = A21A14.
BA = Bank Address. WS256N = A23A20; WS128N = A22A20;

WS064N = A21A18.
CR = Configuration Register data bits D15D0.
WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See

Table 7.1

for description of bus operations.

2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are

don't cares (each hex digit implies 4 bits of data).

5. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

6. No unlock or command cycles required when bank is reading

array data.

7. Reset command is required to return to reading array data (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high

(while the bank is providing status information) or performing

sector lock/unlock.

8. The system must provide the bank address. See

Autoselect

section for more information.

9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231

(WS128N).

10. See

Table 7.9

for indicator bit values.

11. Total number of cycles in the command sequence is determined

by the number of words written to the write buffer.

12. Command sequence resets device for next command after write-

to-buffer operation.

13. System may read and program in non-erasing sectors, or enter

the autoselect mode, when in the Erase Suspend mode. The

Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

14. Erase Resume command is valid only during the Erase Suspend

mode, and requires the bank address.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode. Address equals 55h on all

future devices, but 555h for WS256N/128N/064N.

16. Requires Entry command sequence prior to execution. Unlock

Bypass Reset command is required to return to reading array

data.

17. Requires Entry command sequence prior to execution. SecSi

Sector Exit Reset command is required to exit this mode; device

may otherwise be placed in an unknown state.

18. Requires reset command to configure the Configuration Register.

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

Table 12.2. Sector Protection Commands

Command Sequence

(Notes)

e
s

Bus Cycles (Notes 14)

First

Second

Third Fourth

Fifth

Sixth

Seventh

Addr

Data

Addr

Data

Addr

Data

Addr

Data Addr Data Addr Data Addr Data

Lock

Bits

Command Set Entry (5)

555

2AA

555

Program (6, 12)

77/00

data

Read (6)

data

Command Set Exit (7)

Password

Protection

Command Set Entry (5)

555

2AA

555

Program [0-3] (8)

PWD[0-3]

Read (9)

4 0...00 PWD0 0...01

PWD1

0...02

PWD2 0...03 PWD3

Unlock

PWD0

PWD1

PWD2

PWD3

Command Set Exit (7)

Non-Volatile

Sector

Protection (PPB)

Command Set Entry (5)

555

2AA

[BA]555

PPB Program (10)

All PPB Erase (10, 11)

PPB Status Read

RD(0)

Command Set Exit (7)

Global

Volatile Sector

Protection

Freeze

(PPB Lock)

Command Set Entry (5)

555

2AA

[BA]555

PPB Lock Bit Set

PPB Lock Bit Status Read

RD(0)

Command Set Exit (7)

Volatile Sector

Protection

(DYB)

Command Set Entry (5)

555

2AA

[BA]555

DYB Set

DYB Clear

DYB Status Read

RD(0)

Command Set Exit (7)

Legend:
X = Don't care.
RA = Address of the memory location to be read.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must

be set to `0' for protection while PD(2), bit[2] must be left as `1'.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must

be set to `0' for protection while PD(1), bit[1] must be left as `1'.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23A14; WS128N = A22A14;

WS064N = A21A14.

BA = Bank Address. WS256N = A23A20; WS128N = A22A20;

WS064N = A21A18.
PWD3PWD0 = Password Data. PD3PD0 present four 16 bit

combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If

protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,

DQ2 = 1.

Notes:

1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are

don't cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

5. Entry commands are required to enter a specific mode to enable

instructions only available within that mode.

6. If both the Persistent Protection Mode Locking Bit and the

Password Protection Mode Locking Bit are set at the same time,

the command operation aborts and returns the device to the

default Persistent Sector Protection Mode during 2nd bus cycle.

Note that on all future devices, addresses equal 00h, but is

currently 77h for the WS256N only. See Tables

8.1

and

8.2

for

explanation of lock bits.

7. Exit command must be issued to reset the device into read

mode; device may otherwise be placed in an unknown state.

8. Entire two bus-cycle sequence must be entered for each portion

of the password.

9. Full address range is required for reading password.
10. See

Figure 8.2

for details.

11. "All PPB Erase" command pre-programs all PPBs before erasure

to prevent over-erasure.

12. The second cycle address for the lock register program operation

is 77 for S29Ws256N; however, for WS128N and Ws064N this

address is 00.

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

12.1

Common Flash Memory Interface

The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and back-ward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address (BA)555h any time the device is ready to read array data. The system can read CFI in-
formation at the addresses given in Tables

12.312.6

) within that bank. All reads outside of the

CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed,
writes are not. To terminate reading CFI data, the system must write the reset command.

The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User's Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.

/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* write CFI entry command */

/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command */

For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A
and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.

Table 12.3. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string "QRY"

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

19h

1Ah

0000h

Address for Alternate OEM Extended Table (00h = none exists)

Table 12.4. System Interface String

Addresses

Data

Description

1Bh

0017h

Min. (write/erase)

D7D4: volt, D3D0: 100 millivolt

1Ch

0019h

Max. (write/erase)

D7D4: volt, D3D0: 100 millivolt

1Dh

0000h

Min. voltage (00h = no V

pin present)

1Eh

0000h

Max. voltage (00h = no V

pin present)

1Fh

0006h

Typical timeout per single byte/word write 2

µs

20h

0009h

Typical timeout for Min. size buffer write 2

µs (00h = not supported)

21h

000Ah

Typical timeout per individual block erase 2

22h

0000h

Typical timeout for full chip erase 2

ms (00h = not supported)

23h

0004h

Max. timeout for byte/word write 2

times typical

24h

0004h

Max. timeout for buffer write 2

times typical

25h

0003h

Max. timeout per individual block erase 2

times typical

26h

0000h

Max. timeout for full chip erase 2

times typical (00h = not supported)

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

Table 12.6. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string "PRI"

43h

0031h

Major version number, ASCII

44h

0034h

Minor version number, ASCII

45h

0100h

Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Technology (Bits 5-2) 0100 = 0.11 µm

46h

0002h

Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h

0001h

Sector Protect
0 = Not Supported, X = Number of sectors in per group

48h

0000h

Sector Temporary Unprotect
00 = Not Supported, 01 = Supported

49h

0008h

Sector Protect/Unprotect scheme
08 = Advanced Sector Protection

4Ah

00F3h (WS256N)

007Bh (WS128N)

003Fh (WS064N)

Simultaneous Operation
Number of Sectors in all banks except boot bank

4Bh

0001h

Burst Mode Type
00 = Not Supported, 01 = Supported

4Ch

0000h

Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page

4Dh

0085h

ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh

0095h

ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh

0001h

Top/Bottom Boot Sector Flag
0001h = Dual Boot Device

50h

0001h

Program Suspend. 00h = not supported

51h

0001h

Unlock Bypass
00 = Not Supported, 01=Supported

52h

0007h

SecSi Sector (Customer OTP Area) Size 2

bytes

53h

0014h

Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2

54h

0014h

Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2

55h

0005h

Erase Suspend Time-out Maximum 2

56h

0005h

Program Suspend Time-out Maximum 2

57h

0010h

Bank Organization: X = Number of banks

58h

0013h (WS256N)

000Bh (WS128N)

0007h (WS064N)

Bank 0 Region Information. X = Number of sectors in bank

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

59h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 1 Region Information. X = Number of sectors in bank

5Ah

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 2 Region Information. X = Number of sectors in bank

5Bh

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 3 Region Information. X = Number of sectors in bank

5Ch

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 4 Region Information. X = Number of sectors in bank

5Dh

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 5 Region Information. X = Number of sectors in bank

5Eh

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 6 Region Information. X = Number of sectors in bank

5Fh

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 7 Region Information. X = Number of sectors in bank

60h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 8 Region Information. X = Number of sectors in bank

61h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 9 Region Information. X = Number of sectors in bank

62h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 10 Region Information. X = Number of sectors in bank

63h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 11 Region Information. X = Number of sectors in bank

64h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 12 Region Information. X = Number of sectors in bank

65h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 13 Region Information. X = Number of sectors in bank

66h

0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 14 Region Information. X = Number of sectors in bank

67h

0013h (WS256N)

000Bh (WS128N)

0007h (WS064N)

Bank 15 Region Information. X = Number of sectors in bank

Table 12.6. Primary Vendor-Specific Extended Query (Continued)

Addresses

Data

Description

S29WS-N_00_G0 January 25, 2005

A d v a n c e I n f o r m a t i o n

13 Commonly

Used

Terms

Term

Definition

ACC

ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above V

. In some devices ACC

may protect all sectors when at a low voltage.

max

Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]

min

Least significant bit of the address input signals (A0 for all devices in this document).

Asynchronous

Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.

Autoselect

Read mode for obtaining manufacturer and device information as well as sector
protection status.

Bank

Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.

Boot sector

Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.

Boundary

Location at the beginning or end of series of memory locations.

Burst Read

See synchronous read.

Byte

8 bits

CFI

Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.

Clear

Zero (Logic Low Level)

Configuration Register

Special purpose register which must be programmed to enable synchronous read
mode

Continuous Read

Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address

Erase

Returns bits of a Flash memory array to their default state of a logical One (High Level).

Erase Suspend/Erase Resume

Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure

BGA

Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.

Linear Read

Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
or without wraparound before requiring a new initial address.

MCP

Multi-Chip Package. A method of combining integrated circuits in a single package by
"stacking" multiple die of the same or different devices.

Memory Array

The programmable area of the product available for data storage.

MirrorBitTM Technology

SpansionTM trademarked technology for storing multiple bits of data in the same
transistor.

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

Page

Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.

Page Read

Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less "page"
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.

Password Protection

Sector protection method which uses a programmable password, in addition to the
Persistent Protection method, for protection of sectors in the Flash memory device.

Persistent Protection

Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.

Program

Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of "ones" and "zeros".

Program Suspend/Program
Resume

Halts a programming operation to read data from any location that is not selected for
programming or erase.

Read

Host bus cycle that causes the Flash to output data onto the data bus.

Registers

Dynamic storage bits for holding device control information or tracking the status of
an operation.

Secured Silicon

Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.

Sector Protection

Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase ignores program or erase commands related to that
sector.

Sector

An Area of the memory array in which all bits must be erased together by an erase
operation.

Simultaneous Operation

Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank. Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.

Synchronous Operation

Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).

VersatileIOTM (V

)

Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.

Unlock Bypass

Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two
"Unlock" write cycles, of the usual 4 cycle Program command, are not required
reducing all Program commands to two bus cycles while in this mode.

Word

Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.

Term

Definition

January 25, 2005 S29WS-N_00_G0

A d v a n c e I n f o r m a t i o n

14 Revisions

Revision F (October 29, 2004)

Data sheet completely revised. Changed arrangement of sections; edited explanatory text, added
flowcharts. This document supersedes Revision E+1, issued August 9, 2004; only the changes
specified for Revision F in this section affect the document or device. All other device specifica-
tions remain the same as presented in Revision E+1.

Deleted product selector guide.

11.8.2

Synchronous/Burst Read

Deleted t

AAS

and t

AAH

from table. Modified Note 1.

Table 12.4

System Interface String

Changed data at address 23h from 0003h to 0004h.

Revision G (January 25, 2005)

Global
Updated t

IACC

, t

BACC

, t

, CFI address 4Ah, and the Configuration Register.

Added

Figure 8.2

"PPB Program/Erase Algorithm"

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for

any

use

that

includes

fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2)

for any use where chance of failure is intolerable

(i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable

you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan

, the US Export Administration Regulations or the applicable laws of any other country,

the prior au-

thorization by

the respective government entity

will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.

Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S29WS064N0LBFI110