This document contains information on a product under development at Spansion, LLC. The information is intended to help you evaluate this product. Do not design in
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Publication Number S71PL129Jxx_00 Revision A Amendment 5 Issue Date December 23, 2004
ADVANCE
INFORMATION
S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt
High performance
-- 65ns (65ns Flash, 70ns pSRAM)
Package
-- 8 x 11.6 x 1.2 mm 64 ball FBGA
Operating Temperature
-- 25C to +85C (Wireless)
-- 40C to +85C (Industrial)
Dual CE# Flash memory
General Description
The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) pack-
ages and consists of:
One S29PL129J Flash memory die
One 16M, 32M, or 64M pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details.
Flash Memory Density
128Mb
pSRAM
Density
64Mb
S71PL129JC0
32Mb
S71PL129JB0
16Mb
S71PL129JA0
2
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A5_E December 23, 2004
A d v a n c e I n f o r m a t i o n
Product Selector Guide
128 Mb Flash Memory
Device-Model#
pSRAM density
Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type
Package
S71PL129JA0-9P
16M pSRAM
65
70
Type 7
TLA064
S71PL129JB0-9Z
32M pSRAM
65
70
Type 7
TLA064
S71PL129JB0-9B
32M pSRAM
65
70
Type 2
TLA064
S71PL129JB0-9U
32M pSRAM
65
70
Type 6
TLA064
S71PL129JC0-9Z
64M pSRAM
65
70
Type 7
TLA064
S71PL129JC0-9U
64M pSRAM
65
70
Type 6
TLA064
December 23, 2004 S71PL129Jxx_00_A5
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A d v a n c e I n f o r m a t i o n
S71PL129JC0/S71PL129JB0/S71PL129JA0
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
128 Mb Flash Memory ..........................................................................................2
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Input/Output Description . . . . . . . . . . . . . . . . . . . 8
Pin Description ......................................................................................................8
Logic Symbol ...........................................................................................................8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11
TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................ 11
S29PL129J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Simultaneous Read/Write Operation with Zero Latency ...................... 14
Page Mode Features ........................................................................................... 14
Standard Flash Memory Features ................................................................... 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. PL129J Device Bus Operations ................................ 19
Requirements for Reading Array Data ......................................................... 19
Random Read (Non-Page Read) ............................................................... 20
Page Mode Read ............................................................................................. 20
Table 2. Page Select .......................................................... 20
Simultaneous Read/Write Operation .......................................................... 20
Writing Commands/Command Sequences ................................................. 21
Accelerated Program Operation ............................................................... 21
Autoselect Functions ..................................................................................... 21
Standby Mode ........................................................................................................21
Automatic Sleep Mode ..................................................................................... 22
RESET#: Hardware Reset Pin ........................................................................ 22
Output Disable Mode ....................................................................................... 22
Table 3. S29PL129J Sector Architecture ............................... 23
Table 4. Secured Silicon Sector Addresses ............................ 29
Autoselect Mode ................................................................................................ 29
Table 5. Autoselect Codes for PL129J ................................... 30
Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 31
Selecting a Sector Protection Mode ..............................................................32
Table 7. Sector Protection Schemes ..................................... 32
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Persistent Sector Protection ...........................................................................32
Password Sector Protection ............................................................................32
WP# Hardware Protection .............................................................................32
Selecting a Sector Protection Mode ..............................................................32
Persistent Sector Protection . . . . . . . . . . . . . . . . 33
Persistent Protection Bit (PPB) .......................................................................33
Persistent Protection Bit Lock (PPB Lock) .................................................33
Dynamic Protection Bit (DYB) .......................................................................33
Persistent Sector Protection Mode Locking Bit ........................................35
Password Protection Mode . . . . . . . . . . . . . . . . . 35
Password and Password Mode Locking Bit ................................................36
64-bit Password ...................................................................................................36
Write Protect (WP#) ....................................................................................... 36
Persistent Protection Bit Lock ................................................................... 37
High Voltage Sector Protection ..................................................................... 37
Figure 1. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 38
Temporary Sector Unprotect ........................................................................ 39
Figure 2. Temporary Sector Unprotect Operation ................... 39
Secured Silicon Sector Flash Memory Region ........................................... 39
Factory-Locked Area (64 words) ..............................................................40
Customer-Lockable Area (64 words) ......................................................40
Secured Silicon Sector Protection Bits ....................................................40
Figure 3. Secured Silicon Sector Protect Verify ...................... 41
Hardware Data Protection ..............................................................................41
Low VCC Write Inhibit .................................................................................41
Write Pulse "Glitch" Protection ................................................................41
Logical Inhibit ....................................................................................................41
Power-Up Write Inhibit ................................................................................41
Common Flash Memory Interface (CFI) . . . . . . 42
Table 8. CFI Query Identification String ................................ 42
Table 9. System Interface String ......................................... 43
Table 10. Device Geometry Definition ................................... 43
Table 11. Primary Vendor-Specific Extended Query ................ 43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ........................................................................................... 45
Reset Command ................................................................................................. 45
Autoselect Command Sequence ....................................................................46
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence ....................................................................................................................46
Word Program Command Sequence ...........................................................46
Unlock Bypass Command Sequence ........................................................ 47
Figure 4. Program Operation ............................................... 48
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence ................................................................49
Figure 5. Erase Operation ................................................... 50
Erase Suspend/Erase Resume Commands ..................................................50
Password Program Command ........................................................................ 51
Password Verify Command .............................................................................. 51
Password Protection Mode Locking Bit Program Command ............... 51
Persistent Sector Protection Mode Locking Bit Program Command 52
Secured Silicon Sector Protection Bit Program Command .................. 52
PPB Lock Bit Set Command ............................................................................ 52
DYB Write Command ...................................................................................... 52
Password Unlock Command .......................................................................... 52
PPB Program Command .................................................................................. 53
All PPB Erase Command .................................................................................. 53
DYB Write Command ...................................................................................... 53
PPB Lock Bit Set Command ............................................................................ 53
Command ............................................................................................................. 54
Command Definitions Tables ......................................................................... 54
Table 12. Memory Array Command Definitions ...................... 54
Table 13. Sector Protection Command Definitions .................. 55
Write Operation Status . . . . . . . . . . . . . . . . . . . . 56
DQ7: Data# Polling ............................................................................................ 56
Figure 6. Data# Polling Algorithm ........................................ 58
RY/BY#: Ready/Busy# ....................................................................................... 58
DQ6: Toggle Bit I ...............................................................................................58
Figure 7. Toggle Bit Algorithm ............................................. 59
DQ2: Toggle Bit II ..............................................................................................60
Reading Toggle Bits DQ6/DQ2 .....................................................................60
DQ5: Exceeded Timing Limits ........................................................................60
DQ3: Sector Erase Timer .................................................................................61
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A d v a n c e I n f o r m a t i o n
Table 14. Write Operation Status ......................................... 61
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .62
Figure 8. Maximum Overshoot Waveforms............................. 62
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .63
Industrial (I) Devices ..........................................................................................63
Extended (E) Devices .........................................................................................63
Supply Voltages ....................................................................................................63
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 15. CMOS Compatible ................................................ 64
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Test Conditions ...................................................................................................65
Figure 9. Test Setups......................................................... 65
Table 16. Test Specifications ............................................... 65
Switching Waveforms ........................................................................................65
Table 17. Key to Switching Waveforms ................................. 65
Figure 10. Input Waveforms and Measurement Levels............. 66
VCC RampRate .................................................................................................. 66
Read Operations ................................................................................................ 66
Table 18. Read-Only Operations .......................................... 66
Figure 11. Read Operation Timings....................................... 67
Figure 12. Page Read Operation Timings ............................... 67
Reset ...................................................................................................................... 68
Table 19. Hardware Reset (RESET#) .................................... 68
Figure 13. Reset Timings..................................................... 68
Erase/Program Operations ............................................................................. 69
Table 20. Erase and Program Operations .............................. 69
Timing Diagrams ................................................................................................. 70
Figure 14. Program Operation Timings .................................. 70
Figure 15. Accelerated Program Timing Diagram .................... 70
Figure 16. Chip/Sector Erase Operation Timings..................... 71
Figure 17. Back-to-back Read/Write Cycle Timings ................. 72
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 72
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 73
Figure 20. DQ2 vs. DQ6 ...................................................... 73
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 21. Temporary Sector Unprotect ................................. 74
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 74
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 75
Controlled Erase Operations ..........................................................................76
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 76
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 77
Table 24. CE1#/CE2# Timing ............................................. 77
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 78
Table 25. Erase And Programming Performance .................... 78
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 78
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Description . . . . . . . . . . . . . . . . . . . . . 80
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 80
AC Characteristics and Operating Conditions . 81
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 82
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83
Read Timings ........................................................................................................83
Figure 24. Read Cycle ......................................................... 83
Figure 25. Page Read Cycle (8 Words Access) ........................ 84
Write Timings ......................................................................................................85
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 85
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 86
Deep Power-down Timing ..............................................................................86
Figure 28. Deep Power Down Timing .................................... 86
Power-on Timing ................................................................................................86
Figure 29. Power-on Timing ................................................ 86
Provisions of Address Skew ............................................................................87
Read ....................................................................................................................87
Figure 30. Read................................................................. 87
Write ..................................................................................................................87
Figure 31. Write ................................................................ 87
pSRAM Type 1
Functional Description . . . . . . . . . . . . . . . . . . . . . 88
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 88
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .89
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 94
Output Load Circuit .......................................................................................... 95
Figure 32. Output Load Circuit............................................. 95
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 95
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107
Read Cycle ...........................................................................................................107
Figure 33. Timing of Read Cycle
(CE# = OE# = V
IL
, WE# = ZZ# = V
IH
) .............................. 107
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = V
IH
)......................................................... 108
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = V
IH
)......................................................... 109
Write Cycle ..........................................................................................................110
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = V
IH
)................................................ 110
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = V
IH
)................................................. 110
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = V
IH
) ................................................................... 111
Partial Array Self Refresh (PAR) .....................................................................111
Temperature Compensated Refresh (for 64Mb) .....................................112
Deep Sleep Mode ...............................................................................................112
Reduced Memory Size (for 32M and 16M) ..................................................112
Other Mode Register Settings (for 64M) ....................................................112
Figure 39. Mode Register.................................................. 113
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Don't Care)..................................................................... 113
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 114
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 114
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Product Information . . . . . . . . . . . . . . . . . . . . . . 118
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 119
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119
Power Up ..............................................................................................................119
Figure 43. Power Up 1 (CS1# Controlled) ........................... 119
Figure 44. Power Up 2 (CS2 Controlled).............................. 119
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Absolute Maximum Ratings . . . . . . . . . . . . . . . 120
DC Recommended Operating Conditions . . . . 120
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A d v a n c e I n f o r m a t i o n
DC and Operating Characteristics . . . . . . . . . . . 121
Common ............................................................................................................... 121
16M pSRAM ......................................................................................................... 122
32M pSRAM ........................................................................................................ 122
64M pSRAM ........................................................................................................ 123
128M pSRAM ....................................................................................................... 123
AC Operating Conditions . . . . . . . . . . . . . . . . . 124
Test Conditions (Test Load and Test Input/Output Reference) ....... 124
Figure 45. Output Load ..................................................... 124
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126
Read Timings ...................................................................................................... 126
Figure 46. Timing Waveform of Read Cycle(1)...................... 126
Figure 47. Timing Waveform of Read Cycle(2)...................... 126
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127
Write Timings .................................................................................................... 127
Figure 49. Write Cycle #1 (WE# Controlled) ........................ 127
Figure 50. Write Cycle #2 (CS1# Controlled) ....................... 128
Figure 51. Timing Waveform of Write Cycle(3)
(CS2 Controlled) .............................................................. 128
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ...................................................................... 129
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Functional Description . . . . . . . . . . . . . . . . . . . . . 131
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131
Power Down ....................................................................................................... 131
Power Down Program Sequence ................................................................. 132
Address Key ....................................................................................................... 132
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135
Read Operation ..................................................................................................135
Write Operation ............................................................................................... 136
Power Down Parameters ............................................................................... 137
Other Timing Parameters ............................................................................... 137
AC Test Conditions .........................................................................................138
AC Measurement Output Load Circuits ...................................................138
Figure 53. AC Output Load Circuit 16 Mb.......................... 138
Figure 54. AC Output Load Circuit 32 Mb and 64 Mb .......... 138
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
Read Timings .......................................................................................................139
Figure 55. Read Timing #1 (Basic Timing) .......................... 139
Figure 56. Read Timing #2 (OE# Address Access................. 139
Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 140
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 141
Write Timings ......................................................................................................141
Figure 60. Write Timing #1 (Basic Timing).......................... 141
Figure 61. Write Timing #2 (WE# Control).......................... 142
Figure 62. Write Timing #3-1
(WE#/LB#/UB# Byte Write Control) .................................. 142
Figure 63. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control) .................................. 143
Figure 64. Write Timing #3-4
(WE#/LB#/UB# Byte Write Control) .................................. 143
Read/Write Timings ..........................................................................................144
Figure 65. Read/Write Timing #1-1 (CE1# Control) ............. 144
Figure 66. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................ 144
Figure 67. Read / Write Timing #2 (OE#, WE# Control) ....... 145
Figure 68. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control) ........................................ 145
Figure 69. Power-up Timing #1 ......................................... 146
Figure 70. Power-up Timing #2 ......................................... 146
Figure 71. Power Down Entry and Exit Timing ..................... 146
Figure 72. Standby Entry Timing after Read or Write............ 147
Figure 73. Power Down Program Timing (for 32M/64M Only). 147
Revision Summary
6
S71PL129Jxx_00_A5 December 23, 2004
A d v a n c e I n f o r m a t i o n
MCP Block Diagram
V
SS
RESET#
Flash 1
IO
15
-IO
0
V
CC
f
DQ
15
to DQ
0
RY/BY#
WP#/ACC
V
CC
V
CC
CE2#f
Flash-only Address
Shared Address
OE#
WE#
V
CCS
V
CC
CE#s
UB#s
LB#s
CE#
UB#
LB#
pSRAM
CE2#ps
CE1#f
CEM1#ps
December 23, 2004 S71PL129Jxx_00_A5
7
A d v a n c e I n f o r m a t i o n
Connection Diagram
Note: May be shared depending on density:
-- A21 is shared for the 64M pSRAM configuration.
-- A20 is shred for the 32M pSRAM configuration.
-- A19 is shared for the 16M pSRAM configuration.
Note:
It is advised to tie J5 and L5 together on the board.
MCP
Flash-only Addresses
Shared Addresses
S71PL129JC0
A22
A21-A0
S71PL129JB0
A22-A21
A20-A0
S71PL129JA0
A22-A20
A19-A0
E4
UB#
F4
A18
G4
A17
H4
DQ1
J4
DQ9
K4
DQ10
DQ2
D4
E6
CE2s
A20
J6
DQ4
K6
VCCs
RFU
D6
RFU
E7
A19
F7
A9
G7
A10
H7
DQ6
J7
DQ13
K7
DQ12
DQ5
D7
E5
RST#f
RY/BY#
J5
DQ3
K5
VCCf
DQ11
D5
RFU
E8
A12
F8
A13
G8
A14
H8
RFU
J8
DQ15
K8
DQ7
DQ14
D8
E9
F9
A21
G9
CE2#
H9
A16
J9
RFU
VSS
E3
A6
F3
A5
G3
A4
H3
VSS
J3
OE#
K3
DQ0
CE1#s
DQ8
D3
E2
F2
A2
G2
A1
H2
A0
J2
CE1#f
H6
H5
B6
B5
RAM only
Shared
(Note 1)
Flash only
Legend
Reserved for
Future Use
RFU
RFU
L6
L5
LB#
C4
WE#
C6
A8
C7
WP/ACC
C5
A11
C8
A7
C3
A3
D2
A15
D9
A1
NC
A10
NC
M1
M10
NC
NC
64-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
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S71PL129Jxx_00_A5 December 23, 2004
A d v a n c e I n f o r m a t i o n
Input/Output Description
Pin Description
A21A0
=
22 Address Inputs (Common)
DQ15DQ0
=
16 Data Inputs/Outputs (Common)
CE1#f
=
Chip Enable 1 (Flash)
CE2#f
=
Chip Enable 2 (Flash)
CE1#ps
=
Chip Enable 1 (pSRAM)
CE2ps
=
Chip Enable 2 (pSRAM)
OE#
=
Output Enable (Common)
WE#
=
Write Enable (Common)
RY/BY#
=
Ready/Busy Output
UB#
=
Upper Byte Control (pSRAM)
LB#
=
Lower Byte Control (pSRAM)
RESET#
=
Hardware Reset Pin, Active Low (Flash 1)
WP#/ACC
=
Hardware Write Protect/Acceleration Pin (Flash)
V
CC
f
=
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
V
CC
ps
=
pSRAM Power Supply
V
SS
=
Device Ground (Common)
NC
=
Pin Not Connected Internally
Logic Symbol
22
16
DQ15DQ0
A21A0
CE1#f
OE#
WE#
RES ET#
R Y/BY#
WP #/ACC
UB#
CE2#f
CE2ps
CE1#ps
LB#
December 23, 2004 S71PL129Jxx_00_A5
9
A d v a n c e I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
S71PL
129
J
B0
BA
W
9
Z
0
PACKING TYPE
0
= Tray
2
= 7" Tape and Reel
3
= 13" Tape and Reel
MODEL NUMBER
See valid combinations table.
PACKAGE MODIFIER
9
= 8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064)
TEMPERATURE RANGE
W
= Wireless (-25
C to +85
C)
I
= Industrial (-40
C to +85
C)
PACKAGE TYPE
BA
= Fine-pitch BGA Lead (Pb)-free compliant package
BF
= Fine-pitch BGA Lead (Pb)-free package
pSRAM DENSITY
C0
= 64 Mb pSRAM
B0
= 32 Mb pSRAM
A0
= 16 Mb pSRAM
PROCESS TECHNOLOGY
J
= 110 nm, Floating Gate Technology
FLASH DENSITY
129
= 128Mb, dual CE#
PRODUCT FAMILY
S71PL Multi-chip Product (MCP)
3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM
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S71PL129Jxx_00_A5 December 23, 2004
A d v a n c e I n f o r m a t i o n
S71PL129J Valid Combinations
Speed Options
(ns)
(p)SRAM
Type/Access
Time (ns)
Package
Marking
Base Ordering
Part Number
Package &
Temperature
Package Modifier/
Model Number
Packing Type
S71PL129JA0
BAW
9P
0, 2, 3 (
Note 1
)
65
pSRAM 7 / 70
(
Note 2
)
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
pSRAM 2 / 70
S71PL129JB0
9U
pSRAM 6 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
S71PL129JA0
BFW
9P
0, 2, 3 (
Note 1
)
65
pSRAM 7 / 70
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
pSRAM 2 / 70
S71PL129JB0
9U
pSRAM 6 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
S71PL129JA0
BAI
9P
0, 2, 3 (
Note 1
)
65
pSRAM 7 / 70
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
pSRAM 2 / 70
S71PL129JB0
9U
pSRAM 6 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
S71PL129JA0
BFI
9P
0, 2, 3 (
Note 1
)
65
pSRAM 7 / 70
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
pSRAM 2 / 70
S71PL129JB0
9U
pSRAM 6 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading "S" and packing type
designator from ordering part number.
3. Contact factory for availability of any of the above OPNs. RAM
type availability may vary over time.
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
December 23, 2004 S71PL129Jxx_00_A5
11
A d v a n c e I n f o r m a t i o n
Physical Dimensions
TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package
3352 \ 16-038.22a
PACKAGE
TLA 064
JEDEC
N/A
D x E
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
NOTE
A
---
---
1.20
PROFILE
A1
0.17
---
---
BALL HEIGHT
A2
0.81
---
0.97
BODY THICKNESS
D
11.60 BSC.
BODY SIZE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
n
64
BALL COUNT
b
0.35
0.40
0.45
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B2,B3,B4,B7,B8,B9,B10
C1,C2,C9,C10,D1,D10,E1,E10,
F1,F5,F6,F10,G1,G5,G6,G10
H1,H10,J1,J10,K1,K2,K9,K10
L1,L2,L3,L4,L7,L8,L9,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1.
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.20
C
0.08
C
b
64X
6
0.08 M C
0.15 M C A B
A2
A
A1
SIDE VIEW
L
M
eD
CORNER
E1
7
SE
D1
A
B
D
C
E
F
H
G
10
8
9
7
5
6
4
2
3
J
K
1
eE
SD
BOTTOM VIEW
PIN A1
7
10
INDEX MARK
C
0.15
(2X)
(2X)
C
0.15
B
A
D
E
PIN A1
TOP VIEW
CORNER
Publication Number S29PL129J_MCP_00 Revision A Amendment 0 Issue Date June 4, 2004
ADVANCE
INFORMATION
S29PL129J for MCP
128 Megabit (8 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
TM
Control
Distinctive Characteristics
Architectural Advantages
128 Mbit Page Mode devices
-- Page size of 8 words: Fast page read access from
random locations within the page
Single power supply operation
-- Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
-- Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
-- Data can be continuously read from one bank while
executing erase/program functions in another bank
-- Zero latency switching from write to read operations
FlexBank Architecture
-- 4 separate banks, with up to two simultaneous
operations per device
-- CE#1 controlled banks:
Bank 1A:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
- 48Mbit (32Kw x 96)
-- CE#2 controlled banks:
Bank 2A:
- 48 Mbit (32Kw x 96)
Bank 2B:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/O
TM
(V
IO
) Control
-- Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the V
IO
pin
Secured Silicon Sector region
-- Up to 128 words accessible through a command
sequence
-- Up to 64 factory-locked words
-- Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
Performance Characteristics
High Performance
-- Page access times as fast as 20 ns
-- Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
-- 45 mA active read current
-- 17 mA program/erase current
-- 0.2 A typical standby mode current
Software Features
Software command-set compatible with JEDEC
42.4 standard
-- Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
-- Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
-- Suspends an erase operation to allow read or
program operations in other sectors of same bank
Unlock Bypass Program command
-- Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data
WP#/ ACC (Write Protect/Acceleration) input
-- At V
IL
, hardware level protection for the first and
last two 4K word sectors.
-- At V
IH
, allows removal of sector protection
-- At V
HH
, provides accelerated programming in a
factory setting
Persistent Sector Protection
-- A command sector protection method to lock
combinations of individual sectors and sector groups
Datasheet
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
13
A d v a n c e I n f o r m a t i o n
to prevent program or erase operations within that
sector
-- Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
-- A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
14
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
General Description
The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write
Flash memory device organized as 8 Mwords.
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V V
PP
is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding ran-
dom access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
Bank
PL129J Sectors
CE# Control
1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE1#
1B
48 Mbit (32 Kw x 96)
CE1#
2A
48 Mbit (32 Kw x 96)
CE2#
2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE2#
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
15
A d v a n c e I n f o r m a t i o n
write cycles to program data instead of four. Device erasure occurs by executing
the erase command sequence.
The host system can detect whether a program or erase operation is complete by
reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved. If a read
is needed from the Secured Silicon Sector area (One Time Program area) after
an erase suspend, then the user must use the proper command sequence to
enter and exit this region.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consumption
is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via Fowler-
Nordheim tunneling. The data is programmed using hot electron injection.
16
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Block Diagram
Notes:
1. RY/BY# is an open drain output.
2. For PL129J there are two CE# (CE1# and CE2#)
V
CC
V
SS
State
Control
Command
Register
PGM Voltage
Generator
V
CC
Detector
Timer
Erase Voltage
Generator
Input/Output
Buffers
Sector
Switches
Chip Enable
Output Enable
Logic
Y-Gating
Cell Matrix
Address Latch
Y-Decoder
X-Decoder
Data Latch
RESET#
RY/BY# (See Note)
AmaxA3
A2A0
CE#
WE#
DQ15DQ0
V
IO
OE#
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
17
A d v a n c e I n f o r m a t i o n
Simultaneous Read/Write Block Diagram (PL129J)
Notes:
1. Amax = A21 (PL129J)
V
CC
V
SS
Bank 1A Address
Bank 1B Address
A21A0
RESET#
WE#
CE1#
DQ0DQ15
CE2#
STATE
CONTROL
&
COMMAND
REGISTER
RY/BY#
Bank 1A
X-Decoder
OE#
DQ15DQ0
Status
Control
A21A0
A21A0
A21A0
A21A0
DQ15DQ0
DQ15DQ0
DQ15DQ0
DQ15DQ0
Mux
Mux
Mux
Bank 1B
X-Decoder
Y-gate
Bank 2A
X-Decoder
Bank 2B
X-Decoder
Y-gate
Bank 2A Address
Bank 2B Address
CE1#=L
CE2#=H
CE1#=H
CE2#=L
WP#/ACC
18
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Pin Description
AmaxA0
=
Address bus
DQ15DQ0
=
16-bit data inputs/outputs/float
CE#
=
Chip Enable Inputs
OE#
=
Output Enable Input
WE#
=
Write Enable
V
SS
=
Device Ground
NC
=
Pin Not Connected Internally
RY/BY#
=
Ready/Busy output and open drain.
When RY/BY#= V
IH
, the device is ready to accept
read operations and commands. When RY/BY#=
V
OL
, the device is either executing an embedded
algorithm or the device is executing a hardware
reset operation.
WP#/ACC
=
Write Protect/Acceleration Input.
When WP#/ACC= V
IL
, the highest and lowest two
4K-word sectors are write protected regardless of
other sector protection configurations. When WP#/
ACC= V
IH
, these sector are unprotected unless the
DYB or PPB is programmed. When WP#/ACC= 12V,
program and erase operations are accelerated.
V
IO
=
Input/Output Buffer Power Supply 2.7 V to 3.6 V
V
CC
=
Chip Power Supply
(2.7 V to 3.6 V or 2.7 to 3.3 V)
RESET#
=
Hardware Reset Pin
CE1#, CE2#
=
Chip Enable Inputs.
CE1# controls the 64Mb in Banks 1A and 1B. CE2#
controls the 64 Mb in Banks 2A and 2B.
Notes:
1. Amax = A21
Logic Symbol
max+1
16
DQ15DQ0
AmaxA0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
V
IO
(V
CCQ
)
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
19
A d v a n c e I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the inputs and control levels re-
quired, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.512.5 V, V
HH
= 8.59.5 V, X = Don't Care, SA = Sector
Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
"
"High Voltage Sector Protection"
on page 37."
2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins to V
IL
. In PL129J, CE1# and CE2# are the power control and
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power
control. OE# is the output control and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
See
Table 24
for timing specifications and
Figure 11
for the timing diagram. I
CC1
in the DC Characteristics table represents the active current specification for
reading array data.
Table 1. PL129J Device Bus Operations
Operation
CE1#
CE2#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21A0)
DQ15
DQ0
Read
L
H
L
H
H
X
A
IN
D
OUT
H
L
Write
L
H
H
L
H
X
(
Note 2
)
A
IN
D
IN
H
L
Standby
V
IO
0.3 V
V
IO
0.3 V
X
X
V
IO
0.3 V
X
X
High-Z
Output Disable
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
V
ID
X
A
IN
D
IN
20
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from stable addresses to valid
output data. The chip enable access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t
ACC
t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits AmaxA3 select an 8 word page,
and address bits A2A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
ACC
or t
CE
and subsequent page read ac-
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
PACC
. When CE1# and CE#2 are deasserted (=V
IH
), the
reassertion of CE1# or CE#2 for subsequent access has access time of t
ACC
or
t
CE
. Here again, CE1#/CE#2 selects the device and OE# is the output control and
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping AmaxA3 constant and changing
A2A0 to select the specific word within that page.
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(A21A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
Table 2. Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Bank
CE1#
CE2#
PL129J: A21A20
Bank 1A
0
1
00
Bank 1B
0
1
01, 10, 11
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
21
A d v a n c e I n f o r m a t i o n
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE1# or CE#2 to V
IL
, and OE# to V
IH
.
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word, instead of four.
"Word Program Command Sequence"
on page
46 has details on programming data to the device using both standard and Unlock
Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 4
indicates the set of address space that each sector occupies. A "bank ad-
dress" is the set of address bits required to uniquely select a bank. Similarly, a
"sector address" refers to the address bits required to uniquely select a sector.
"Command Definitions"
on page 45 has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
I
CC2
in the DC Characteristics table represents the active current specification for
the write mode. See the timing specification tables and timing diagrams in
"Re-
set"
for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the
factory.
If the system asserts V
HH
on this pin, the device automatically enters the afore-
mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
HH
from the WP#/ACC pin re-
turns the device to normal operation. Note that V
HH
must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin should be raised to V
CC
when not in
use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-
sistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15DQ0. Standard
read cycle timings apply in this mode. See
"Secured Silicon Sector Addresses"
on
page 29 and
"Autoselect Command Sequence"
on page 46 for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
Bank 2A
1
0
00, 01, 10
Bank 2B
1
0
11
22
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#
pins are both held at V
IO
0.3 V. (Note that this is a more restricted voltage
range than V
IH
.) If CE1# or CE#2 and RESET# are held at V
IH
, but not within V
IO
0.3 V, the device is in standby mode, but the standby current is greater. The
device requires standard access time (t
CE
) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
CC3
in
"DC Characteristics"
represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at V
IH
before
the device reduces current to the stated sleep mode specification.
I
CC5
in
"DC
Characteristics"
represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
SS
0.3 V, the device draws CMOS standby current (
I
CC4
). If RESET# is held
at V
IL
but not within V
SS
0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a "0" (busy) until the internal reset operation is complete, which requires
a time of t
READY
(during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is "1"), the reset
operation is completed within a time of t
READY
(not during Embedded Algorithms).
The system can read data t
RH
after the RESET# pin returns to V
IH
.
Refer to the
AC Characteristics
tables for RESET# parameters and to
Figure 13
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
23
A d v a n c e I n f o r m a t i o n
Table 3. S29PL129J Sector Architecture (Sheet 1 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
Bank
1A
SA1-0
0
1
0000000000
4
000000h000FFFh
SA1-1
0
1
0000000001
4
001000h001FFFh
SA1-2
0
1
0000000010
4
002000h002FFFh
SA1-3
0
1
0000000011
4
003000h003FFFh
SA1-4
0
1
0000000100
4
004000h004FFFh
SA1-5
0
1
0000000101
4
005000h005FFFh
SA1-6
0
1
0000000110
4
006000h006FFFh
SA1-7
0
1
0000000111
4
007000h007FFFh
SA1-8
0
1
0000001XXX
32
008000h00FFFFh
SA1-9
0
1
0000010XXX
32
010000h017FFFh
SA1-10
0
1
0000011XXX
32
018000h01FFFFh
SA1-11
0
1
0000100XXX
32
020000h027FFFh
SA1-12
0
1
0000101XXX
32
028000h02FFFFh
SA1-13
0
1
0000110XXX
32
030000h037FFFh
SA1-14
0
1
0000111XXX
32
038000h03FFFFh
SA1-15
0
1
0001000XXX
32
040000h047FFFh
SA1-16
0
1
0001001XXX
32
048000h04FFFFh
SA1-17
0
1
0001010XXX
32
050000h057FFFh
SA1-18
0
1
0001011XXX
32
058000h05FFFFh
SA1-19
0
1
0001100XXX
32
060000h067FFFh
SA1-20
0
1
0001101XXX
32
068000h06FFFFh
SA1-21
0
1
0001110XXX
32
070000h077FFFh
SA1-22
0
1
0001111XXX
32
078000h07FFFFh
SA1-23
0
1
0010000XXX
32
080000h087FFFh
SA1-24
0
1
0010001XXX
32
088000h08FFFFh
SA1-25
0
1
0010010XXX
32
090000h097FFFh
SA1-26
0
1
0010011XXX
32
098000h09FFFFh
SA1-27
0
1
0010100XXX
32
0A0000h0A7FFFh
SA1-28
0
1
0010101XXX
32
0A8000h0AFFFFh
SA1-29
0
1
0010110XXX
32
0B0000h0B7FFFh
SA1-30
0
1
0010111XXX
32
0B8000h0BFFFFh
SA1-31
0
1
0011000XXX
32
0C0000h0C7FFFh
SA1-32
0
1
0011001XXX
32
0C8000h0CFFFFh
SA1-33
0
1
0011010XXX
32
0D0000h0D7FFFh
SA1-34
0
1
0011011XXX
32
0D8000h0DFFFFh
SA1-35
0
1
0011100XXX
32
0E0000h0E7FFFh
SA1-36
0
1
0011101XXX
32
0E8000h0EFFFFh
SA1-37
0
1
0011110XXX
32
0F0000h0F7FFFh
SA1-38
0
1
0011111XXX
32
0F8000h0FFFFFh
24
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Bank
1B
SA1-39
0
1
0100000XXX
32
100000h107FFFh
SA1-40
0
1
0100001XXX
32
108000h10FFFFh
SA1-41
0
1
0100010XXX
32
110000h117FFFh
SA1-42
0
1
0100011XXX
32
118000h11FFFFh
SA1-43
0
1
0100100XXX
32
120000h127FFFh
SA1-44
0
1
0100101XXX
32
128000h12FFFFh
SA1-45
0
1
0100110XXX
32
130000h137FFFh
SA1-46
0
1
0100111XXX
32
138000h13FFFFh
SA1-47
0
1
0101000XXX
32
140000h147FFFh
SA1-48
0
1
0101001XXX
32
148000h14FFFFh
SA1-49
0
1
0101010XXX
32
150000h157FFFh
SA1-50
0
1
0101011XXX
32
158000h15FFFFh
SA1-51
0
1
0101100XXX
32
160000h167FFFh
SA1-52
0
1
0101101XXX
32
168000h16FFFFh
SA1-53
0
1
0101110XXX
32
170000h177FFFh
SA1-54
0
1
0101111XXX
32
178000h17FFFFh
SA1-55
0
1
0110000XXX
32
180000h187FFFh
SA1-56
0
1
0110001XXX
32
188000h18FFFFh
SA1-57
0
1
0110010XXX
32
190000h197FFFh
SA1-58
0
1
0110011XXX
32
198000h19FFFFh
SA1-59
0
1
0110100XXX
32
1A0000h1A7FFFh
SA1-60
0
1
0110101XXX
32
1A8000h1AFFFFh
SA1-61
0
1
0110110XXX
32
1B0000h1B7FFFh
SA1-62
0
1
0110111XXX
32
1B8000h1BFFFFh
SA1-63
0
1
0111000XXX
32
1C0000h1C7FFFh
SA1-64
0
1
0111001XXX
32
1C8000h1CFFFFh
SA1-65
0
1
0111010XXX
32
1D0000h1D7FFFh
SA1-66
0
1
0111011XXX
32
1D8000h1DFFFFh
SA1-67
0
1
0111100XXX
32
1E0000h1E7FFFh
SA1-68
0
1
0111101XXX
32
1E8000h1EFFFFh
SA1-69
0
1
0111110XXX
32
1F0000h1F7FFFh
SA1-70
0
1
0111111XXX
32
1F8000h1FFFFFh
SA1-71
0
1
1000000XXX
32
200000h207FFFh
SA1-72
0
1
1000001XXX
32
208000h20FFFFh
SA1-73
0
1
1000010XXX
32
210000h217FFFh
SA1-74
0
1
1000011XXX
32
218000h21FFFFh
SA1-75
0
1
1000100XXX
32
220000h227FFFh
SA1-76
0
1
1000101XXX
32
228000h22FFFFh
SA1-77
0
1
1000110XXX
32
230000h237FFFh
SA1-78
0
1
1000111XXX
32
238000h23FFFFh
SA1-79
0
1
1001000XXX
32
240000h247FFFh
SA1-80
0
1
1001001XXX
32
248000h24FFFFh
SA1-81
0
1
1001010XXX
32
250000h257FFFh
SA1-82
0
1
1001011XXX
32
258000h25FFFFh
Table 3. S29PL129J Sector Architecture (Sheet 2 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
25
A d v a n c e I n f o r m a t i o n
Bank
1B
SA1-83
0
1
1001100XXX
32
260000h267FFFh
SA1-84
0
1
1001101XXX
32
268000h26FFFFh
SA1-85
0
1
1001110XXX
32
270000h277FFFh
SA1-86
0
1
1001111XXX
32
278000h27FFFFh
SA1-87
0
1
1010000XXX
32
280000h287FFFh
SA1-88
0
1
1010001XXX
32
288000h28FFFFh
SA1-89
0
1
1010010XXX
32
290000h297FFFh
SA1-90
0
1
1010011XXX
32
298000h29FFFFh
SA1-91
0
1
1010100XXX
32
2A0000h2A7FFFh
SA1-92
0
1
1010101XXX
32
2A8000h2AFFFFh
SA1-93
0
1
1010110XXX
32
2B0000h2B7FFFh
SA1-94
0
1
1010111XXX
32
2B8000h2BFFFFh
SA1-95
0
1
1011000XXX
32
2C0000h2C7FFFh
SA1-96
0
1
1011001XXX
32
2C8000h2CFFFFh
SA1-97
0
1
1011010XXX
32
2D0000h2D7FFFh
SA1-98
0
1
1011011XXX
32
2D8000h2DFFFFh
SA1-99
0
1
1011100XXX
32
2E0000h2E7FFFh
SA1-100
0
1
1011101XXX
32
2E8000h2EFFFFh
SA1-101
0
1
1011110XXX
32
2F0000h2F7FFFh
SA1-102
0
1
1011111XXX
32
2F8000h2FFFFFh
SA1-103
0
1
1100000XXX
32
300000h307FFFh
SA1-104
0
1
1100001XXX
32
308000h30FFFFh
SA1-105
0
1
1100010XXX
32
310000h317FFFh
SA1-106
0
1
1100011XXX
32
318000h31FFFFh
SA1-107
0
1
1100100XXX
32
320000h327FFFh
SA1-108
0
1
1100101XXX
32
328000h32FFFFh
SA1-109
0
1
1100110XXX
32
330000h337FFFh
SA1-110
0
1
1100111XXX
32
338000h33FFFFh
SA1-111
0
1
1101000XXX
32
340000h347FFFh
SA1-112
0
1
1101001XXX
32
348000h34FFFFh
SA1-113
0
1
1101010XXX
32
350000h357FFFh
SA1-114
0
1
1101011XXX
32
358000h35FFFFh
SA1-115
0
1
1101100XXX
32
360000h367FFFh
SA1-116
0
1
1101101XXX
32
368000h36FFFFh
SA1-117
0
1
1101110XXX
32
370000h377FFFh
SA1-118
0
1
1101111XXX
32
378000h37FFFFh
SA1-119
0
1
1110000XXX
32
380000h387FFFh
SA1-120
0
1
1110001XXX
32
388000h38FFFFh
SA1-121
0
1
1110010XXX
32
390000h397FFFh
SA1-122
0
1
1110011XXX
32
398000h39FFFFh
SA1-123
0
1
1110100XXX
32
3A0000h3A7FFFh
SA1-124
0
1
1110101XXX
32
3A8000h3AFFFFh
SA1-125
0
1
1110110XXX
32
3B0000h3B7FFFh
SA1-126
0
1
1110111XXX
32
3B8000h3BFFFFh
Table 3. S29PL129J Sector Architecture (Sheet 3 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
26
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Ba
nk 1B
SA1-127
0
1
1111000XXX
32
3C0000h3C7FFFh
SA1-128
0
1
1111001XXX
32
3C8000h3CFFFFh
SA1-129
0
1
1111010XXX
32
3D0000h3D7FFFh
SA1-130
0
1
1111011XXX
32
3D8000h3DFFFFh
SA1-131
0
1
1111100XXX
32
3E0000h3E7FFFh
SA1-132
0
1
1111101XXX
32
3E8000h3EFFFFh
SA1-133
0
1
1111110XXX
32
3F0000h3F7FFFh
SA1-134
0
1
1111111XXX
32
3F8000h3FFFFFh
Bank
2A
SA2-0
1
0
0000000XXX
32
000000h007FFFh
SA2-1
1
0
0000001XXX
32
008000h00FFFFh
SA2-2
1
0
0000010XXX
32
010000h017FFFh
SA2-3
1
0
0000011XXX
32
018000h01FFFFh
SA2-4
1
0
0000100XXX
32
020000h027FFFh
SA2-5
1
0
0000101XXX
32
028000h02FFFFh
SA2-6
1
0
0000110XXX
32
030000h037FFFh
SA2-7
1
0
0000111XXX
32
038000h03FFFFh
SA2-8
1
0
0001000XXX
32
040000h047FFFh
SA2-9
1
0
0001001XXX
32
048000h04FFFFh
SA2-10
1
0
0001010XXX
32
050000h057FFFh
SA2-11
1
0
0001011XXX
32
058000h05FFFFh
SA2-12
1
0
0001100XXX
32
060000h067FFFh
SA2-13
1
0
0001101XXX
32
068000h06FFFFh
SA2-14
1
0
0001110XXX
32
070000h077FFFh
SA2-15
1
0
0001111XXX
32
078000h07FFFFh
SA2-16
1
0
0010000XXX
32
080000h087FFFh
SA2-17
1
0
0010001XXX
32
088000h08FFFFh
SA2-18
1
0
0010010XXX
32
090000h097FFFh
SA2-19
1
0
0010011XXX
32
098000h09FFFFh
SA2-20
1
0
0010100XXX
32
0A0000h0A7FFFh
SA2-21
1
0
0010101XXX
32
0A8000h0AFFFFh
SA2-22
1
0
0010110XXX
32
0B0000h0B7FFFh
SA2-23
1
0
0010111XXX
32
0B8000h0BFFFFh
SA2-24
1
0
0011000XXX
32
0C0000h0C7FFFh
SA2-25
1
0
0011001XXX
32
0C8000h0CFFFFh
SA2-26
1
0
0011010XXX
32
0D0000h0D7FFFh
SA2-27
1
0
0011011XXX
32
0D8000h0DFFFFh
SA2-28
1
0
0011100XXX
32
0E0000h0E7FFFh
SA2-29
1
0
0011101XXX
32
0E8000h0EFFFFh
SA2-30
1
0
0011110XXX
32
0F0000h0F7FFFh
SA2-31
1
0
0011111XXX
32
0F8000h0FFFFFh
SA2-32
1
0
0100000XXX
32
100000h107FFFh
SA2-33
1
0
0100001XXX
32
108000h10FFFFh
SA2-34
1
0
0100010XXX
32
110000h117FFFh
SA2-35
1
0
0100011XXX
32
118000h11FFFFh
Table 3. S29PL129J Sector Architecture (Sheet 4 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
27
A d v a n c e I n f o r m a t i o n
Ba
nk 2A
SA2-36
1
0
0100100XXX
32
120000h127FFFh
SA2-37
1
0
0100101XXX
32
128000h12FFFFh
SA2-38
1
0
0100110XXX
32
130000h137FFFh
SA2-39
1
0
0100111XXX
32
138000h13FFFFh
SA2-40
1
0
0101000XXX
32
140000h147FFFh
SA2-41
1
0
0101001XXX
32
148000h14FFFFh
SA2-42
1
0
0101010XXX
32
150000h157FFFh
SA2-43
1
0
0101011XXX
32
158000h15FFFFh
Bank
2A
SA2-44
1
0
0101100XXX
32
160000h167FFFh
SA2-45
1
0
0101101XXX
32
168000h16FFFFh
SA2-46
1
0
0101110XXX
32
170000h177FFFh
SA2-47
1
0
0101111XXX
32
178000h17FFFFh
SA2-48
1
0
0110000XXX
32
180000h187FFFh
SA2-49
1
0
0110001XXX
32
188000h18FFFFh
SA2-50
1
0
0110010XXX
32
190000h197FFFh
SA2-51
1
0
0110011XXX
32
198000h19FFFFh
SA2-52
1
0
0110100XXX
32
1A0000h1A7FFFh
SA2-53
1
0
0110101XXX
32
1A8000h1AFFFFh
SA2-54
1
0
0110110XXX
32
1B0000h1B7FFFh
SA2-55
1
0
0110111XXX
32
1B8000h1BFFFFh
SA2-56
1
0
0111000XXX
32
1C0000h1C7FFFh
SA2-57
1
0
0111001XXX
32
1C8000h1CFFFFh
SA2-58
1
0
0111010XXX
32
1D0000h1D7FFFh
SA2-59
1
0
0111011XXX
32
1D8000h1DFFFFh
SA2-60
1
0
0111100XXX
32
1E0000h1E7FFFh
SA2-61
1
0
0111101XXX
32
1E8000h1EFFFFh
SA2-62
1
0
0111110XXX
32
1F0000h1F7FFFh
SA2-63
1
0
0111111XXX
32
1F8000h1FFFFFh
SA2-64
1
0
1000000XXX
32
200000h207FFFh
SA2-65
1
0
1000001XXX
32
208000h20FFFFh
SA2-66
1
0
1000010XXX
32
210000h217FFFh
SA2-67
1
0
1000011XXX
32
218000h21FFFFh
SA2-68
1
0
1000100XXX
32
220000h227FFFh
SA2-69
1
0
1000101XXX
32
228000h22FFFFh
SA2-70
1
0
1000110XXX
32
230000h237FFFh
SA2-71
1
0
1000111XXX
32
238000h23FFFFh
SA2-72
1
0
1001000XXX
32
240000h247FFFh
SA2-73
1
0
1001001XXX
32
248000h24FFFFh
SA2-74
1
0
1001010XXX
32
250000h257FFFh
SA2-75
1
0
1001011XXX
32
258000h25FFFFh
SA2-76
1
0
1001100XXX
32
260000h267FFFh
SA2-77
1
0
1001101XXX
32
268000h26FFFFh
SA2-78
1
0
1001110XXX
32
270000h277FFFh
SA2-79
1
0
1001111XXX
32
278000h27FFFFh
Table 3. S29PL129J Sector Architecture (Sheet 5 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
28
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Bank 2A
SA2-80
1
0
1010000XXX
32
280000h287FFFh
SA2-81
1
0
1010001XXX
32
288000h28FFFFh
SA2-82
1
0
1010010XXX
32
290000h297FFFh
SA2-83
1
0
1010011XXX
32
298000h29FFFFh
SA2-84
1
0
1010100XXX
32
2A0000h2A7FFFh
SA2-85
1
0
1010101XXX
32
2A8000h2AFFFFh
SA2-86
1
0
1010110XXX
32
2B0000h2B7FFFh
SA2-87
1
0
1010111XXX
32
2B8000h2BFFFFh
SA2-88
1
0
1011000XXX
32
2C0000h2C7FFFh
SA2-89
1
0
1011001XXX
32
2C8000h2CFFFFh
SA2-90
1
0
1011010XXX
32
2D0000h2D7FFFh
SA2-91
1
0
1011011XXX
32
2D8000h2DFFFFh
SA2-92
1
0
1011100XXX
32
2E0000h2E7FFFh
SA2-93
1
0
1011101XXX
32
2E8000h2EFFFFh
SA2-94
1
0
1011110XXX
32
2F0000h2F7FFFh
SA2-95
1
0
1011111XXX
32
2F8000h2FFFFFh
Bank 2B
SA2-96
1
0
1100000XXX
32
300000h307FFFh
SA2-97
1
0
1100001XXX
32
308000h30FFFFh
SA2-98
1
0
1100010XXX
32
310000h317FFFh
SA2-99
1
0
1100011XXX
32
318000h31FFFFh
SA2-100
1
0
1100100XXX
32
320000h327FFFh
SA2-101
1
0
1100101XXX
32
328000h32FFFFh
SA2-102
1
0
1100110XXX
32
330000h337FFFh
SA2-103
1
0
1100111XXX
32
338000h33FFFFh
SA2-104
1
0
1101000XXX
32
340000h347FFFh
SA2-105
1
0
1101001XXX
32
348000h34FFFFh
SA2-106
1
0
1101010XXX
32
350000h357FFFh
SA2-107
1
0
1101011XXX
32
358000h35FFFFh
SA2-108
1
0
1101100XXX
32
360000h367FFFh
SA2-109
1
0
1101101XXX
32
368000h36FFFFh
SA2-110
1
0
1101110XXX
32
370000h377FFFh
SA2-111
1
0
1101111XXX
32
378000h37FFFFh
SA2-112
1
0
1110000XXX
32
380000h387FFFh
SA2-113
1
0
1110001XXX
32
388000h38FFFFh
SA2-114
1
0
1110010XXX
32
390000h397FFFh
SA2-115
1
0
1110011XXX
32
398000h39FFFFh
SA2-116
1
0
1110100XXX
32
3A0000h3A7FFFh
SA2-117
1
0
1110101XXX
32
3A8000h3AFFFFh
SA2-118
1
0
1110110XXX
32
3B0000h3B7FFFh
SA2-119
1
0
1110111XXX
32
3B8000h3BFFFFh
SA2-120
1
0
1111000XXX
32
3C0000h3C7FFFh
SA2-121
1
0
1111001XXX
32
3C8000h3CFFFFh
SA2-122
1
0
1111010XXX
32
3D0000h3D7FFFh
SA2-123
1
0
1111011XXX
32
3D8000h3DFFFFh
Table 3. S29PL129J Sector Architecture (Sheet 6 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
29
A d v a n c e I n f o r m a t i o n
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V
ID
on ad-
dress pin A9. Address pins must be as shown in
Table 5
. In addition, when
verifying sector protection, the sector address must appear on the appropriate
highest order address bits.
Table 5
shows the remaining address bits that are
don't care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7DQ0. How-
ever, the autoselect codes can also be accessed in-system through the command
register, for instances when the device is erased or programmed in a system with-
out access to high voltage on the A9 pin. The command sequence is illustrated in
Table 12
. Note: If a Bank Address (BA) (on address bits A21A19) is asserted
during the third write cycle of the autoselect command, the host system can read
autoselect data that bank and then immediately read array data from the other
bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in
Table 12
. This method does
not require V
ID
. See
"Autoselect Command Sequence"
on page 46 for more
information.
Ba
nk 2B
SA2-124
1
0
1111100XXX
32
3E0000h3E7FFFh
SA2-125
1
0
1111101XXX
32
3E8000h3EFFFFh
SA2-126
1
0
1111110XXX
32
3F0000h3F7FFFh
SA2-127
1
0
1111111000
4
3F8000h3F8FFFh
SA2-128
1
0
1111111001
4
3F9000h3F9FFFh
SA2-129
1
0
1111111010
4
3FA000h3FAFFFh
SA2-130
1
0
1111111011
4
3FB000h3FBFFFh
SA2-131
1
0
1111111100
4
3FC000h3FCFFFh
SA2-132
1
0
1111111101
4
3FD000h3FDFFFh
SA2-133
1
0
1111111110
4
3FE000h3FEFFFh
SA2-134
1
0
1111111111
4
3FF000h3FFFFFh
Table 4. Secured Silicon Sector Addresses
Sector Size
Address Range
Factory-Locked Area
64 words
000000h-00003Fh
Customer-Lockable Area
64 words
000040h-00007Fh
Table 3. S29PL129J Sector Architecture (Sheet 7 of 7)
Bank
Sector
CE1#
CE2#
Sector Address (A21-
A12)
Sector Size
(Kwords)
Address Range (x16)
30
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, BA = Bank Address, SA = Sector Address, X = Don't care.
Note: The autoselect codes may also be accessed in-system via command sequences
Table 5. Autoselect Codes for PL129J
Description
CE1# CE2# OE# WE#
A21
to
A12
A10
A9 A8
A7
A6
A5
to
A4
A3 A2 A1
A0
DQ15
to DQ0
Manufacturer
ID: Spansion
products
L
H
L
H
X
X
V
I
D
X
L
L
X
L
L
L
L
0001h
H
L
De
v
i
ce
I
D
Read
Cycle 1
L
H
L
H
X
X
V
I
D
X
L
L
L
L
L
L
H
227Eh
H
L
Read
Cycle 2
L
H
H
H
H
L
2221h
H
L
Read
Cycle 3
L
H
H
H
H
H
2200h
H
L
Sector
Protection
Verification
L
H
L
H
SA
X
V
I
D
X
L
L
L
L
L
H
L
0001h (protected),
0000h (unprotected)
H
L
Secured
Silicon
Indicator Bit
(DQ7, DQ6)
L
H
L
H
X
X
V
I
D
X
X
L
X
L
L
H
H
DQ7=1 (factory
locked),
DQ6=1 (factory and
customer locked)
H
L
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
31
A d v a n c e I n f o r m a t i o n
Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection
CE1# Control
CE2# Control
Sector Group
A21-12
Sector/Sector Block
Size
Sector Group
A21-12
Sector/Sector Block
Size
SA1-0
0000000000
4 Kwords
SA2-0SA2-3
00000XXXXX
128 (4x32) Kwords
SA1-1
0000000001
4 Kwords
SA2-4SA2-7
00001XXXXX
128 (4x32) Kwords
SA1-2
0000000010
4 Kwords
SA2-8SA2-11
00010XXXXX
128 (4x32) Kwords
SA1-3
0000000011
4 Kwords
SA2-12SA2-15
00011XXXXX
128 (4x32) Kwords
SA1-4
0000000100
4 Kwords
SA2-16SA2-19
00100XXXXX
128 (4x32) Kwords
SA1-5
0000000101
4 Kwords
SA2-20SA2-23
00101XXXXX
128 (4x32) Kwords
SA1-6
0000000110
4 Kwords
SA2-24SA2-27
00110XXXXX
128 (4x32) Kwords
SA1-7
0000000111
4 Kwords
SA2-28SA2-31
00111XXXXX
128 (4x32) Kwords
SA1-8
0000001XXX
32 Kwords
SA2-32SA2-35
01000XXXXX
128 (4x32) Kwords
SA1-9
0000010XXX
32 Kwords
SA2-36SA2-39
01001XXXXX
128 (4x32) Kwords
SA1-10
0000011XXX
32 Kwords
SA2-40SA2-43
01010XXXXX
128 (4x32) Kwords
SA1-11 - SA1-14
00001XXXXX
128 (4x32) Kwords
SA2-44SA2-47
01011XXXXX
128 (4x32) Kwords
SA1-15 - SA1-18
00010XXXXX
128 (4x32) Kwords
SA2-48SA2-51
01100XXXXX
128 (4x32) Kwords
SA1-19 - SA1-22
00011XXXXX
128 (4x32) Kwords
SA2-52SA2-55
01101XXXXX
128 (4x32) Kwords
SA1-23 - SA1-26
00100XXXXX
128 (4x32) Kwords
SA2-56SA2-59
01110XXXXX
128 (4x32) Kwords
SA1-27 - SA1-30
00101XXXXX
128 (4x32) Kwords
SA2-60SA2-63
01111XXXXX
128 (4x32) Kwords
SA1-31 - SA1-34
00110XXXXX
128 (4x32) Kwords
SA2-64SA2-67
10000XXXXX
128 (4x32) Kwords
SA1-35 - SA1-38
00111XXXXX
128 (4x32) Kwords
SA2-68SA2-71
10001XXXXX
128 (4x32) Kwords
SA1-39 - SA1-42
01000XXXXX
128 (4x32) Kwords
SA2-72SA2-75
10010XXXXX
128 (4x32) Kwords
SA1-43 - SA1-46
01001XXXXX
128 (4x32) Kwords
SA2-76SA2-79
10011XXXXX
128 (4x32) Kwords
SA1-47 - SA1-50
01010XXXXX
128 (4x32) Kwords
SA2-80SA2-83
10100XXXXX
128 (4x32) Kwords
SA1-51 - SA1-54
01011XXXXX
128 (4x32) Kwords
SA2-84SA2-87
10101XXXXX
128 (4x32) Kwords
SA1-55 - SA1-58
01100XXXXX
128 (4x32) Kwords
SA2-88SA2-91
10110XXXXX
128 (4x32) Kwords
SA1-59 - SA1-62
01101XXXXX
128 (4x32) Kwords
SA2-92SA2-95
10111XXXXX
128 (4x32) Kwords
SA1-63 - SA1-66
01110XXXXX
128 (4x32) Kwords
SA2-96SA2-99
11000XXXXX
128 (4x32) Kwords
SA1-67 - SA1-70
01111XXXXX
128 (4x32) Kwords
SA2-100SA2-103
11001XXXXX
128 (4x32) Kwords
SA1-71 - SA1-74
10000XXXXX
128 (4x32) Kwords
SA2-104SA2-107
11010XXXXX
128 (4x32) Kwords
SA1-75 - SA1-78
10001XXXXX
128 (4x32) Kwords
SA2-108SA2-111
11011XXXXX
128 (4x32) Kwords
SA1-79 - SA1-82
10010XXXXX
128 (4x32) Kwords
SA2-112SA2-115
11100XXXXX
128 (4x32) Kwords
SA1-83 - SA1-86
10011XXXXX
128 (4x32) Kwords
SA2-116SA2-119
11101XXXXX
128 (4x32) Kwords
SA1-87 - SA1-90
10100XXXXX
128 (4x32) Kwords
SA2-120SA2-123
11110XXXXX
128 (4x32) Kwords
SA1-91 - SA1-94
10101XXXXX
128 (4x32) Kwords
SA2-124
1111100XXX
32 Kwords
SA1-95 - SA1-98
10110XXXXX
128 (4x32) Kwords
SA2-125
1111101XXX
32 Kwords
SA1-99 - SA1-102
10111XXXXX
128 (4x32) Kwords
SA2-126
1111110XXX
32 Kwords
SA1-103 - SA1-106
11000XXXXX
128 (4x32) Kwords
SA2-127
1111111000
4 Kwords
SA1-107 - SA1-110
11001XXXXX
128 (4x32) Kwords
SA2-128
1111111001
4 Kwords
SA1-111 - SA1-114
11010XXXXX
128 (4x32) Kwords
SA2-129
1111111010
4 Kwords
SA1-115 - SA1-118
11011XXXXX
128 (4x32) Kwords
SA2-130
1111111011
4 Kwords
SA1-119 - SA1-122
11100XXXXX
128 (4x32) Kwords
SA2-131
1111111100
4 Kwords
SA1-123 - SA1-126
11101XXXXX
128 (4x32) Kwords
SA2-132
1111111101
4 Kwords
SA1-127 - SA1-130
11110XXXXX
128 (4x32) Kwords
SA2-133
1111111110
4 Kwords
SA1-131 - SA1-134
11111XXXXX
128 (4x32) Kwords
SA2-134
1111111111
4 Kwords
32
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion program-
ming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See
"Se-
cured Silicon Sector Addresses"
on page 29 for details.
Sector Protection
The PL129J features several levels of sector protection, which can disable both
the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled pro-
tection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA1-
133, SA1-134, SA2-0 and SA2-1.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The cus-
tomer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method is used. If the Persistent Sector Protection
method is desired, programming the Persistent Sector Protection Mode Locking
Bit permanently sets the device to the Persistent Sector Protection mode. If the
Password Sector Protection method is desired, programming the Password Mode
Locking Bit permanently sets the device to the Password Sector Protection mode.
It is not possible to switch between the two protection modes once a locking bit
has been set. One of the two modes must be selected when the device is first
Table 7. Sector Protection Schemes
DYB
PPB
PPB Lock
Sector State
0
0
0
Unprotected--PPB and DYB are changeable
0
0
1
Unprotected--PPB not changeable, DYB is changeable
0
1
0
Protected--PPB and DYB are changeable
1
0
0
1
1
0
0
1
1
Protected--PPB not changeable, DYB is changeable
1
0
1
1
1
1
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
33
A d v a n c e I n f o r m a t i o n
programmed. This prevents a program or virus from later setting the Password
Mode Locking Bit, which would cause an unexpected shift from the default Per-
sistent Sector Protection Mode into the Password Protection Mode.
The device is shipped with all sectors unprotected. Optional Spansion program-
ming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Au-
toselect Mode for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection
method in previous flash devices. This new method provides three different sec-
tor protection states:
Persistently Locked--The sector is protected and cannot be changed.
Dynamically Locked--The sector is protected and can be changed by a simple
command.
Unlocked--The sector is unprotected and can be changed by a simple com-
mand.
To achieve these states, three types of "bits" are used:
Persistent Protection Bit
Persistent Protection Bit Lock
Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four
sectors (see the sector address tables for specific sector protection groupings).
All 4 Kword boot-block sectors have individual sector Persistent Protection Bits
(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB
Write Command.
The device erases all PPBs in parallel. If any PPB requires erasure, the device
must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth-
erwise, a previously erased sector PPBs can potentially be over-erased. The flash
device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to
"1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable.
There is only one PPB Lock bit per device. The PPB Lock is cleared after power-
up or hardware reset. There is no command sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYBs is "0". Each DYB is individually modifiable through
the DYB Write Command.
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and
PPB Lock is defaulted to power up in the cleared state meaning the PPBs are
changeable.
When the device is first powered on the DYBs power up cleared (sectors not pro-
tected). The Protection State for each sector is determined by the logical OR of
34
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
the PPB and the DYB related to that sector. For the sectors that have the PPBs
cleared, the DYBs control whether or not the sector is protected or unprotected.
By issuing the DYB Write command sequences, the DYBs are set or cleared, thus
placing each sector in the protected or unprotected state. These are the so-called
Dynamic Locked or Unlocked states. These states are called dynamic states be-
cause it is very easy to switch back and forth between the protected and
unprotected conditions. This allows software to easily protect sectors against in-
advertent changes yet does not prevent the easy removal of protection when
changes are needed. The DYBs maybe set or cleared as often as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The
PPBs retain their state across power cycles because the PPBs are non-volatile. In-
dividual PPBs are set with a command but must all be cleared as a group through
a complex sequence of program and erasing commands. The PPBs are also lim-
ited to 100 erase cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are pro-
grammed to the desired settings, the PPB Lock may be set to "1". Setting the PPB
Lock disables all program and erase commands to the non-volatile PPBs. In ef-
fect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear
the PPB Lock is to go through a power cycle. System boot code can determine if
any changes to the PPB are needed; for example, to allow new system code to
be downloaded. If no changes are needed then the boot code can set the PPB
Lock to disable any further changes to the PPBs during system operation.
The WP#/ACC write protect pin adds a final level of hardware protection to sec-
tors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible
to change the contents of these sectors. These sectors generally hold system
boot code. The WP#/ACC pin can prevent any changes to the boot code that could
override the choices made while setting up sector protection during system
initialization.
For customers who are concerned about malicious viruses there is another level
of security - the persistently locked state. To persistently protect a given sector
or sector group, the PPBs associated with that sector need to be set to "1". Once
all PPBs are programmed to the desired settings, the PPB Lock should be set to
"1". Setting the PPB Lock automatically disables all program and erase commands
to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their cur-
rent state. The only way to clear the PPB Lock is to go through a power cycle.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Write command se-
quence is all that is necessary. The DYB write command for the dynamic sectors
switch the DYBs to signify protected and unprotected, respectively. If there is a
need to change the status of the persistently locked sectors, a few more steps
are required. First, the PPB Lock bit must be disabled by either putting the device
through a power-cycle, or hardware reset. The PPBs can then be changed to re-
flect the desired settings. Setting the PPB lock bit once again lock the PPBs, and
the device operates normally again.
The best protection is achieved by executing the PPB lock bit set command early
in the boot code, and protect the boot code by holding WP#/ACC = VIL.
Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating
to the status of the sector.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
35
A d v a n c e I n f o r m a t i o n
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and
the protection can not be removed until the next power cycle clears the PPB lock.
If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB
then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sec-
tor enables status polling for approximately 1 s before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 s
after which the device returns to read mode without having erased the protected
sector.
The programming of the DYB, PPB, and PPB lock for a given sector can be verified
by writing a DYB/PPB/PPB lock verify command to the device. There is an alter-
native means of reading the protection status. Take RESET# to VIL and hold WE#
at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of
the PPBs). Scanning the addresses (A18A11) while (A6, A1, A0) = (0, 1, 0) pro-
duces a logical `1" code at device output DQ0 for a protected sector or a "0" for
an unprotected sector. In this mode, the other addresses are don't cares. Address
location with A1 = VIL are reserved for autoselect manufacturer and device
codes.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking
bit exists to guarantee that the device remain in software sector protection. Once
set, the Persistent Sector Protection locking bit prevents programming of the
password protection mode locking bit. This guarantees that a hacker could not
place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of se-
curity than the Persistent Sector Protection Mode. There are two main differences
between the Persistent Sector Protection and the Password Sector Protection
Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB Lock
bit set to the locked state, rather than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password
to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
Once the Password Mode Locking Bit is set, the password is permanently set with
no means to read, program, or erase it. The password is used to clear the PPB
Lock bit. The Password Unlock command must be written to the flash, along with
a password. The flash device internally compares the given password with the
pre-programmed password. If they match, the PPB Lock bit is cleared, and the
PPBs can be altered. If they do not match, the flash device does nothing. There
is a built-in 2 s delay for each "password check." This delay is intended to thwart
any efforts to run a program that tries all possible combinations in order to crack
the password.
36
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first
program the password. The password may be correlated to the unique Electronic
Serial Number (ESN) of the particular flash device. Each ESN is different for every
flash device; therefore each password should be different for every flash device.
While programming in the password region, the customer may perform Password
Verify operations.
Once the desired password is programmed in, the customer must then set the
Password Mode Locking Bit. This operation achieves two objectives:
Permanently sets the device to operate using the Password Protection Mode. It is
not possible to reverse this function.
Disables all further commands to the password region. All program, and read op-
erations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Protection
method is desired when setting the Password Mode Locking Bit. More importantly,
the user must be sure that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations are disabled, there is no
means to verify what the password is afterwards. If the password is lost after set-
ting the Password Mode Locking Bit, there is not any way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password
on the DQ bus and further password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persis-
tent Sector Protection Locking Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Verify commands (see "Password Verify
Command"). The password function works in conjunction with the Password
Mode Locking Bit, which when set, prevents the Password Verify command from
reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper
two and lower two sectors(PL127J: 0, 1, 268, and 269, PL064J: 0, 1, 140, and
141, PL032J: 0, 1, 76, and 77, PL129J: SA1-133, SA1-134,SA2-0 and SA2-1)
without using V
ID
. This function is provided by the WP# pin and overrides the pre-
viously discussed method,
"High Voltage Sector Protection"
on page 37.
If the system asserts V
IL
on the WP#/ACC pin, the device disables program and
erase functions in the two outermost 4 Kword sectors on both ends of the flash
array independent of whether it was previously protected or unprotected.
If the system asserts V
IH
on the WP#/ACC pin, the device reverts the upper two
and lower two sectors to whether they were last set to be protected or unpro-
tected. That is, sector protection or unprotection for these sectors depends on
whether they were last protected or unprotected using the method described in
"High Voltage Sector Protection"
on page 37.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
37
A d v a n c e I n f o r m a t i o n
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of
the Password Mode Locking Bit after power-up reset. If the Password Mode Lock
Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the
ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution of the Password Unlock
command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert-
ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock
Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit
is not set.
If the Password Mode Locking Bit is not set, including Persistent Protection Mode,
the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is
set by issuing the PPB Lock Bit Set command. Once set the only means for clear-
ing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password
Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming
equipment. The procedure requires high voltage (V
ID
) to be placed on the RE-
SET# pin. Refer to
Figure 1
for details on this procedure. Note that for sector
unprotect, all unprotected sectors must first be protected prior to the first sector
write cycle.
38
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
Sector Protect:
Write 60h to sector
address with
A7-A0 =
00000010
Set up sector
address
Wait 100 s
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
00000010
Read from
sector address
with A7-A0 =
00000010
START
PLSCNT = 1
RESET# = V
ID
Wait 4
s
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
Sector Unprotect:
Write 60h to sector
address with
A7-A0 =
01000010
Set up first sector
address
Wait 1.2 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
00000010
Read from
sector address
with A7-A0 =
00000010
START
PLSCNT = 1
RESET# = V
ID
Wait 4
s
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm
Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
39
A d v a n c e I n f o r m a t i o n
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to
V
ID
. During this mode, formerly protected sectors can be pro-
grammed or erased by selecting the sector addresses. Once V
ID
is removed from
the RESET# pin, all the previously protected sectors are protected again.
Figure 2
shows the algorithm, and
Figure 21
shows the timing diagrams, for this
feature. While PPB lock is set, the device cannot enter the Temporary Sector Un-
protection Mode.
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN) The
128-word Secured Silicon sector is divided into 64 factory-lockable words that
can be programmed and locked by the customer. The Secured Silicon sector is
located at addresses 000000h-00007Fh in both Persistent Protection mode and
Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the
factory-locked and customer locked status of the part.
The system accesses the Secured Silicon Sector through a command sequence
(see
"Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence"
on page 46). After the system has written the Enter Secured Silicon
Sector command sequence, it may read the Secured Silicon Sector by using the
addresses normally occupied by the boot sectors. This mode of operation contin-
ues until the system issues the Exit Secured Silicon Sector command sequence,
or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to the normal address space. Note
that the ACC function and unlock bypass modes are not available when the Se-
cured Silicon Sector is enabled.
Notes:
1. All protected sectors are unprotected (If WP#/ACC = V
IL
, upper two and lower
two sectors remain protected).
2. All previously protected sectors are protected once again
Figure 2. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
40
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Factory-Locked Area (64 words)
The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is
locked when the part is shipped, whether or not the area was programmed at the
factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is perma-
nently set to a "1". Optional Spansion programming services can program the
factory-locked area with a random ESN, a customer-defined code, or any combi-
nation of the two. Because only FASL can program and protect the factory-locked
area, this method ensures the security of the ESN once the product is shipped to
the field. Contact your local sales office for details on using Spansion's program-
ming services. Note that the ACC function and unlock bypass modes are not
available when the Secured Silicon sector is enabled.
Customer-Lockable Area (64 words)
The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is
shipped unprotected, which allows the customer to program and optionally lock
the area as appropriate for the application. The Secured Silicon Sector Customer-
locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1"
by issuing the Secured Silicon Protection Bit Program Command. The Secured Sil-
icon Sector can be read any number of times, but can be programmed and locked
only once. Note that the accelerated programming (ACC) and unlock bypass func-
tions are not available when programming the Secured Silicon Sector.
The Customer-lockable Secured Silicon Sector area can be protected using one
of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command se-
quence, and then follow the in-system sector protect algorithm as shown in
Figure 1
, except that RESET# may be at either V
IH
or V
ID
. This allows in-sys-
tem protection of the Secured Silicon Sector Region without raising any de-
vice pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
To verify the protect/unprotect status of the Secured Silicon Sector, follow the
algorithm shown in
Figure 3
.
Once the Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence to return to reading and
writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked,
there is no procedure available for unlocking the Secured Silicon Sector area and
none of the bits in the Secured Silicon Sector memory space can be modified in
any way.
Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured
Silicon Sector memory area. Once set, the Secured Silicon Sector memory area
contents are non-modifiable.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
41
A d v a n c e I n f o r m a t i o n
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not ini-
tiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE1# = CE2# = V
IH
or WE# = V
IH
. To initiate a write cycle, CE1# / CE2# and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# (CE1#, CE2# in PL129J) = V
IL
and OE# = V
IH
during power up,
the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
Figure 3. Secured Silicon Sector Protect Verify
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
V
IH
or V
ID
Wait 1
s
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove V
IH
or V
ID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
42
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in
Table 8
,
Table 9
,
Table 10
, and
Table 11
. To terminate reading CFI data, the system must write the
reset command. The CFI Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in
Table 8
,
Table 9
,
Table 10
, and
Table 11
. The
system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Contact your local sales office for copies of these documents.
Table 8. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string "QRY"
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
43
A d v a n c e I n f o r m a t i o n
Table 9. System Interface String
Addresses
Data
Description
1Bh
0027h
V
CC
Min. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Ch
0036h
V
CC
Max. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Dh
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
0003h
Typical timeout per single byte/word write 2
N
s
20h
0000h
Typical timeout for Min. size buffer write 2
N
s (00h = not supported)
21h
0009h
Typical timeout per individual block erase 2
N
ms
22h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
0004h
Max. timeout for byte/word write 2
N
times typical
24h
0000h
Max. timeout for buffer write 2
N
times typical
25h
0004h
Max. timeout per individual block erase 2
N
times typical
26h
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Table 10. Device Geometry Definition
Addresses
Data
Description
27h
0018h (PL129J)
Device Size = 2
N
byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
00FDh (PL129J)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
32h
33h
34h
0000h
0000h
0001h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Table 11. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string "PRI"
44
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
43h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
0033h
Minor version number, ASCII (reflects modifications to the CFI table)
45h
TBD
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0007h (PLxxxJ)
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
4Ah
00E7h (PL129J)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0002h (PLxxxJ)
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh
0001h
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = Both top and bottom boot with write protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
50h
0001h
Program Suspend
0 = Not supported, 1 = Supported
57h
0004h
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
58h
0027h (PL129J)
Bank 1 Region Information
X = Number of Sectors in Bank 1
59h
0060h (PL129J)
Bank 2 Region Information
X = Number of Sectors in Bank 2
5Ah
0060h (PL129J)
Bank 3 Region Information
X = Number of Sectors in Bank 3
5Bh
0027h (PL129J)
Bank 4 Region Information
X = Number of Sectors in Bank 4
Table 11. Primary Vendor-Specific Extended Query (Continued)
Addresses
Data
Description
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
45
A d v a n c e I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations.
Table 12
defines the valid register command
sequences. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in
PL129J), whichever happens later. All data is latched on the rising edge of WE#
or CE# (CE1# / CE2# in PL129J), whichever happens first. See
AC Characteristics
for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See
"Erase Suspend/Erase Re-
sume Commands"
on page 50 for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See "
Reset Command
," for more
information.
See
"Requirements for Reading Array Data"
on page 19 in
"Device Bus Opera-
tions"
for more information. The
AC Characteristics
table provides the read
parameters, and
Figure 12
shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don't cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
46
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and device codes, and determine whether or not a sector is protected.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the
other bank.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the au-
toselect command. The bank then enters the autoselect mode. The system may
read any number of autoselect codes without reinitiating the command sequence.
Table 12
shows the address and data requirements. To determine sector protec-
tion information, the system must write to the appropriate bank address (BA) and
sector address (SA).
The system must write the reset command to return to the read mode (or erase-
suspend-read mode if the bank was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
The Secured Silicon Sector region provides a secured data area containing a ran-
dom, eight word electronic serial number (ESN). The system can access the
Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. The Secured Silicon Sector is not accessible when
the device is executing an Embedded Program or embedded Erase algorithm.
Table 12
shows the address and data requirements for both command sequences.
Also see,
"Secured Silicon Sector Flash Memory Region"
on page 39 for further in-
formation. Note: The ACC function and unlock bypass modes are not available
when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up com-
mand. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further con-
trols or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin.
Table 12
shows the address and
data requirements for the program command sequence. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7, DQ6, or RY/BY#. See
"Write
Operation Status"
on page 56 for information on these status bits.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
47
A d v a n c e I n f o r m a t i o n
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Sector, autoselect and CFI functions are unavailable when the Secured Sil-
icon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from "0" back to a "1." Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is
still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster
than using the standard program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cycle in this se-
quence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time.
Table 12
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (
Table 13
)
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts V
HH
on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at V
HH
any operation other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
Figure 4
illustrates the algorithm for the program operation. See the
Erase/Pro-
gram Operations
table in
AC Characteristics
for parameters, and
Figure 14
for
timing diagrams.
48
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations.
Table 12
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
"Write Op-
eration Status"
on page 56 for information on these status bits.
Any commands written during the chip erase operation are ignored. Note that Se-
cured Silicon Sector, autoselect, and CFI functions are unavailable when a
[program/erase] operation is in progress. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase com-
mand sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5
illustrates the algorithm for the erase operation. See the
Erase/Program
Operations
tables in
AC Characteristics
for parameters, and
Figure 16
for timing
diagrams.
Note: See
Table 12
for program command sequence.
Figure 4. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
49
A d v a n c e I n f o r m a t i o n
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command.
Table 12
shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 s, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. If any com-
mand other than 30h, B0h, F0h is input during the time-out period, the
normal operation cannot be guaranteed. The system must rewrite the com-
mand sequence and any additional addresses and commands. Note that Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See
"DQ3: Sector Erase Timer"
on page 61). The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See
"Write Operation Status"
on
page 56 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5
illustrates the algorithm for the erase operation. See the
Erase/Program
Operations
tables in
AC Characteristics
for parameters, and
Figure 16
for timing
diagrams.
50
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writing this command. This com-
mand is valid only during the sector erase operation, including the 80 s time-out
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 35 s to suspend the erase operation. How-
ever, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation. Addresses are "don't-cares" when writing the Erase suspend
command.
After the erase operation has been suspended, the bank enters the erase-sus-
pend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device "erase suspends" all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces sta-
tus information on DQ7DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See
"Write Operation Status"
on page 56 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the program
Notes:
1. See
Table 12
for erase command sequence.
2. See
"DQ3: Sector Erase Timer"
on page 61 for information on the sector erase
timer.
Figure 5. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
51
A d v a n c e I n f o r m a t i o n
operation using the DQ7 or DQ6 status bits, just as in the standard Word Program
operation. See
"Write Operation Status"
on page 56 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect com-
mand sequence. The device allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored in the memory array. When
the device exits the autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Secured Silicon Sector Ad-
dresses"
on page 29 and
"Autoselect Command Sequence"
on page 46 for details.
To resume the sector erase operation, the system must write the Erase Resume
command (address bits are don't care). The bank address of the erase-sus-
pended bank is required when writing this command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
Password Program Command
The Password Program Command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. Four Password Program commands are required to program the password.
The system must enter the unlock cycle, password program command (38h) and
the program address/data for each portion of the password when programming.
There are no provisions for entering the 2-cycle unlock cycle, the password pro-
gram command, and all the password data. There is no special addressing order
required for programming the password. Also, when the password is undergoing
programming, Simultaneous Operation is disabled. Read operations to any mem-
ory location will return the programming status. Once programming is complete,
the user must issue a Read/Reset command to return the device to normal oper-
ation. Once the Password is written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Password Program Command is
only capable of programming "0"s. Programming a "1" after a cell is programmed
as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell
remaining as a "0". The password is all ones when shipped from the factory. All
64-bit password combinations are valid as a password.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always drive all F's onto the DQ data bus.
The Password Verify command is permitted if the Secured Silicon sector is en-
abled. Also, the device will not operate in Simultaneous Operation when the
Password Verify command is executed. Only the password is returned regardless
of the bank address. The lower two address bits (A1-A0) are valid during the
Password Verify. Writing the Read/Reset command returns the device back to
normal operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the
Password Protection Mode Locking Bit, which prevents further verifies or updates
to the Password. Once programmed, the Password Protection Mode Locking Bit
cannot be erased! If the Password Protection Mode Locking Bit is verified as pro-
gram without margin, the Password Protection Mode Locking Bit Program
52
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
command can be executed to improve the program margin. Once the Password
Protection Mode Locking Bit is programmed, the Persistent Sector Protection
Locking Bit program circuitry is disabled, thereby forcing the device to remain in
the Password Protection mode. Exiting the Mode Locking Bit Program command
is accomplished by writing the Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs
the Persistent Sector Protection Mode Locking Bit, which prevents the Password
Mode Locking Bit from ever being programmed. If the Persistent Sector Protec-
tion Mode Locking Bit is verified as programmed without margin, the Persistent
Sector Protection Mode Locking Bit Program Command should be reissued to im-
prove program margin. By disabling the program circuitry of the Password Mode
Locking Bit, the device is forced to remain in the Persistent Sector Protection
mode of operation, once this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by writing the Read/Reset
command.
Secured Silicon Sector Protection Bit Program Command
The Secured Silicon Sector Protection Bit Program Command programs the Se-
cured Silicon Sector Protection Bit, which prevents the Secured Silicon sector
memory from being cleared. If the Secured Silicon Sector Protection Bit is verified
as programmed without margin, the Secured Silicon Sector Protection Bit Pro-
gram Command should be reissued to improve program margin. Exiting the V
CC
-
level Secured Silicon Sector Protection Bit Program Command is accomplished by
writing the Read/Reset command.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either
at reset or if the Password Unlock command was successfully executed. There is
no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared
unless the device is taken through a power-on clear or the Password Unlock com-
mand is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the
DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected
as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command
is accomplished by writing the Read/Reset command (only in the Persistent Pro-
tection Mode).
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high
order address bits (AmaxA12) are issued at the same time as the code 01h or
00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write
cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or
PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the
DYB Write command is accomplished by writing the Read/Reset command.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs
can be unlocked for modification, thereby allowing the PPBs to become accessible
for modification. The exact password must be entered in order for the unlocking
function to occur. This command cannot be issued any faster than 2
s at a time
to prevent a hacker from running through all 64-bit combinations in an attempt
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
53
A d v a n c e I n f o r m a t i o n
to correctly match a password. If the command is issued before the 2
s execu-
tion window for each portion of the unlock, the command will be ignored.
Once the Password Unlock command is entered, the RY/BY# indicates that the
device is busy. Approximately 1 s is required for each portion of the unlock. Once
the first portion of the password unlock completes (RY/BY# is not low or DQ6
does not toggle when read), the next part of the password is written. The system
must thus monitor RY/BY# or the status bits to confirm when to write the next
portion of the password. Seven cycles are required to successfully clear the PPB
Lock Bit.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is
individually programmed (but is bulk erased with the other PPBs). The specific
sector address (A22A12) are written at the same time as the program command
60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for
the sector, the PPB Program command will not execute and the command will
time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether
the PPB has been programmed with margin. If the PPB has been programmed
without margin, the program command should be reissued to improve the pro-
gram margin. Also note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The PPB Program command does not follow the Embedded Program algorithm.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means
for individually erasing a specific PPB. Unlike the PPB program, no specific sector
address is required. However, when the PPB erase command is written all Sector
PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command
will not execute and the command will time-out without erasing the PPBs. After
erasing the PPBs, two additional cycles are needed to determine whether the PPB
has been erased with margin. If the PPBs has been erased without margin, the
erase command should be reissued to improve the program margin.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All
PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure
may occur making it difficult to program the PPB at a later time. Also note that
the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the
PPBs beyond 100 cycles is not guaranteed.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that
is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is
protected regardless of the value of the DYB. If the PPB is cleared, setting the
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank address
is latched when the command is written.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit
that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector
is protected regardless of the value of the DYB. If the PPB is cleared, setting the
54
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank address
is latched when the command is written.
Command
The programming of either the PPB or DYB for a given sector or sector group can
be verified by writing a Sector Protection Status command to the device.
Note that there is no single command to independently verify the programming
of a DYB for a given sector group.
Command Definitions Tables
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by Amax:A19.
PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens
later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse,
whichever happens first.
RA = Read Address (Amax:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.
WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#.
X = Don't care
Notes:
1. See
Table 1
for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
Table 12. Memory Array Command Definitions
Command (Notes)
Cy
cle
s
Bus Cycles (Notes
1
4
)
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (
Note 5
)
1
RA
RD
Reset (
Note 6
)
1
XXX
F0
Autoselect
(
Note 7
)
Manufacturer ID
4
555
AA
2AA
55
(BA)
555
90
(BA)
X00
01
Device ID (
Note 10
)
6
555
AA
2AA
55
(BA)
555
90
(BA)
X01
227E
(BA)
X0E
(
Note
10
)
(BA)
X0F
(
Note
10
)
Secured Silicon Sector
Factory Protect (
Note
8
)
4
555
AA
2AA
55
(BA)
555
90
X03
(
Note
8
)
Sector Group Protect
Verify (
Note 9
)
4
555
AAA
2AA
55
(BA)
555
90
(SA)
X02
XX00/
XX01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (
Note 11
)
1
BA
B0
Program/Erase Resume (
Note 12
)
1
BA
30
CFI Query (
Note 13
)
1
55
98
Accelerated Program (
Note 15
)
2
XX
A0
PA
PD
Unlock Bypass Entry (
Note 15
)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (
Note 15
)
2
XX
A0
PA
PD
Unlock Bypass Erase (
Note 15
)
2
XX
80
XX
10
Unlock Bypass CFI (Notes
13
,
15
)
1
XX
98
Unlock Bypass Reset (
Note 15
)
2
XXX
90
XXX
00
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
55
A d v a n c e I n f o r m a t i o n
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don't cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)
when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).
7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID
or device ID information. See
"Autoselect Command Sequence"
on page 46 for more information.
8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.
9. The data is 00h for an unprotected sector group and 01h for a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. PL129J (X0Eh = 2221h, X0Fh = 2200h).
11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.
12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or when device is in autoselect mode.
14. WP#/ACC must be at V
ID
during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required
to return to the reading array.
Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
Table 13. Sector Protection Command Definitions
Command (Notes)
Cy
cle
s
Bus Cycles (Notes
1
-
4
)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset
1
XXX
F0
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured Silicon Sector Exit
4
555
AA
2AA
55
555
90
XX
00
Secured Silicon Protection Bit Program
(Notes
5
,
6
)
6
555
AA
2AA
55
555
60
OW
68
OW
48
OW
RD
(0)
Secured Silicon Protection Bit Status
5
555
AA
2AA
55
555
60
OW
48
OW
RD
(0)
Password Program (Notes
5
,
7
,
8
)
4
555
AA
2AA
55
555
38
XX
[0-3]
PD
[0-3]
Password Verify (Notes
6
,
8
,
9
)
4
555
AA
2AA
55
555
C8
PWA
[0-3]
PWD
[0-3]
Password Unlock (Notes
7
,
10
,
11
)
7
555
AA
2AA
55
555
28
PWA
[0]
PWD
[0]
PWA
[1]
PWD
[1]
PWA
[2]
PWD
[2]
PWA
[3]
PWD
[3]
PPB Program (Notes
5
,
6
,
12
)
6
555
AA
2AA
55
555
60
(SA)
WP
68
(SA)
WP
48
(SA)
WP
RD
(0)
PPB Status
4
555
AA
2AA
55
555
90
(SA)
WP
RD
(0)
All PPB Erase (Notes
5
,
6
,
13
,
14
)
6
555
AA
2AA
55
555
60
WP
60
(SA)
40
(SA)
WP
RD
(0)
PPB Lock Bit Set
3
555
AA
2AA
55
555
78
PPB Lock Bit Status (
Note 15
)
4
555
AA
2AA
55
555
58
SA
RD
(1)
DYB Write (
Note 7
)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (
Note 7
)
4
555
AA
2AA
55
555
48
SA
X0
DYB Status (
Note 6
)
4
555
AA
2AA
55
555
58
SA
RD
(0)
PPMLB Program (Notes
5
,
6
,
12
)
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD
(0)
PPMLB Status (
Note 5
)
5
555
AA
2AA
55
555
60
PL
48
PL
RD
(0)
SPMLB Program (Notes
5
,
6
,
12
)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD
(0)
SPMLB Status (
Note 5
)
5
555
AA
2AA
55
555
60
SL
48
SL
RD
(0)
56
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don't care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See
Table 1
for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don't cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =
0 in cycle 6, program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 s timeout is required between any two portions of password.
12. A 100 s timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase
command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase opera-
tion: DQ2, DQ3, DQ5, DQ6, and DQ7.
Table 14
and the following subsections describe
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Pro-
gram or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device out-
puts the datum programmed to DQ7. The system must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns
to the read mode.
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
57
A d v a n c e I n f o r m a t i o n
During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 s, then the
bank returns to the read mode. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15DQ0 on the following read cycles. Just prior to the
completion of an Embedded Program or Erase operation, DQ7 may change asyn-
chronously with DQ15DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15DQ0 may be still invalid. Valid
data on DQ15DQ0 appears on successive read cycles.
Table 14
shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm.
Figure 18
in
AC Characteristics
shows the Data# Polling timing
diagram.
58
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to V
CC
.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.
Table 14
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is
any sector address within the sector being erased. During chip erase, a valid address is
any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously
with DQ5.
Figure 6. Data# Polling Algorithm
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7DQ0
Addr = VA
Read DQ7DQ0
Addr = VA
DQ7 = Data?
START
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
59
A d v a n c e I n f o r m a t i o n
During an Embedded Program or Erase algorithm operation, successive read cy-
cles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 400 s, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see
"DQ7: Data# Polling"
on page 56).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 s after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 14
shows the outputs for Toggle Bit I on DQ6.
Figure 7
shows the toggle bit
algorithm.
Figure 19
in
"Read Operation Timings"
shows the toggle bit timing di-
agrams.
Figure 20
shows the differences between DQ2 and DQ6 in graphical
form. See also "
DQ2: Toggle Bit II
".
Figure 7. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle?
Read Byte Twice
(DQ7DQ0)
Address = VA
Read Byte
(DQ7DQ0)
Address =VA
Read Byte
(DQ7DQ0)
Address =VA
60
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE1# / CE2# to
control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device
is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode
information. See
Table 14
to compare outputs for DQ2 and DQ6.
Figure 7
shows the toggle bit algorithm in flowchart form, and the
"DQ2: Toggle
Bit II"
explains the algorithm. See also "
DQ6: Toggle Bit I
."
Figure 19
shows the
toggle bit timing diagram.
Figure 20
shows the differences between DQ2 and DQ6
in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 7
for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see
"DQ5: Exceeded Timing Limits"
). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling,
the device did not completed the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of
Figure 7
).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified inter-
nal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the
program or erase cycle was not successfully completed.
The device may output a "1" on DQ5 if the system tries to program a "1" to a
location that was previously programmed to "0." Only an erase operation can
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle
bit may stop toggling as DQ5 changes to "1." See
"DQ6: Toggle Bit I"
and
"DQ2: Tog-
gle Bit II"
for more information.
Figure 7. Toggle Bit Algorithm
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
61
A d v a n c e I n f o r m a t i o n
change a "0" back to a "1." Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a "1."
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a "0" to a "1." See also
"Sector Erase Command Sequence"
on page 49.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is "0," the device accepts additional
sector erase commands. To ensure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second status check, the last com-
mand might not have been accepted.
Table 14
shows the status of DQ3 relative to the other status bits.
Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits.
"DQ5: Exceeded Timing Limits"
for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
Table 14. Write Operation Status
Status
DQ7
(
Note 2
)
DQ6
DQ5
(
Note 1
)
DQ3
DQ2
(
Note 2
)
RY/BY#
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
62
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . 65C to +150C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . 65C to +125C
Voltage with Respect to Ground
V
CC
(
Note 1
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +4.0 V
A9, OE#, and RESET# (
Note 2
) . . . . . . . . . . . . . . . . . . . . . 0.5 V to +13.0 V
WP#/ACC (
Note 2
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +10.5 V
All other pins (
Note 1
) . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V
CC
+0.5 V
Output Short Circuit Current (
Note 3
). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions,
input or I/O pins may overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum
DC voltage on input or I/O pins is V
CC
+0.5 V. During voltage transitions, input or
I/O pins may overshoot to V
CC
+2.0 V for periods up to 20 ns. See
Figure 8
.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is 0.5 V.
During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V
SS
to 2.0 V for periods of up to 20 ns. See
Figure 8
. Maximum DC input voltage on
pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods
up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure of the device to absolute max-
imum rating conditions for extended periods may affect device reliability.
Figure 8. Maximum Overshoot Waveforms
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
63
A d v a n c e I n f o r m a t i o n
Operating Ranges
Operating ranges define those limits between which the functionality of the de-
vice is guaranteed.
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . 55C to +125C
Supply Voltages
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.73.6 V
V
IO
or 2.73.6 V
Notes:
For all AC and DC specifications, V
IO
= V
CC
; contact your local sales office for other
V
IO
options.
64
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
Notes:
1. The I
CC
current listed is typically less than 5 mA/MHz, with OE# at V
IH
.
2. Maximum I
CC
specifications are tested with V
CC
= V
CCmax
.
3. I
CC
active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30 ns. Typical sleep
mode current is 1 mA.
5. Not 100% tested.
6. In S29PL129J there are two CE# (CE1#, CE2#).
7. Valid CE1#/CE2# conditions: (CE1# = V
IL,
CE2# = V
IH,
) or (CE1# = V
IH,
CE2# = V
IL
) or (CE1# = V
IH,
CE2# = V
IH
)
Table 15. CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
1.0
A
I
LIT
A9, OE#, RESET# Input Load Current
V
CC
= V
CC max
; V
ID
= 12.5 V
35
A
I
LR
Reset Leakage Current
V
CC
= V
CC max
; V
ID
= 12.5 V
35
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
, OE# = V
IH
V
CC
= V
CC max
1.0
A
I
CC1
V
CC
Active Read Current (Notes
1
,
2
)
OE# = V
IH
, V
CC
= V
CC max
(Note 1)
5 MHz
20
30
mA
10 MHz
45
55
I
CC2
V
CC
Active Write Current (Notes
2
,
3
)
OE# = V
IH
, WE# = V
IL
15
25
mA
I
CC3
V
CC
Standby Current (
Note 2
)
CE#, RESET#, WP#/ACC
= V
IO
0.3 V
0.2
5
A
I
CC4
V
CC
Reset Current (
Note 2
)
RESET# = V
SS
0.3 V
0.2
5
A
I
CC5
Automatic Sleep Mode (Notes
2
,
4
)
V
IH
= V
IO
0.3 V;
V
IL
= V
SS
0.3 V
0.2
5
A
I
CC6
V
CC
Active Read-While-Program Current
(Notes
1
,
2
)
OE# = V
IH
,
5 MHz
21
45
mA
10 MHz
46
70
I
CC7
V
CC
Active Read-While-Erase Current
(Notes
1
,
2
)
OE# = V
IH
,
5 MHz
21
45
mA
10 MHz
46
70
I
CC8
V
CC
Active Program-While-Erase-
Suspended Current (Notes
2
,
5
)
OE# = V
IH
17
25
mA
I
CC9
V
CC
Active Page Read Current (
Note 2
)
OE# = V
IH
, 8 word Page Read
10
15
mA
V
IL
Input Low Voltage
V
IO
= 2.73.6 V
0.5
0.8
V
V
IH
Input High Voltage
V
IO
= 2.73.6 V
2.0
V
CC
+0.3
V
V
HH
Voltage for ACC Program Acceleration
V
CC
= 3.0 V 10%
8.5
9.5
V
V
ID
Voltage for Autoselect and Temporary
Sector Unprotect
V
CC
= 3.0 V 10%
11.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 2.0 mA, V
CC
= V
CC min
, V
IO
= 2.73.6
V
0.4
V
V
OH
Output High Voltage
I
OH
= 2.0 mA, V
CC
= V
CC min
, V
IO
= 2.73.6
V
2.4
V
V
LKO
Low V
CC
Lock-Out Voltage (
Note 5
)
2.3
2.5
V
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
65
A d v a n c e I n f o r m a t i o n
AC Characteristics
Test Conditions
Switching Waveforms
Note: Diodes are IN3064 or equivalent
Figure 9. Test Setups
Table 16. Test Specifications
Test Condition
All Speeds
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
pF
Input Rise and Fall Times
V
IO
= 3.0 V
5
ns
Input Pulse Levels
V
IO
= 3.0 V
0.03.0
V
Input timing measurement reference levels
V
IO
/2
V
Output timing measurement reference levels
V
IO
/2
V
Table 17. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
2.7 k
C
L
6.2 k
3.6 V
Device
Under
Test
V
IO
= 3.0 V
66
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
VCC RampRate
All DC characteristics are specified for a V
CC
ramp rate > 1V/100 s and V
CC
>=V
CCQ
- 100 mV. If the V
CC
ramp rate is < 1V/100 s, a hardware reset
required.+
Read Operations
Notes:
1. Not 100% tested.
2. See
Figure 9
and
Table 16
for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE#
high to the data bus driven to V
CC
/2 is taken as t
DF
.
4. S29PL129J has two CE# (CE1#, CE2#).
5. Valid CE1# / CE2# conditions: (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
) or (CE1# = V
IH,
CE2# = V
IH
)
6. Valid CE1# / CE2# transitions: (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
) to (CE1# = CE2# = V
IH
)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = V
IH
) to (CE1# = V
IL
,CE2# = V
IH
) or (CE1# = V
IH
,CE2# = V
IL
)
8. For 70pF Output Load Capacitance, 2 ns is added to the above t
ACC
,t
CE
,t
PACC
,t
OE
values for all speed grades
Figure 10. Input Waveforms and Measurement Levels
Table 18. Read-Only Operations
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
55
60
65
70
Unit
t
AVAV
t
RC
Read Cycle Time (
Note 1
)
Min
55
60
65
70
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
55
60
65
70
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
55
60
65
70
ns
t
PACC
Page Access Time
Max
20
25
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
20
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (
Note 3
)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Notes
1
,
3
)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (
Note 3
)
Min
5
ns
t
OEH
Output Enable Hold
Time (
Note 1
)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
VIO
0.0 V
VIO/2
VIO/2
Output
Measurement Level
In
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
67
A d v a n c e I n f o r m a t i o n
Notes:
1. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 11. Read Operation Timings
Notes:
1. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 12. Page Read Operation Timings
t
OH
t
CE
Data
WE#
Addresses
CE#
OE#
HIGH Z
Valid Data
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Amax-A3
CE#
OE#
A2-A0
Data
Same Page
Aa
Ab
Ac
Ad
Qa
Qb
Qc
Qd
t
ACC
t
PACC
t
PACC
t
PACC
68
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Reset
Note: Not 100% tested.
Table 19. Hardware Reset (RESET#)
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
s
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
Reset High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
s
t
RB
RY/BY# Recovery Time
Min
0
ns
Notes:
1. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#
Figure 13. Reset Timings
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
69
A d v a n c e I n f o r m a t i o n
Erase/Program Operations
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See
Table 25, "Erase And Programming Performance,"
on page 78 for more information.
Table 20. Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
55
60
65
70
Unit
t
AVAV
t
WC
Write Cycle Time (
Note 1
)
Min
55
60
65
70
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
30
35
ns
t
AHT
Address Hold Time From CE1#, CE#2 or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
25
30
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
10
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE1# or CE#2 Setup Time
Min
0
ns
t
WHEH
t
CH
CE1# or CE#2 Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
20
25
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (
Note 4
)
Typ
6
s
t
WHWH1
t
WHWH1
Accelerated Programming Operation (
Note 4
)
Typ
4
s
t
WHWH2
t
WHWH2
Sector Erase Operation (
Note 4
)
Typ
0.5
sec
t
VCS
V
CC
Setup Time (
Note 1
)
Min
50
s
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
Min
35
ns
70
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Timing Diagrams
Notes:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 14. Program Operation Timings
Figure 15. Accelerated Program Timing Diagram
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
WP#/ACC
t
VHH
V
HH
V
IL
or V
IH
V
IL
or V
IH
t
VHH
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
71
A d v a n c e I n f o r m a t i o n
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see
"Write Operation Status"
on
page 56
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 16. Chip/Sector Erase Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
Status
D
OUT
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
72
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Figure 17. Back-to-back Read/Write Cycle Timings
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle
Figure 18. Data# Polling Timings (During Embedded Algorithms)
OE#
CE#
WE#
Addresses
t
OH
Data
Valid
In
Valid
In
Valid PA
Valid RA
t
WC
t
WPH
t
AH
t
WP
t
DS
t
DH
t
AS
t
RC
t
CE
t
AH
Valid
Out
t
OE
t
ACC
t
OEH
t
GHWL
t
DF
Valid
In
CE# Controlled Write Cycles
WE# Controlled Write Cycle
Valid PA
Valid PA
t
CP
t
CPH
t
WC
t
WC
Read Cycle
t
SR/W
t
AS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
73
A d v a n c e I n f o r m a t i o n
Notes:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or
CE# to toggle DQ2 and DQ6.
Figure 20. DQ2 vs. DQ6
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read)
(second read)
(stops toggling)
t
CEPH
t
AHT
t
AS
DQ6/DQ2
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
74
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Protect/Unprotect
Note: Not 100% tested.
Table 21. Temporary Sector Unprotect
Parameter
All Speed Options
JEDEC
Std
Description
Unit
t
VIDR
V
ID
Rise and Fall Time (See Note)
Min
500
ns
t
VHH
V
HH
Rise and Fall Time (See Note)
Min
250
ns
t
RSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
s
t
RRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
Min
4
s
Figure 21. Temporary Sector Unprotect Timing Diagram
RESET#
t
VIDR
V
ID
V
IL
or V
IH
V
ID
V
IL
or V
IH
CE#
WE#
RY/BY#
t
VIDR
t
RSP
Program or Erase Command Sequence
t
RRB
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
75
A d v a n c e I n f o r m a t i o n
Notes:
1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram
Sector Group Protect: 150 s
Sector Group Unprotect: 15 ms
1 s
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h
60h
40h
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
V
ID
V
IH
76
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Controlled Erase Operations
Notes:
1. Not 100% tested.
2. See the
Table 25, "Erase And Programming Performance,"
on page 78 for more information.
Table 22. Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
55
60
65
70
Unit
t
AVAV
t
WC
Write Cycle Time (
Note 1
)
Min
55
60
65
70
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
30
35
ns
t
DVEH
t
DS
Data Setup Time
Min
25
30
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE1# or CE#2 Pulse Width
Min
35
40
ns
t
EHEL
t
CPH
CE1# or CE#2 Pulse Width High
Min
20
25
ns
t
WHWH1
t
WHWH1
Programming Operation (
Note 2
)
Typ
6
s
t
WHWH1
t
WHWH1
Accelerated Programming Operation (
Note 2
)
Typ
4
s
t
WHWH2
t
WHWH2
Sector Erase Operation (
Note 2
)
Typ
0.5
sec
June 4, 2004 S29PL129J_MCP_00_A0
S29PL129J for MCP
77
A d v a n c e I n f o r m a t i o n
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
OUT
is the data written to the device
4. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Table 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings
Table 24. CE1#/CE2# Timing
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
CCR
CE1#/CE2# Recover Time
Min
30
ns
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
78
S29PL129J for MCP
S29PL129J_MCP_00_A0 June 4, 2004
A d v a n c e I n f o r m a t i o n
Notes:
1. Typical program and erase times assume the following conditions: 25C, 3.0 V V
CC
, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90C, V
CC
= 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See
Table 12
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Table 25. Erase And Programming Performance
Parameter
Typ (
Note 1
)
Max (
Note 2
)
Unit
Comments
Sector Erase Time
0.5
2
sec
Excludes 00h programming
prior to erasure (
Note 4
)
Chip Erase Time
PL129J
135
216
sec
Word Program Time
6
100
s
Excludes system level
overhead (
Note 5
)
Accelerated Word Program Time
4
60
s
Chip Program Time
(
Note 3
)
PL129J
50.4
200
sec
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6.3
7
pF
C
OUT
Output Capacitance
V
OUT
= 0
7.0
8
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
5.5
8
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN
= 0
11
12
pF
CE1#
t
CCR
t
CCR
CE2#
Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
79
A d v a n c e I n f o r m a t i o n
pSRAM Type 6
2M Word by 16-bit Cmos Pseudo Static RAM (32M Density)
4M Word by 16-bit Cmos Pseudo Static RAM (64M Density)
Features
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
-- Page read operation by 8 words
Logic compatible with SRAM R/W pin
Standby current
-- Standby = 70 A (32M)
-- Standby = 100 A (64M)
-- Deep power-down Standby = 5 A
Access Times
Pin Description
32M
64M
Access Time
70 ns
CE1# Access Time
70 ns
OE# Access Time
25 ns
Page Access Time
30 ns
Pin Name
Description
A
0
to A
21
Address Inputs
A0 to A2
Page Address Inputs
I/O1 to I/O16
Data Inputs/Outputs
CE1#
Chip Enable Input
CE2
Chip select Input
WE#
Write Enable Input
OE#
Output Enable Input
LB#,UB#
Data Byte Control Inputs
V
DD
Power Supply
GND
Ground
NC
Not Connection
80
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004
A d v a n c e I n f o r m a t i o n
Functional Description
Legend:L = Low-level Input (V
IL
), H = High-level Input (V
IH
), X = V
IL
or V
IH
, High-Z = High Impedance.
Absolute Maximum Ratings
Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are
developed by Spansion and component devices that are developed by a third party (third-party components). Spansion
components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory
Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. How-
ever, ESD test results for third-party components may be available from the component manufacturer. Component man-
ufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash
memory Qualification Database and Spansion MCP Qualification Report are available from Spansion sales offices.
DC Recommended Operating Conditions (Ta = -40C to 85C)
Note: V
IH
(Max) V
DD
= 1.0 V with 10 ns pulse width. V
IL
(Min) -1.0 V with 10 ns pulse width.
Mode
CE1#
CE2
OE#
WE#
LB#
UB#
Address
I/O
1-8
I/O
9-16
Power
Read (Word)
L
H
L
H
L
L
X
D
OUT
D
OUT
I
DDO
Read (Lower Byte)
L
H
L
H
L
H
X
D
OUT
High-Z
I
DDO
Read (Upper Byte)
L
H
L
H
H
L
X
High-Z
D
OUT
I
DDO
Write (Word)
L
H
X
L
L
L
X
D
IN
D
IN
I
DDO
Write (Lower Byte)
L
H
X
L
L
H
X
D
IN
Invalid
I
DDO
Write (Upper Byte)
L
H
X
L
H
L
X
Invalid
D
IN
I
DDO
Outputs Disabled
L
H
H
H
X
X
X
High-Z
High-Z
I
DDO
Standby
H
H
X
X
X
X
X
High-Z
High-Z
I
DDO
Deep Power-down Standby
H
L
X
X
X
X
X
High-Z
High-Z
I
DDSD
Symbol
Rating
Value
Unit
V
DD
Power Supply Voltage
-1.0 to 3.6
V
V
IN
Input Voltage
-1.0 to 3.6
V
V
OUT
Output Voltage
-1.0 to 3.6
V
T
opr
Operating Temperature
-40 to 85
C
T
strg
Storage Temperature
-55 to 150
C
P
D
Power Dissipation
0.6
W
I
OUT
Short Circuit Output Current
50
mA
Symbol
Parameter
Min
Typ
Max
Unit
V
DD
Power Supply Voltage
2.6
2.75
3.3
V
V
IH
Input High Voltage
2.0
--
V
DD
+ 0.3 (Note)
V
IL
Input Low Voltage
-0.3 (Note)
--
0.4
Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
81
A d v a n c e I n f o r m a t i o n
DC Characteristics (Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Capacitance (Ta = 25C, f = 1 MHz)
Note: This parameter is sampled periodically and is not 100% tested.
AC Characteristics and Operating Conditions
(Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol
Parameter
Test Condition
Min
Typ.
Max
Unit
I
IL
Input Leakage
Current
V
IN
= 0 V to V
DD
-1.0
--
+1.0
A
I
LO
Output Leakage
Current
Output disable, V
OUT
= 0 V to V
DD
-1.0
--
+1.0
A
V
OH
Output High Voltage
I
OH
= - 0.5 mA
2.0
V
V
V
OL
Output Low Voltage
I
OL
= 1.0 mA
--
--
0.4
V
I
DDO1
Operating Current
CE1#= V
IL
, CE2 = V
IH
, I
OUT
= 0
mA, t
RC
= min.
ET5UZ8A-43DS
--
--
40
mA
ET5VB5A-43DS
--
--
50
I
DDO2
Page Access
Operating Current
CE1#= V
IL
, CE2 = V
IH
, I
OUT
= 0 mA
Page add. cycling, t
RC
= min.
--
--
25
mA
I
DDS
Standby Current
(MOS)
CE1# = V
DD
- 0.2 V,
CE2 = V
DD
- 0.2 V
ET5UZ8A-43DS
--
--
70
mA
ET5VB5A-43DS
--
--
100
A
I
DDSD
Deep Power-down
Standby Current
CE2 = 0.2 V
--
--
5
A
Symbol
Parameter
Test Condition
Max
Unit
C
IN
Input Capacitance
V
IN
= GND
10
pF
C
OUT
Output Capacitance
V
OUT
= GND
10
pF
Symbol
Parameter
Min
Max
Unit
t
RC
Read Cycle Time
70
10000
ns
t
ACC
Address Access Time
--
70
ns
t
CO
Chip Enable (CE1#) Access Time
--
70
ns
t
OE
Output Enable Access Time
--
25
ns
t
BA
Data Byte Control Access Time
--
25
ns
t
COE
Chip Enable Low to Output Active
10
--
ns
t
OEE
Output Enable Low to Output Active
0
--
ns
t
BE
Data Byte Control Low to Output Active
0
--
ns
t
OD
Chip Enable High to Output High-Z
--
20
ns
t
ODO
Output Enable High to Output High-Z
--
20
ns
t
BD
Data Byte Control High to Output High-Z
--
20
ns
82
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004
A d v a n c e I n f o r m a t i o n
AC Test Conditions
t
OH
Output Data Hold Time
10
--
ns
t
PM
Page Mode Time
70
10000
ns
t
PC
Page Mode Cycle Time
30
--
ns
t
AA
Page Mode Address Access Time
--
30
ns
t
AOH
Page Mode Output Data Hold Time
10
--
ns
t
WC
Write Cycle Time
70
10000
ns
t
WP
Write Pulse Width
50
--
ns
t
CW
Chip Enable to End of Write
70
--
ns
t
BW
Data Byte Control to End of Write
60
--
ns
t
AW
Address Valid to End of Write
60
--
ns
t
AS
Address Set-up Time
0
--
ns
t
WR
Write Recovery Time
0
--
ns
t
CEH
Chip Enable High Pulse Width
10
--
ns
t
WEH
Write Enable High Pulse Width
6
--
ns
t
ODW
WE# Low to Output High-Z
--
20
ns
t
OEW
WE# High to Output Active
0
ns
t
DS
Data Set-up Time
30
--
ns
t
DH
Data Hold Time
0
--
ns
t
CS
CE2 Set-up Time
0
--
ns
t
CH
CE2 Hold Time
300
--
s
t
DPD
CE2 Pulse Width
10
--
ms
t
CHC
CE2 Hold from CE1#
0
--
ns
t
CHP
CE2 Hold from Power On
30
--
s
Parameter
Condition
Output load
30 pF + 1 TTL Gate
Input pulse level
V
DD
- 0.2 V, 0.2 V
Timing measurements
V
DD
x 0.5
Reference level
V
DD
x 0.5
t
R
, t
F
5 ns
Symbol
Parameter
Min
Max
Unit
Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
83
A d v a n c e I n f o r m a t i o n
Timing Diagrams
Read Timings
Figure 24. Read Cycle
t
ACC
t
OD
t
OH
VALID DATA OUT
t
OE
t
BE
t
OEE
t
BD
Hi-Z
Hi-Z
t
CO
Fix-H
t
BA
t
COE
INDETERMINATE
t
ODO
t
RC
Address
A0 to A20(32M)
A0 to A21(64M)
CE1#
CE2
OE#
WE#
UB#, LB#
D
OUT
I/O1 to I/O16
84
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004
A d v a n c e I n f o r m a t i o n
Figure 25. Page Read Cycle (8 Words Access)
t
PM
t
PC
t
RC
t
AOH
Fix-H
Hi-Z
Hi-Z
t
BE
D
OUT
t
ACC
t
COE
t
CO
t
OE
t
BA
t
OEE
t
PC
t
AOH
t
PC
D
OUT
t
OD
t
OH
t
BD
t
ODO
t
AA
* Maximum 8 words
D
OUT
t
AOH
D
OUT
t
AA
t
AA
Address
A0 to A2
Address
A3 to A20(32M)
A3 to A21(64M)
CE1#
CE2
OE#
WE#
UB#, LB#
D
OUT
I/O1 to I/O16
Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
85
A d v a n c e I n f o r m a t i o n
Write Timings
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)
UB#
D
IN
I/O1 to I/O16
D
OUT
I/O1 to I/O16
CE2
CE1#
WE#
Address
A0 to A20
A0 to
(32M)
A21(64M)
t
WC
t
AS
t
BW
t
WR
VALID DATA IN
t
ODW
t
WP
t
DS
t
DH
t
OEW
(See Note 11)
(S
)
ee Note 10
Hi-Z
t
CW
t
WR
t
WEH
t
AW
t
WR
t
CH
(See Note 9)
(See Note 9)
, LB#
86
pSRAM Type 6
pSRAM_Type06_14_A1 Ocotober 16, 2004
A d v a n c e I n f o r m a t i o n
Deep Power-down Timing
Power-on Timing
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8)
Figure 28. Deep Power Down Timing
Figure 29. Power-on Timing
t
WC
t
WP
t
AS
t
CW
t
WR
VALID DATA IN
t
ODW
t
DS
t
DH
t
COE
Hi-Z
Hi-Z
t
AW
t
WR
t
CEH
t
BW
t
BE
t
WR
t
CH
(See Note 9)
Address
A0 to A20
A0 to
(32M)
A21(64M)
WE#
CE1#
CE2
UB#, LB#
D
OUT
I/O1 to I/O16
D
IN
I/O1 to I/O16
t
CS
t
DPD
t
CH
CE1#
CE2
t
CHC
t
CHP
t
CH
V
DD
min
V
DD
CE1#
CE2
Ocotober 16, 2004 pSRAM_Type06_14_A1
pSRAM Type 6
87
A d v a n c e I n f o r m a t i o n
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than t
RC
min. sustain over 10 s
in an active status, at least one valid address cycle over t
RC
min. is required dur-
ing 10s.
Write
In case multiple invalid address cycles shorter than t
WC
min. sustain over 10 s
in an active status, at least one valid address cycle over t
WC
min. is required dur-
ing 10 s.
Notes:
1. Stresses greater than listed under "
Absolute Maximum Ratings
" section may cause permanent damage to the device.
2. All voltages are reference to GND.
3. I
DDO
depends on the cycle time.
4. I
DDO
depends on output loading. Specified values are defined with the output open condition.
5. AC measurements are assumed t
R
, t
F
= 5 ns.
6. Parameters t
OD
, t
ODO
, t
BD
and t
OD
W define the time at which the output goes the open condition and are not output voltage
reference levels.
7. Data cannot be retained at deep power-down stand-by mode.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. During the output state of I/O signals, input signals of reverse polarity must not be applied.
10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
Figure 30. Read
Figure 31. Write
over 10
s
t
RC
min
CE1#
WE#
Address
t
WP
min
t
WC
min
CE1#
WE#
Address
88
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
pSRAM Type 1
4Mbit (256K Word x 16-bit)
8Mbit (512K Word x 16-bit)
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
Functional Description
Absolute Maximum Ratings
Mode
CE#
CE2/ZZ#
OE#
WE#
UB#
LB#
Addresses
I/O 1-8
I/O 9-16
Power
Read (word)
L
H
L
H
L
L
X
Dout
Dout
I
ACTIVE
Read (lower byte)
L
H
L
H
H
L
X
Dout
High-Z
I
ACTIVE
Read (upper byte)
L
H
L
H
L
H
X
High-Z
Dout
I
ACTIVE
Write (word)
L
H
X
L
L
L
X
Din
Din
I
ACTIVE
Write (lower byte)
L
H
X
L
H
L
X
Din
Invalid
I
ACTIVE
Write (upper byte)
L
H
X
L
L
H
X
Invalid
Din
I
ACTIVE
Outputs disabled
L
H
H
H
X
X
X
High-Z
High-Z
I
ACTIVE
Standby
H
H
X
X
X
X
X
High-Z
High-Z
I
STANDBY
Deep power down
H
L
X
X
X
X
X
High-Z
High-Z
I
DEEP SLEEP
Item
Symbol
Ratings
Units
Voltage on any pin relative to V
SS
Vin, Vout
-0.2 to V
CC
+0.3
V
Voltage on V
CC
relative to V
SS
V
CC
-0.2 to 3.6
V
Power dissipation
P
D
1
W
Storage temperature
T
STG
-55 to 150
C
Operating temperature
T
A
-25 to 85
C
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
89
A d v a n c e I n f o r m a t i o n
DC Characteristics
(4Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
-70
Density
4Mb pSRAM
Symbol
Parameter
Conditions
Min
Max
Units
V
CC
Power Supply
2.7
3.3
V
V
IH
Input High Level
0.8 Vccq
V
CC
+ 0.3
V
V
IL
Input Low Level
-0.3
0.4
V
I
IL
Input Leakage
Current
Vin = 0 to V
CC
0.5
A
I
LO
Output Leakage
Current
OE = V
IH
or
Chip Disabled
0.5
A
V
OH
Output High
Voltage
I
OH
= -1.0 mA
V
I
OH
= -0.2 mA
0.8 Vccq
I
OH
= -0.5 mA
V
OL
Output Low
Voltage
I
OL
= 2.0 mA
V
I
OL
= 0.2 mA
0.2
I
OL
= 0.5 mA
I
ACTIVE
Operating
Current
V
CC
= 3.3 V
25
mA
I
STANDBY
Standby Current
V
CC
= 3.0 V
70
A
V
CC
= 3.3 V
I
DEEP
SLEEP
Deep Power
Down Current
x
A
I
PAR 1/4
1/4 Array PAR
Current
x
A
I
PAR 1/2
1/2 Array PAR
Current
x
A
90
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
(8Mb pSRAM Asynchronous)
Asynchronous
Version
B
C
Performance Grade
-55
-70
-70
Density
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
Symbol
Parameter
Conditions
Min
Max
Units
Min
Max
Units
Min
Max
Units
V
CC
Power Supply
2.7
3.3
V
2.7
3.6
V
2.7
3.3
V
V
IH
Input High Level
2.2
V
CC
+ 0.3
V
2.2
V
CC
+ 0.3
V
0.8
V
CC
+0.3
V
V
IL
Input Low Level
-0.3
0.6
V
-0.3
0.6
V
-0.3
0.4
V
I
IL
Input Leakage
Current
Vin = 0 to V
CC
0.5
A
0.5
A
0.5
A
I
LO
Output Leakage
Current
OE = V
IH
or
Chip Disabled
0.5
A
0.5
A
0.5
A
V
OH
Output High Voltage
I
OH
= -1.0 mA V
CC
-0.4
V
V
CC
-0.4
V
V
I
OH
= -0.2 mA
0.8 V
CCQ
I
OH
= -0.5 mA
V
OL
Output Low Voltage
I
OL
= 2.0 mA
0.4
V
0.4
V
V
I
OL
= 0.2 mA
0.2
I
OL
= 0.5 mA
I
ACTIVE
Operating Current
V
CC
= 3.3 V
25
mA
23
mA
25
mA
I
STANDBY
Standby Current
V
CC
= 3.0 V
60
A
60
A
70
A
V
CC
= 3.3 V
I
DEEP
SLEEP
Deep Power Down
Current
x
A
x
A
x
A
I
PAR 1/4
1/4 Array PAR
Current
x
A
x
A
x
A
I
PAR 1/2
1/2 Array PAR
Current
x
A
x
A
x
A
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
91
A d v a n c e I n f o r m a t i o n
DC Characteristics
(16Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
-55
-70
Density
16Mb pSRAM
16Mb pSRAM
Symbol
Parameter
Conditions
Minimum
Maximum
Units
Minimum Maximum
Units
V
CC
Power Supply
2.7
3.6
V
2.7
3.6
V
V
IH
Input High Level
2.2
V
CC
+ 0.3
V
2.2
V
CC
+ 0.3
V
V
IL
Input Low Level
-0.3
0.6
V
-0.3
0.6
V
I
IL
Input Leakage Current
Vin = 0 to V
CC
0.5
A
0.5
A
I
LO
Output Leakage Current
OE = V
IH
or Chip Disabled
0.5
A
0.5
A
V
OH
Output High Voltage
I
OH
= -1.0 mA
V
CC
-0.4
V
V
CC
-0.4
V
I
OH
= -0.2 mA
I
OH
= -0.5 mA
V
OL
Output Low Voltage
I
OL
= 2.0 mA
0.4
V
0.4
V
I
OL
= 0.2 mA
I
OL
= 0.5 mA
I
ACTIVE
Operating Current
V
CC
= 3.3 V
25
mA
25
mA
I
STANDBY
Standby Current
V
CC
= 3.0 V
100
A
100
A
V
CC
= 3.3 V
I
DEEP SLEEP
Deep Power Down Current
x
A
x
A
I
PAR 1/4
1/4 Array PAR Current
x
A
x
A
I
PAR 1/2
1/2 Array PAR Current
x
A
x
A
92
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
(16Mb pSRAM Page Mode)
Page Mode
Performance Grade
-60
-65
-70
Density
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
Symbol
Parameter
Conditions
Min
Max
Units
Min
Max
Units
Min
Max
Units
V
CC
Power Supply
2.7
3.3
V
2.7
3.3
V
2.7
3.3
V
V
IH
Input High
Level
0.8 Vccq V
CC
+ 0.2
V
0.8 Vccq V
CC
+ 0.2
V
0.8 Vccq
V
CC
+ 0.2
V
V
IL
Input Low
Level
-0.2
0.2 Vccq
V
-0.2
0.2 Vccq
V
-0.2
0.2 Vccq
V
I
IL
Input Leakage
Current
Vin = 0 to V
CC
1
A
1
A
1
A
I
LO
Output
Leakage
Current
OE = V
IH
or
Chip Disabled
1
A
1
A
1
A
V
OH
Output High
Voltage
I
OH
= -1.0 mA
V
V
V
I
OH
= -0.2 mA
I
OH
= -0.5 mA 0.8 Vccq
0.8 Vccq
0.8 Vccq
V
OL
Output Low
Voltage
I
OL
= 2.0 mA
V
V
V
I
OL
= 0.2 mA
I
OL
= 0.5 mA
0.2 Vccq
0.2 Vccq
0.2 Vccq
I
ACTIVE
Operating
Current
V
CC
= 3.3 V
25
mA
25
mA
25
mA
I
STANDBY
Standby
Current
V
CC
= 3.0 V
A
A
A
V
CC
= 3.3 V
100
100
100
I
DEEP
SLEEP
Deep Power
Down Current
10
A
10
A
10
A
I
PAR 1/4
1/4 Array PAR
Current
65
A
65
A
65
A
I
PAR 1/2
1/2 Array PAR
Current
80
A
80
A
80
A
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
93
A d v a n c e I n f o r m a t i o n
DC Characteristics
(32Mb pSRAM Page Mode)
Page Mode
Version
C
E
Performance Grade
-65
-60
-65
-70
Density
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
Symbol Parameter
Conditions
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
V
CC
Power
Supply
2.7
3.6
V
2.7
3.3
V
2.7
3.3
V
2.7
3.3
V
V
IH
Input High
Level
1.4
V
CC
+
0.2
V
0.8 Vccq
V
CC
+ 0.2
V
0.8 Vccq
V
CC
+ 0.2
V
0.8
Vccq
V
CC
+
0.2
V
V
IL
Input Low
Level
-0.2
0.4
V
-0.2
0.2
Vccq
V
-0.2
0.2
Vccq
V
-0.2
0.2
Vccq
V
I
IL
Input
Leakage
Current
Vin = 0 to V
CC
0.5
A
1
A
1
A
1
A
I
LO
Output
Leakage
Current
OE = V
IH
or
Chip Disabled
0.5
A
1
A
1
A
1
A
V
OH
Output High
Voltage
I
OH
= -1.0 mA
V
V
V
V
I
OH
= -0.2 mA
0.8
Vccq
I
OH
= -0.5 mA
0.8 Vccq
0.8 Vccq
0.8
Vccq
V
OL
Output Low
Voltage
I
OL
= 2.0 mA
V
V
V
V
I
OL
= 0.2 mA
0.2
I
OL
= 0.5 mA
0.2
Vccq
0.2
Vccq
0.2
Vccq
I
ACTIVE
Operating
Current
V
CC
= 3.3 V
25
mA
25
mA
25
mA
25
mA
I
STANDBY
Standby
Current
V
CC
= 3.0 V
A
A
A
A
V
CC
= 3.3 V
100
120
120
120
I
DEEP
SLEEP
Deep Power
Down
Current
10
A
10
A
10
A
10
A
I
PAR 1/4
1/4 Array
PAR Current
65
A
75
A
75
A
75
A
I
PAR 1/2
1/2 Array
PAR Current
80
A
90
A
90
A
90
A
94
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
(64Mb pSRAM Page Mode)
Timing Test Conditions
Page Mode
Performance Grade
-70
Density
64Mb pSRAM
Symbol
Parameter
Conditions
Min
Max
Units
V
CC
Power Supply
2.7
3.3
V
V
IH
Input High Level
0.8 Vccq
V
CC
+ 0.2
V
V
IL
Input Low Level
-0.2
0.2 Vccq
V
I
IL
Input Leakage
Current
Vin = 0 to V
CC
1
A
I
LO
Output Leakage
Current
OE = V
IH
or
Chip Disabled
1
A
V
OH
Output High
Voltage
I
OH
= -1.0 mA
V
I
OH
= -0.2 mA
I
OH
= -0.5 mA
0.8 Vccq
V
OL
Output Low
Voltage
I
OL
= 2.0 mA
V
I
OL
= 0.2 mA
I
OL
= 0.5 mA
0.2 Vccq
I
ACTIVE
Operating
Current
V
CC
= 3.3 V
25
mA
I
STANDBY
Standby Current
V
CC
= 3.0 V
A
V
CC
= 3.3 V
120
I
DEEP
SLEEP
Deep Power
Down Current
10
A
I
PAR 1/4
1/4 Array PAR
Current
65
A
I
PAR 1/2
1/2 Array PAR
Current
80
A
Item
Input Pulse Level
0.1 V
CC
to 0.9 V
CC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 V
CC
Operating Temperature
-25C to +85C
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
95
A d v a n c e I n f o r m a t i o n
Output Load Circuit
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200 s
after CE# > V
IH
.
Figure 32. Output Load Circuit
V
CC
30 pF
I/O
14.5K
14.5K
Output Load
96
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(4Mb pSRAM Page Mode)
Asynchronous
Performance Grade
-70
Density
4Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Re
a
d
trc
Read cycle time
70
ns
taa
Address Access
Time
70
ns
tco
Chip select to
output
70
ns
toe
Output enable to
valid output
20
ns
tba
UB#, LB# Access
time
70
ns
tlz
Chip select to
Low-z output
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
tolz
Output enable to
Low-Z output
5
ns
thz
Chip enable to
High-Z output
0
20
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
tohz
Output disable to
High-Z output
0
20
ns
toh
Output hold from
Address Change
10
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
97
A d v a n c e I n f o r m a t i o n
Wr
i
t
e
twc
Write cycle time
70
ns
tcw
Chipselect to end
of write
70
ns
tas
Address set up
Time
0
ns
taw
Address valid to
end of write
70
ns
tbw
UB#, LB# valid
to end of write
70
ns
twp
Write pulse width
55
ns
twr
Write recovery
time
0
ns
twhz
Write to output
High-Z
20
ns
tdw
Data to write
time overlap
25
ns
tdh
Data hold from
write time
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
ns
Ot
her
tpc
Page read cycle
x
tpa
Page address
access time
x
twpc
Page write cycle
x
tcp
Chip select high
pulse width
x
Asynchronous
Performance Grade
-70
Density
4Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
98
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(8Mb pSRAM Asynchronous)
Asynchronous
Version
B
C
Performance Grade
-55
-70
-70
Density
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
Read
trc
Read cycle time
55
ns
70
ns
70
ns
taa
Address Access
Time
55
ns
70
ns
70
ns
tco
Chip select to
output
55
ns
70
ns
70
ns
toe
Output enable to
valid output
30
ns
35
ns
20
ns
tba
UB#, LB# Access
time
55
ns
70
ns
70
ns
tlz
Chip select to
Low-z output
5
ns
5
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
5
ns
5
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
20
ns
0
25
ns
0
20
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
0
25
ns
0
20
ns
tohz
Output disable to
High-Z output
0
20
ns
0
25
ns
0
20
ns
toh
Output hold from
Address Change
10
ns
10
ns
10
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
99
A d v a n c e I n f o r m a t i o n
Wr
i
t
e
twc
Write cycle time
55
ns
70
ns
70
ns
tcw
Chip select to
end of write
45
ns
55
ns
70
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
taw
Address valid to
end of write
45
ns
55
ns
70
ns
tbw
UB#, LB# valid
to end of write
45
ns
55
ns
70
ns
twp
Write pulse width
45
ns
55
ns
55
ns
twr
Write recovery
time
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
25
ns
25
20
ns
tdw
Data to write
time overlap
40
ns
40
ns
25
ns
tdh
Data hold from
write time
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
5
5
tow
Write high pulse
width
x
x
ns
x
x
ns
x
x
ns
Ot
h
e
r
tpc
Page read cycle
x
x
x
tpa
Page address
access time
x
x
x
twpc
Page write cycle
x
x
x
tcp
Chip select high
pulse width
x
x
x
Asynchronous
Version
B
C
Performance Grade
-55
-70
-70
Density
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
100
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(16Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
-55
-70
Density
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Re
a
d
trc
Read cycle time
55
ns
70
ns
taa
Address Access
Time
55
ns
70
ns
tco
Chip select to
output
55
ns
70
ns
toe
Output enable to
valid output
30
ns
35
ns
tba
UB#, LB# Access
time
55
ns
70
ns
tlz
Chip select to
Low-z output
5
ns
5
ns
tblz
UB#, LB# Enable
to Low-Z output
5
ns
5
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
thz
Chip enable to
High-Z output
0
25
ns
0
25
ns
tbhz
UB#, LB#
disable to High-Z
output
0
25
ns
0
25
ns
tohz
Output disable to
High-Z output
0
25
ns
0
25
ns
toh
Output hold from
Address Change
10
ns
10
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
101
A d v a n c e I n f o r m a t i o n
Wr
i
t
e
twc
Write cycle time
55
ns
70
ns
tcw
Chipselect to end
of write
50
ns
55
ns
tas
Address set up
Time
0
ns
0
ns
taw
Address valid to
end of write
50
ns
55
ns
tbw
UB#, LB# valid
to end of write
50
ns
55
ns
twp
Write pulse width
50
ns
55
ns
twr
Write recovery
time
0
ns
0
ns
twhz
Write to output
High-Z
25
ns
25
ns
tdw
Data to write
time overlap
25
ns
25
ns
tdh
Data hold from
write time
0
ns
0
ns
tow
End write to
output Low-Z
5
5
tow
Write high pulse
width
x
x
ns
x
x
ns
Ot
her
tpc
Page read cycle
x
x
tpa
Page address
access time
x
x
twpc
Page write cycle
x
x
tcp
Chip select high
pulse width
x
x
Asynchronous
Performance Grade
-55
-70
Density
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
102
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(16Mb pSRAM Page Mode)
Page Mode
Performance Grade
-60
-65
-70
Density
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
Re
a
d
trc
Read cycle time
60
20k
ns
65
20k
ns
70
20k
ns
taa
Address Access
Time
60
ns
65
ns
70
ns
tco
Chip select to
output
60
ns
65
ns
70
ns
toe
Output enable to
valid output
25
ns
25
ns
25
ns
tba
UB#, LB# Access
time
60
ns
65
ns
70
ns
tlz
Chip select to
Low-z output
10
ns
10
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
10
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
5
ns
0
5
ns
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
5
ns
0
5
ns
0
5
ns
tohz
Output disable to
High-Z output
0
5
ns
0
5
ns
0
5
ns
toh
Output hold from
Address Change
5
ns
5
ns
5
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
103
A d v a n c e I n f o r m a t i o n
Wr
i
t
e
twc
Write cycle time
60
20k
ns
65
20k
ns
70
20k
ns
tcw
Chipselect to end
of write
50
ns
60
ns
60
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
taw
Address valid to
end of write
50
ns
60
ns
60
ns
tbw
UB#, LB# valid
to end of write
50
ns
60
ns
60
ns
twp
Write pulse width
50
ns
50
ns
50
ns
twr
Write recovery
time
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
5
ns
5
ns
5
ns
tdw
Data to write
time overlap
20
ns
20
ns
20
ns
tdh
Data hold from
write time
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
5
5
tow
Write high pulse
width
7.5
ns
7.5
ns
7.5
ns
Ot
her
tpc
Page read cycle
25
20k
ns
25
20k
ns
25
20k
ns
tpa
Page address
access time
25
ns
25
ns
25
ns
twpc
Page write cycle
25
20k
ns
25
20k
ns
25
20k
ns
tcp
Chip select high
pulse width
10
ns
10
ns
10
ns
Page Mode
Performance Grade
-60
-65
-70
Density
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
104
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(32Mb pSRAM Page Mode)
Page Mode
Version
C
E
Performance Grade
-65
-60
-65
-70
Density
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
Read
trc
Read cycle time
65
20k
ns
60
20k
ns
65
20k
ns
70
20k
ns
taa
Address Access
Time
65
ns
60
ns
65
ns
70
ns
tco
Chip select to
output
65
ns
60
ns
65
ns
70
ns
toe
Output enable to
valid output
20
ns
25
ns
25
ns
25
ns
tba
UB#, LB# Access
time
65
ns
60
ns
65
ns
70
ns
tlz
Chip select to
Low-z output
10
ns
10
ns
10
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
10
ns
10
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
tohz
Output disable to
High-Z output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
toh
Output hold from
Address Change
5
ns
5
ns
5
ns
5
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
105
A d v a n c e I n f o r m a t i o n
Wr
i
t
e
twc
Write cycle time
65
20k
ns
60
20k
ns
65
20k
ns
70
20k
ns
tcw
Chipselect to end
of write
55
ns
50
ns
60
ns
60
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
0
ns
taw
Address valid to
end of write
55
ns
50
ns
60
ns
60
ns
tbw
UB#, LB# valid
to end of write
55
ns
50
ns
60
ns
60
ns
twp
Write pulse width
55
20k
ns
50
ns
50
ns
50
ns
twr
Write recovery
time
0
ns
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
5
ns
5
ns
5
ns
5
ns
tdw
Data to write
time overlap
25
ns
20
ns
20
ns
20
ns
tdh
Data hold from
write time
0
ns
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
5
5
5
tow
Write high pulse
width
7.5
ns
7.5
ns
7.5
ns
7.5
ns
Ot
h
e
r
tpc
Page read cycle
25
20k
ns
25
20k
ns
25
20k
ns
25
20k
ns
tpa
Page address
access time
25
ns
25
ns
25
ns
25
ns
twpc
Page write cycle
25
20k
ns
25
20k
ns
25
20k
ns
25
20k
ns
tcp
Chip select high
pulse width
10
ns
10
ns
10
ns
10
ns
Page Mode
Version
C
E
Performance Grade
-65
-60
-65
-70
Density
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
106
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
(64Mb pSRAM Page Mode)
Page Mode
Performance Grade
-70
Density
64Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Re
a
d
trc
Read cycle time
70
20k
ns
taa
Address Access
Time
70
ns
tco
Chip select to
output
70
ns
toe
Output enable to
valid output
25
ns
tba
UB#, LB# Access
time
70
ns
tlz
Chip select to
Low-z output
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
tolz
Output enable to
Low-Z output
5
ns
thz
Chip enable to
High-Z output
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
5
ns
tohz
Output disable to
High-Z output
0
5
ns
toh
Output hold from
Address Change
5
ns
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
107
A d v a n c e I n f o r m a t i o n
Timing Diagrams
Read Cycle
Wr
i
t
e
twc
Write cycle time
70
20k
ns
tcw
Chipselect to end
of write
60
ns
tas
Address set up
Time
0
ns
taw
Address valid to
end of write
60
ns
tbw
UB#, LB# valid
to end of write
60
ns
twp
Write pulse width
50
20k
ns
twr
Write recovery
time
0
ns
twhz
Write to output
High-Z
5
ns
tdw
Data to write
time overlap
20
ns
tdh
Data hold from
write time
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
ns
Ot
her
tpc
Page read cycle
20
20k
ns
tpa
Page address
access time
20
ns
twpc
Page write cycle
20
20k
ns
tcp
Chip select high
pulse width
10
ns
Figure 33. Timing of Read Cycle (CE# = OE# = V
IL
, WE# = ZZ# = V
IH
)
Page Mode
Performance Grade
-70
Density
64Mb pSRAM
3 Volt
Symbol
Parameter
Min
Max
Units
Address
Data Out
t
RC
t
AA
t
OH
Data Valid
Previous Data Valid
108
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
Figure 34. Timing Waveform of Read Cycle (WE# = ZZ# = V
IH
)
Address
LB#, UB#
OE#
Data Valid
t
RC
t
AA
t
CO
t
HZ
t
OHZ
t
BHZ
t
OLZ
t
OE
t
LZ
High-Z
Data Out
t
LB,
t
UB
t
BLZ
CE#
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
109
A d v a n c e I n f o r m a t i o n
Figure 35. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = V
IH
)
Page Address (A4 - A20)
LB#, UB#
OE#
t
AA
t
CO
t
HZ
t
OHZ
t
BHZ
t
OLZ
t
OE
High-Z
Data Out
t
LB,
t
UB
t
BLZ,
CE#
Word Address (A0 - A3)
t
PA
t
RC
t
PGMAX
t
PC
110
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
Write Cycle
Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ# = V
IH
)
Figure 37. Timing Waveform of Write Cycle (CE# Control, ZZ# = V
IH
)
Addr es s
Dat a
In
CE#
Data Valid
t
WC
t
AW
t
CW
t
WR
t
WHZ
t
DH
High-Z
WE#
Da ta
Out
High-Z
t
OW
t
AS
t
WP
t
DW
t
BW
LB#, UB#
Ad dres s
WE#
Data Valid
t
WC
t
AW
t
CW
t
WR
t
DH
LB#, UB#
Dat a In
High-Z
t
AS
t
WP
t
DW
t
BW
Da ta O ut
t
WHZ
CE#
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
111
A d v a n c e I n f o r m a t i o n
Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
There are several power savings modes.
Partial Array Self Refresh
Temperature Compensated Refresh (64M)
Deep Sleep Mode
Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 39 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register set-
tings for the PASR operation are defined in Table xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
Figure 38. Timing Waveform of Page Mode Write Cycle (ZZ# = V
IH
)
Page Addr es s
(A4 - A20)
LB#, UB#
WE#
t
WP
t
CW
t
DW
High-Z
Dat a Out
t
LBW,
t
UBW
CE#
Wor d Addr es s
(A0 - A3 )
t
WC
t
PWC
t
DH
t
PDW
t
PDH
t
PDW
t
PDH
t
AS
t
PGMAX
112
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the ad-
dress space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4 must
be set to a one (1) value, "PASR Enabled". If this is the case, PASR will be acti-
vated 10 s after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the op-
eration temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower tem-
peratures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given op-
erating temperature. There are four different temperature settings that can be
programmed in to the PSRAM. These are defined in Figure 39.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-
ister bit set to a zero (0), "Deep Sleep Enabled". If this is the case, Deep Sleep
will be entered 10 s after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table "Address Patterns for RMS". The RMS mode is enabled at the time of ZZ
transitioning high and the mode remains active until the register is updated. To
return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
Other Mode Register Settings (for 64M)
The Page Mode operation can also be enabled and disabled using the Mode Reg-
ister. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
113
A d v a n c e I n f o r m a t i o n
Figure 39. Mode Register
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are Don't Care)
Deep Sleep Enable/Disable
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled (default)
PAR Section
1 1 1 = Top 1/4 array
1 1 0 = Top 1/2 array
1 0 1 = Top 3/4 array
1 0 0 = No PAR
0 1 1 = Bottom 1/4 array
0 1 0 = Bottom 1/2 array
0 0 1 = Bottom 3/4 array
0 0 0 = Full array (default)
Reserved
Must set to all 0
A21 - A8
A7
A6
A5
A4
A3
A2
A1
A0
Page Mode
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
Temp
Compensated
Refresh
1 0 = 15
o
C
0 1 = 45
o
C
0 0 = 70
o
C
1 1 = 85
o
C (default)
Array Mode
for ZZ#
0 = PAR (default)
1 = RMS
64 Mb
32 Mb / 16 Mb
Address
ZZ#
t
WC
t
AS
CE#
WE#
t
ZZWE
t
AW
t
WP
t
WR
t
CDZZ
114
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
Mode Register Update and Deep Sleep Timings
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)
Figure 42. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Item
Symbol
Min
Max
Unit
Note
Chip deselect to ZZ# low
t
CDZZ
5
ns
ZZ# low to WE# low
t
ZZWE
10
500
ns
Write register cycle time
t
WC
70/85
ns
1
Chip enable to end of write
t
CW
70/85
ns
1
Address valid to end of write
t
AW
70/85
ns
1
Write recovery time
t
WR
0
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WR
40
ns
Deep Sleep Pulse Width
t
ZZMIN
10
s
Deep Sleep Recovery
t
R
200
s
ZZ#
t
ZZMIN
t
CDZZ
t
R
CE#
A4
ZZ#
t
WC
t
BW
t
AS
CE#
WE#
t
ZZWE
t
AW
t
WP
t
WR
t
R
t
ZZMIN
LB#, UB#
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
115
A d v a n c e I n f o r m a t i o n
Address Patterns for PASR (A4=1) (64M)
A2 A1 A0
Active Section
Address Space
Size
Density
1
1
1
Top quarter of die
300000h-3FFFFFh
1Mb x 16
16Mb
1
1
0
Top half of die
200000h-3FFFFFh
2Mb x 16
32Mb
1
0
1
Reserved
1
0
0
No PASR
None
0
0
0
1
1
Bottom quarter of die
000000h-0FFFFFh
1Mb x 16
16Mb
0
1
0
Bottom half of die
000000h-1FFFFFh
2Mb x 16
32Mb
0
0
1
Reserved
0
0
0
Full array
000000h-3FFFFFh
4Mb x 16
64Mb
116
pSRAM Type 1
pSRAM_Type01_12_A1 August 30, 2004
A d v a n c e I n f o r m a t i o n
Deep ICC Characteristics (for 64Mb)
Address Patterns for PAR (A3= 0, A4=1) (32M)
Address Patterns for RMS (A3 = 1, A4 = 1) (32M)
Item
Symbol
Test
Array Partition Typ Max Unit
PASR Mode Standby Current
I
PASR
V
IN
= V
CC
or 0V, Chip Disabled, t
A
= 85C
None
10
A
1/4 Array
60
1/2 Array
80
Full Array
120
Item
Symbol
Max Temperature
Typ
Max
Unit
Temperature Compensated Refresh Current
I
TCR
15C
50
A
45C
60
70C
80
85C
120
Item
Symbol
Test
Typ
Max
Unit
Deep Sleep Current
I
ZZ
V
IN
= V
CC
or 0V, Chip in ZZ# mode, t
A
= 25C
10
A
A2 A1
A0
Active Section
Address Space
Size
Density
0
1
1
One-quarter of die
000000h - 07FFFFh
512Kb x 16
8Mb
0
1
0
One-half of die
000000h - 0FFFFFh
1Mb x 16
16Mb
x
0
0
Full die
000000h - 1FFFFFh
2Mb x 16
32Mb
1
1
1
One-quarter of die
180000h - 1FFFFFh
512Kb x 16
8Mb
1
1
0
One-half of die
100000h - 1FFFFFh
1Mb x 16
16Mb
A2 A1
A0
Active Section
Address Space
Size
Density
0
1
1
One-quarter of die
000000h - 07FFFFh
512Kb x 16
8Mb
0
1
0
One-half of die
000000h - 0FFFFFh
1Mb x 16
16Mb
1
1
1
One-quarter of die
180000h - 1FFFFFh
512Kb x 16
8Mb
1
1
0
One-half of die
100000h - 1FFFFFh
1Mb x 16
16Mb
August 30, 2004 pSRAM_Type01_12_A1
pSRAM Type 1
117
A d v a n c e I n f o r m a t i o n
Low Power ICC Characteristics (32M)
Address Patterns for PAR (A3= 0, A4=1) (16M)
Address Patterns for RMS (A3 = 1, A4 = 1) (16M)
Low Power ICC Characteristics (16M)
Item
Symbol
Test
Array Partition
Typ
Max
Unit
PAR Mode Standby Current I
PAR
V
IN
= V
CC
or 0V,
Chip Disabled, t
A
= 85
o
C
1/4 Array
75
A
1/2 Array
90
A
RMS Mode Standby Current I
RMSSB
V
IN
= V
CC
or 0V,
Chip Disabled, t
A
= 85
o
C
8Mb Device
75
A
16Mb Device
90
A
Deep Sleep Current
I
ZZ
V
IN
= V
CC
or 0V,
Chip in ZZ mode, t
A
= 85
o
C
10
A
A2 A1
A0
Active Section
Address Space
Size
Density
0
1
1
One-quarter of die
00000h - 0FFFFh
256Kb x 16
4Mb
0
1
0
One-half of die
00000h - 7FFFFh
512Kb x 16
8Mb
x
0
0
Full die
00000h - FFFFFh
1Mb x 16
16Mb
1
1
1
One-quarter of die
C0000h - FFFFh
256Kb x 16
4Mb
1
1
0
One-half of die
80000h - 1FFFFFh
512Kb x 16
8Mb
A2 A1
A0
Active Section
Address Space
Size
Density
0
1
1
One-quarter of die
00000h - 0FFFFh
256Kb x 16
4Mb
0
1
0
One-half of die
00000h - 7FFFFh
512Kb x 16
8Mb
1
1
1
One-quarter of die
C0000h - FFFFFh
256Kb x 16
4Mb
1
1
0
One-half of die
80000h - FFFFFh
512Kb x 16
8Mb
Item
Symbol
Test
Array Partition
Typ
Max
Unit
PAR Mode Standby Current
I
PAR
V
IN
= V
CC
or 0V,
Chip Disabled, t
A
= 85
o
C
1/4 Array
65
A
1/2 Array
80
RMS Mode Standby Current
I
RMSSB
V
IN
= V
CC
or 0V,
Chip Disabled, t
A
= 85
o
C
4Mb Device
65
A
8Mb Device
80
Deep Sleep Current
I
ZZ
V
IN
= V
CC
or 0V,
Chip in ZZ# mode, t
A
= 85
o
C
10
A
118
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
Type 2 pSRAM
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
128Mbit (8M Word x 16-bit)
Features
Process Technology: CMOS
Organization: x16 bit
Power Supply Voltage: 2.7~3.1V
Three State Outputs
Compatible with Low Power SRAM
Product Information
Pin Description
Density
V
CC
Range
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
Mode
16Mb
2.7-3.1V
80 A
30 mA
Dual CS
16Mb
2.7-3.1V
80 A
35 mA
Dual CS and Page Mode
32Mb
2.7-3.1V
100 A
35 mA
Dual CS
32Mb
2.7-3.1V
100 A
40 mA
Dual CS and Page Mode
64Mb
2.7-3.1V
TBD
TBD
Dual CS
64Mb
2.7-3.1V
TBD
TBD
Dual CS and Page Mode
128Mb
2.7-3.1V
TBD
TBD
Dual CS and Page Mode
Pin Name
Description
I/O
CS1#, CS2
Chip Select
I
OE#
Output Enable
I
WE#
Write Enable
I
LB#, UB#
Lower/Upper Byte Enable
I
A0-A19 (16M)
A0-A20 (32M)
A0-A21 (64M)
A0-A22 (128M)
Address Inputs
I
I/O0-I/O15
Data Inputs/Outputs
I/O
V
CC
/V
CCQ
Power Supply
--
V
SS
/V
SSQ
Ground
--
NC
Not Connection
--
DNU
Do Not Use
--
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
119
A d v a n c e I n f o r m a t i o n
Power Up Sequence
1. Apply power.
2. Maintain stable power (V
CC
min.=2.7V) for a minimum 200 s with
CS1#=high or CS2=low.
Timing Diagrams
Power Up
Notes:
1. After V
CC
reaches V
CC
(Min.), wait 200 s with CS1# high. Then the device gets into the normal operation.
Notes:
1. After V
CC
reaches V
CC
(Min.), wait 200 s with CS2 low. Then the device gets into the normal operation.
Figure 43. Power Up 1 (CS1# Controlled)
Figure 44. Power Up 2 (CS2 Controlled)
Min. 200 s
V
CC
CS1#
CS2
V
CC(Min)
Normal Operation
Power Up Mode
Min. 200s
V
CC
CS1#
CS2
V
CC(Min)
Normal Operation
Power Up Mode
~ ~
~ ~
~ ~
~ ~
120
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
Functional Description
Legend:X = Don't care (must be low or high state).
Absolute Maximum Ratings
Notes:
1. Stresses greater than those listed under "
Absolute Maximum Ratings
" section may cause permanent damage to the device.
Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute
maximum rating conditions longer than one second may affect reliability.
DC Recommended Operating Conditions
Notes:
1. TA=-40 to 85C, unless otherwise specified.
2. Overshoot: V
CC
+1.0V in case of pulse width 20ns.
3. Undershoot: -1.0V in case of pulse width 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Mode
CS1#
CS2
OE#
WE#
LB#
UB#
I/O
1-8
I/O
9-16
Power
Deselected
H
X
X X X
X
High-Z
High-Z
Standby
Deselected
X L
X
X
X
X
High-Z
High-Z
Standby
Deselected
X
X
X
X
H
H
High-Z
High-Z
Standby
Output Disabled
L
H
H
H
L
X
High-Z
High-Z
Active
Outputs Disabled
L
H
H
H
X
L
High-Z
High-Z
Active
Lower Byte Read
L
H
L
H
L
H
D
OUT
High-Z
Active
Upper Byte Read
L
H
L
H
H
L
High-Z
D
OUT
Active
Word Read
L
H
L
H
L
L
D
OUT
D
OUT
Active
Lower Byte Write
L
H
X
L
L
H
D
IN
High-Z
Active
Upper Byte Write
L
H
X
L
H
L
High-Z
D
IN
Active
Word Write
L
H
X
L
L
L
D
IN
D
IN
Active
Item
Symbol
Ratings
Unit
Voltage on any pin relative to V
SS
V
IN ,
V
OUT
-0.2 to V
CC
+0.3V
V
Voltage on V
CC
supply relative to V
SS
V
CC
-0.2 to 3.6V
V
Power Dissipation
P
D
1.0
W
Operating Temperature
T
A
-40 to 85
C
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Power Supply Voltage
2.7
2.9
3.1
V
V
SS
Ground
0
0
0
V
IH
Input High Voltage
2.2
--
V
CC
+ 0.3 (Note 2)
V
IL
Input Low Voltage
-0.2 (Note 3)
--
0.6
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
121
A d v a n c e I n f o r m a t i o n
Capacitance (Ta = 25C, f = 1 MHz)
Note: This parameter is sampled periodically and is not 100% tested.
DC and Operating Characteristics
Common
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
--
8
pF
C
IO
Input/Output Capacitance
V
OUT
= 0V
--
10
pF
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Leakage Current
I
LI
V
IN
=V
SS
to V
CC
-1
--
1
A
Output Leakage Current
I
LO
CS1#=V
IH
or CS2=V
IL
or OE#=V
IH
or WE#=V
IL
or
LB#=UB#=V
IH
, V
IO
=V
SS
to V
CC
-1
--
1
A
Output Low Voltage
V
OL
I
OL
=2.1mA
--
--
0.4
V
Output High Voltage
V
OH
I
OH
=-1.0mA
2.4
--
--
V
122
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
16M pSRAM
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
32M pSRAM
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
I
CC1
Cycle time=1s, 100% duty, I
IO
=0mA,
CS1#
0.2V, LB#0.2V and/or UB#0.2V,
CS2V
CC
-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
--
--
7
mA
I
CC2
Async
Cycle time=Min, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
=V
IH
or V
IL
--
--
30
mA
Page
Cycle time=t
RC
+3t
PC
, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
-V
IH
or V
IL
35
mA
Standby Current (CMOS)
I
SB1
(Note 1)
Other inputs=0-VCC
1. CS1# V
CC
- 0.2, CS2 V
CC
- 0.2V (CS1#
controlled) or
2. 0V CS2 0.2V (CS2 controlled)
--
--
80
mA
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
I
CC1
Cycle time=1s, 100% duty, I
IO
=0mA,
CS1#
0.2V, LB#0.2V and/or UB#0.2V,
CS2
V
CC
-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
--
--
7
mA
I
CC2
Async
Cycle time=Min, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
=V
IH
or V
IL
--
--
35
mA
Page
Cycle time=t
RC
+3t
PC
, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
-V
IH
or V
IL
40
mA
Standby Current (CMOS)
I
SB1
(Note 1)
Other inputs=0-VCC
1. CS1# V
CC
- 0.2, CS2 V
CC
- 0.2V (CS1#
controlled) or
2. 0V CS2 0.2V (CS2 controlled)
--
-- 100 mA
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
123
A d v a n c e I n f o r m a t i o n
64M pSRAM
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
128M pSRAM
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. I
SB1
is measured after 60ms from
the time when standby mode is set up.
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
I
CC1
Cycle time=1s, 100% duty, I
IO
=0mA,
CS1#
0.2V, LB#0.2V and/or UB#0.2V,
CS2V
CC
-0.2V, V
IN
0.2V or V
IN
VCC-0.2V
--
-- TBD mA
I
CC2
Async
Cycle time=Min, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
=V
IH
or V
IL
--
-- TBD mA
Page
Cycle time=t
RC
+3t
PC
, I
IO
=0mA, 100% duty,
CS1#=V
IL
, CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
,
V
IN
-V
IH
or V
IL
TBD mA
Standby Current (CMOS)
I
SB1
(Note 1)
Other inputs=0-VCC
1. CS1# V
CC
- 0.2, CS2 V
CC
- 0.2V (CS1#
controlled) or
2. 0V CS2 0.2V (CS2 controlled)
--
-- TBD mA
Item
Symbol
Test Conditions
Min Typ Max Unit
Average Operating
Current
I
CC1
Cycle time=1s, 100% duty, I
IO
=0mA, CS1#0.2V,
LB#
0.2V and/or UB#0.2V, CS2V
CC
-0.2V, V
IN
0.2V or
V
IN
VCC-0.2V
--
-- TBD mA
I
CC2
Cycle time=t
RC
+3t
PC
, I
IO
=0mA, 100% duty, CS1#=V
IL
,
CS2=V
IH
LB#=V
IL
and/or UB#=V
IL
, V
IN
-V
IH
or V
IL
--
-- TBD mA
Standby Current (CMOS) I
SB1
(Note 1)
Other inputs=0-V
CC
1. CS1# V
CC
- 0.2, CS2 V
CC
- 0.2V (CS1# controlled) or
2. 0V CS2 0.2V (CS2 controlled)
--
-- TBD mA
124
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See Figure 45): CL=50pF
Note: Including scope and jig capacitance.
Figure 45. Output Load
C
L
Dout
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
125
A d v a n c e I n f o r m a t i o n
AC Characteristics (Ta = -40C to 85C, V
CC
= 2.7 to 3.1 V)
Notes:
1. t
WP
(min)=70ns for continuous write operation over 50 times.
Symbol
Parameter
Speed Bins
Unit
70ns
Min
Max
Read
t
RC
Read Cycle Time
70
--
ns
t
AA
Address Access Time
--
70
ns
t
CO
Chip Select to Output
--
70
ns
t
OE
Output Enable to Valid Output
--
35
ns
t
BA
UB#, LB# Access Time
--
70
ns
t
LZ
Chip Select to Low-Z Output
10
--
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
10
--
ns
t
OLZ
Output Enable to Low-Z Output
5
--
ns
t
HZ
Chip Disable to High-Z Output
0
25
ns
t
BHZ
UB#, LB# Disable to High-Z Output
0
25
ns
t
OHZ
Output Disable to High-Z Output
0
25
ns
t
OH
Output Hold from Address Change
5
--
ns
t
PC
Page Cycle Time
25
--
ns
t
PA
Page Access Time
--
20
ns
Wr
i
t
e
t
WC
Write Cycle Time
70
--
ns
t
CW
Chip Select to End of Write
60
--
ns
t
AS
Address Set-up Time
0
--
ns
t
AW
Address Valid to End of Write
60
--
ns
t
BW
UB#, LB# Valid to End of Write
60
--
ns
t
WP
Write Pulse Width
55 (Note 1)
--
ns
t
WR
Write Recovery Time
0
--
ns
t
WHZ
Write to Output High-Z
0
25
ns
t
DW
Data to Write Time Overlap
30
--
ns
t
DH
Data Hold from Write Time
0
--
ns
t
OW
End Write to Output Low-Z
5
--
ns
126
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
Timing Diagrams
Read Timings
Notes:
1. Address Controlled, CS1#=OE#=V
IL
, CS2=WE#=V
IH
, UB# and/or LB#=V
IL
.
Notes:
1. WE#=V
IH
.
Figure 46. Timing Waveform of Read Cycle(1)
Figure 47. Timing Waveform of Read Cycle(2)
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
Data Valid
High-Z
t
RC
t
OH
t
AA
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
t
CO
Address
UB#, LB#
OE#
Data out
CS1#
CS2
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
127
A d v a n c e I n f o r m a t i o n
Notes:
1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.
t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device
to device interconnection.
t
OE
(max) is met only when OE# becomes enabled after t
AA
(max).
If invalid address signals shorter than min. t
RC
are continuously repeated for over 4s, the device needs a normal read
timing (t
RC
) or needs to sustain standby state for min. t
RC
at least once in every 4s.
Write Timings
Figure 48. Timing Waveform of Page Cycle (Page Mode Only)
Figure 49. Write Cycle #1 (WE# Controlled)
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Valid
Address
Valid
Address
Valid
Address
Valid
Address
Valid
Address
t
PC
t
PA
High Z
A1~A0
DQ15~DQ0
OE#
t
OHZ
t
OE
t
CO
t
AA
CS1#
CS2
Address
1)
Address
CS1#
Data Undefined
UB#, LB#
WE#
Data in
Data out
t
WC
t
CW
t
WR
t
AW
t
BW
t
WP
t
AS
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
CS2
128
Type 2 pSRAM
pSRAM_Type02_15A1 June 25, 2004
A d v a n c e I n f o r m a t i o n
Figure 50. Write Cycle #2 (CS1# Controlled)
Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled)
Address
Data Valid
UB#, LB#
WE#
Data in
Data out
High-Z
t
WC
t
CW
t
AW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AS
CS1#
CS2
Address
Data Valid
UB#, LB#
WE#
Data in
Data out
High-Z
t
WC
t
CW
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR
t
AS
CS1#
CS2
June 25, 2004 pSRAM_Type02_15A1
Type 2 pSRAM
129
A d v a n c e I n f o r m a t i o n
Notes:
1. A write occurs during the overlap (t
WP
) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS1# goes high and WE# goes high. The t
WP
is measured from the beginning of
write to the end of write.
2. t
CW
is measured from the CS1# going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS1# or WE# going
high.
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Address
Data Valid
UB#, LB#
WE#
Data in
Data out
High-Z
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS1#
CS2
130
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
pSRAM Type 7
16Mb (1M word x 16-bit)
32Mb (2M word x 16-bit)
64Mb (4M word x 16-bit)
CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low
Power SRAM Interface
Features
Asynchronous SRAM Interface
Fast Access Time
-- tCE = tAA = 60ns max (16M)
-- tCE = tAA = 65ns max (32M/64M)
8 words Page Access Capability
-- tPAA = 20ns max (32M/64M)
Low Voltage Operating Condition
-- VDD = +2.7V to +3.1V
Wide Operating Temperature
-- TA = -30C to +85C
Byte Control by LB and UB
Various Power Down modes
-- Sleep (16M)
-- Sleep, 4M-bit Partial, or 8M-bit Partial (32M)
-- Sleep, 8M-bit Partial, or 16M-bit Partial (64M)
Pin Description
Pin Name
Description
A
21
to A
0
Address Input: A
19
to A
0
for 16M, A
20
to A
0
for 32M, A
21
to A
0
for 64M
CE1#
Chip Enable (Low Active)
CE2#
Chip Enable (High Active)
WE#
Write Enable (Low Active)
OE#
Output Enable (Low Active)
UB#
Upper Byte Control (Low Active)
LB#
Lower Byte Control (Low Active)
DQ
16
-
9
Upper Byte Data Input/Output
DQ
8
-
1
Lower Byte Data Input/Output
V
DD
Power Supply
V
SS
Ground
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
131
A d v a n c e i n f o r m a t i o n
Functional Description
Legend:L = V
IL
, H = V
IH
, X can be either V
IL
or V
IH
, High-Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of
1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
3. Can be either V
IL
or V
IH
but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the
device in power-down mode and maintains the low-power idle state as long as
CE2 is kept Low. CE2 High resumes the device from power-down mode. These
devices have three power-down modes. These can be programmed by series of
read/write operation. Each mode has following features.
The default state is Sleep and it is the lowest power consumption but all data is
lost once CE2 is brought to Low for Power Down. It is not required to program to
Sleep mode after power-up.
Mode
CE2#
CE1#
WE#
OE#
LB#
UB#
A
21-0
DQ
8-1
DQ
16-9
Standby (Deselect)
H
H
X
X
X
X
X
High-Z
High-Z
Output Disable (Note 1)
H
L
H
H
X
X
Note 3
High-Z
High-Z
Output Disable (No Read)
H
L
H
H
Valid
High-Z
High-Z
Read (Upper Byte)
H
L
Valid
High-Z
Output Valid
Read (Lower Byte)
L
H
Valid
Output Valid
High-Z
Read (Word)
L
L
Valid
Output Valid
Output Valid
No Write
L
H
H
H
Valid
Invalid
Invalid
Write (Upper Byte)
H
L
Valid
Invalid
Input Valid
Write (Lower Byte)
L
H
Valid
Input Valid
Invalid
Write (Word)
L
L
Valid
Input Valid
Input Valid
Power Down
L
X
X
X
X
X
X
High-Z
High-Z
32M
64M
Mode
Retention Data
Retention Address
Mode
Retention Data
Retention Address
Sleep (default)
No
N/A
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
132
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between
each read/write operation requires that device be in standby mode. The following
table shows the detail sequence.
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled, and the data written by the second or third cycle is valid as a normal
write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles
is "don't care." If the fourth or fifth cycles are written into different address, the
program is also cancelled but write data might not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial
mode, the written data stored in memory cell array can be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Cycle #
Operation
Address
Data
1st
Read
3FFFFFh (MSB)
Read Data (RDa)
2nd
Write
3FFFFFh
RDa
3rd
Write
3FFFFFh
RDa
4th
Write
3FFFFFh
Don't Care (X)
5th
Write
3FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
Mode
Address
32M
64M
A21
A20
A19
A18 - A0
Binary
Sleep (default)
Sleep (default)
1
1
1
1
3FFFFFh
4M Partial
N/A
1
1
0
1
37FFFFh
8M Partial
8M Partial
1
0
1
1
2FFFFFh
N/A
16M Partial
1
0
0
1
27FFFFh
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
133
A d v a n c e i n f o r m a t i o n
Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions (See Warning Below)
Notes:
1. Maximum DC voltage on input and I/O pins is V
DD
+0.2V. During voltage transitions, inputs can positive overshoot to
V
DD
+1.0V for periods of up to 5 ns.
2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot V
SS
to -1.0V for
periods of up to 5ns.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-
vice's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their FUJITSU representative before-
hand.
Package Capacitance
Test conditions: T
A
= 25C, f = 1.0 MHz
Item
Symbol
Value
Unit
Voltage of V
DD
Supply Relative to V
SS
V
DD
-0.5 to +3.6
V
Voltage at Any Pin Relative to V
SS
V
IN
, V
OUT
-0.5 to +3.6
V
Short Circuit Output Current
I
OUT
50
mA
Storage temperature
T
STG
-55 to +125
C
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
DD
2.7
3.1
V
V
SS
0
0
V
High Level Input Voltage (Note 1)
V
IH
V
DD
0.8
V
DD
+0.2
V
High Level Input Voltage (Note 1)
V
IL
-0.3
V
DD
0.2
V
Ambient Temperature
T
A
-30
85
C
Symbol
Description
Test Setup
Typ
Max
Unit
C
IN1
Address Input Capacitance
V
IN
= 0V
--
5
pF
C
IN2
Control Input Capacitance
V
IN
= 0V
--
5
pF
C
IO
Data Input/Output Capacitance
V
IO
= 0V
--
8
pF
134
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
Notes:
1. All voltages are referenced to V
SS
.
2. DC Characteristics are measured after following POWER-UP timing.
3. I
OUT
depends on the output load conditions.
Parameter
Symbol
Test Conditions
16M
32M
64M
Unit
Min. Max. Min. Max. Min. Max.
Input Leakage
Current
I
LI
V
IN
= V
SS
to V
DD
-1.0 +1.0 -1.0 +1.0 -1.0 +1.0
A
Output Leakage
Current
I
LO
V
OUT
= V
SS
to V
DD
, Output Disable
-1.0 +1.0 -1.0 +1.0 -1.0 +1.0
A
Output High
Voltage Level
V
OH
V
DD
= V
DD
(min), I
OH
= 0.5mA
2.2
--
2.4
--
2.4
--
V
Output Low
Voltage Level
V
OL
I
OL
= 1mA
--
0.4
--
0.4
--
0.4
V
V
DD
Power
Down Current
I
DDPS
V
DD
= V
DD
max.,
V
IN
= V
IH
or V
IL
,
CE2 0.2 V
SLEEP
10
--
10
--
10
A
I
DDP4
4M Partial
N/A
--
40
N/A
A
I
DDP8
8M Partial
N/A
--
50
--
80
A
I
DDP16
16M Partial
N/A
N/A
--
100
A
V
DD
Standby
Current
I
DDS
V
DD
= V
DD
max.,
V
IN
= V
IH
or V
IL
CE1 = CE2 = V
IH
--
1
--
1.5
--
1.5
mA
I
DDS1
V
DD
= V
DD
max.,
V
IN
0.2V or V
IN
V
DD
0.2V,
CE1 = CE2 V
DD
0.2V
TA<
+
85
C
--
100
--
80
--
170
A
TA<
+
40
C
90
A
V
DD
Active Current
I
DDA1
V
DD
= V
DD
max.,
V
IN
= V
IH
or V
IL
,
CE1 = V
IL
and CE2= V
IH
,
I
OUT
=0mA
t
RC
/ t
WC
= min.
--
20
--
30
--
40
mA
I
DDA2
t
RC
/ t
WC
= 1s
--
3
--
3
--
5
mA
V
DD
Page
Read Current
I
DDA3
V
DD
= V
DD
max., V
IN
= V
IH
or V
IL
,
CE1 = V
IL
and CE2= V
IH
,
I
OUT
=0mA, t
PRC
= min.
N/A
--
10
--
10
mA
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
135
A d v a n c e i n f o r m a t i o n
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system
operation, please contact local Spansion representative for the relaxation of 1s limitation.
2. Address should not be changed within minimum t
RC
.
3. The output load 50 pF with 50 ohm termination to V
DD
x 0.5 (16M), The output load 50 pF (32M and 64M).
4. The output load 5pF.
5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 s. In other
words, Page Read Cycle must be closed within 4 s.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. t
RC
(min) and t
PRC
(min) must be satisfied.
10. If actual value of t
WHOL
is shorter than specified minimum values, the actual t
AA
of following Read can become longer by the
amount of subtracting the actual value from the specified minimum value.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
70
1000
65
1000
65
1000
ns
1, 2
CE1# Access Time
t
CE
--
60
--
65
--
65
ns
3
OE# Access Time
t
OE
--
40
--
40
--
40
ns
3
Address Access Time
t
AA
--
60
--
65
--
65
ns
3, 5
LB# / UB# Access Time
t
BA
--
30
--
30
--
30
ns
3
Page Address Access Time
t
PAA
N/A
--
20
--
20
ns
3,6
Page Read Cycle Time
t
PRC
N/A
20
1000
20
1000
ns
1, 6, 7
Output Data Hold Time
t
OH
5
--
5
--
5
--
ns
3
CE1# Low to Output Low-Z
t
CLZ
5
--
5
--
5
--
ns
4
OE# Low to Output Low-Z
t
OLZ
0
--
0
--
0
--
ns
4
LB# / UB# Low to Output Low-Z
t
BLZ
0
--
0
--
0
--
ns
4
CE1# High to Output High-Z
t
CHZ
--
20
--
20
--
20
ns
3
OE# High to Output High-Z
t
OHZ
--
20
--
14
--
14
ns
3
LB# / UB# High to Output High-Z
t
BHZ
--
20
--
20
--
20
ns
3
Address Setup Time to CE1# Low
t
ASC
-6
--
6
--
6
--
ns
Address Setup Time to OE# Low
t
ASO
10
--
10
--
10
--
ns
Address Invalid Time
t
AX
--
10
--
10
--
10
ns
5, 8
Address Hold Time from CE1# High
t
CHAH
-6
--
6
--
6
--
ns
9
Address Hold Time from OE# High
t
OHAH
-6
--
6
--
6
--
ns
WE# High to OE# Low Time for Read
t
WHOL
10
1000
12
--
25
--
ns
10
CE1# High Pulse Width
t
CP
10
--
12
--
12
--
ns
136
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
operation, please contact local Spansion representative for the relaxation of 1s limitation.
2. Minimum value must be equal or greater than the sum of write pulse (t
CW
, t
WP
or t
BW
) and write recovery time (t
WR
).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. t
WPH
minimum is absolute minimum value for device to detect High level. And it is defined at minimum V
IH
level.
8. If OE# is Low after minimum t
OHCL
, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t
RC
is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t
RC
is met and data
bus is in High-Z.
Parameter
Symbol
16M
32M
64M
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
t
WC
70
1000
65
1000
65
1000
ns
1,2
Address Setup Time
t
AS
0
--
0
--
0
--
ns
3
CE1# Write Pulse Width
t
CW
45
--
40
--
40
--
ns
3
WE# Write Pulse Width
t
WP
45
--
40
--
40
--
ns
3
LB#/UB# Write Pulse Width
t
BW
45
--
40
--
40
--
ns
3
LB#/UB# Byte Mask Setup Time
t
BS
-5
--
5
--
5
--
ns
4
LB#/UB# Byte Mask Hold Time
t
BH
-5
--
5
--
5
--
ns
5
Write Recovery Time
t
WR
0
--
0
--
0
--
ns
6
CE1# High Pulse Width
t
CP
10
--
12
--
12
--
ns
WE# High Pulse Width
t
WHP
7.5
1000
7.5
1000
7.5
1000
ns
7
LB#/UB# High Pulse Width
t
BHP
10
1000
12
1000
12
1000
ns
Data Setup Time
t
DS
15
--
12
--
12
--
ns
Data Hold Time
t
DH
0
--
0
--
0
--
ns
OE# High to CE1# Low Setup Time for Write
t
OHCL
-5
--
5
--
5
--
ns
8
OE# High to Address Setup Time for Write
t
OES
0
--
0
--
0
--
ns
9
LB# and UB# Write Pulse Overlap
t
BWO
30
--
30
--
30
--
ns
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
137
A d v a n c e i n f o r m a t i o n
AC Characteristics
Power Down Parameters
Notes:
1. Applicable also to power-up.
2. Applicable when 4Mb and 8Mb Partial modes are programmed.
Other Timing Parameters
Notes:
1. Some data might be written into any address location if t
CHWX
(min) is not satisfied.
2. The Input Transition Time (t
T
) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC
specification of some of the timing parameters.
Parameter
Symbol
16M
32M
64M
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
CE2 Low Setup Time for Power Down Entry
t
CSP
10
--
10
--
10
--
ns
CE2 Low Hold Time after Power Down Entry
t
C2LP
80
--
65
--
65
--
ns
CE1# High Hold Time following CE2 High after Power
Down Exit [SLEEP mode only]
t
CHH
300
--
300
--
300
--
s
1
CE1# High Hold Time following CE2 High after Power
Down Exit [not in SLEEP mode]
t
CHHP
N/A
1
--
1
--
s
2
CE1# High Setup Time following CE2 High after Power
Down Exit
t
CHS
0
--
0
--
0
--
ns
1
Parameter
Symbol
16M
32M
64M
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
CE1# High to OE# Invalid Time for Standby Entry
t
CHOX
10
--
10
--
10
--
ns
CE1# High to WE# Invalid Time for Standby Entry
t
CHWX
10
--
10
--
10
--
ns
1
CE2 Low Hold Time after Power-up
t
C2LH
50
--
50
--
50
--
s
CE1# High Hold Time following CE2 High after Power-up
t
CHH
300
--
300
--
300
--
s
Input Transition Time
t
T
1
25
1
25
1
25
ns
2
138
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
AC Characteristics
AC Test Conditions
AC Measurement Output Load Circuits
Figure 53. AC Output Load Circuit 16 Mb
Figure 54. AC Output Load Circuit 32 Mb and 64 Mb
Symbol
Description
Test Setup
Value
Unit
Note
V
IH
Input High Level
V
DD
* 0.8
V
V
IL
Input Low Level
V
DD
* 0.2
V
V
REF
Input Timing Measurement Level
V
DD
* 0.5
V
t
T
Input Transition Time
Between V
IL
and V
IH
5
ns
DEVICE
UNDER
TEST
V
DD
V
DD
*0.5 V
V
SS
OUT
0.1
F
50 pF
50 ohm
DEVICE
UNDER
TEST
V
DD
V
SS
OUT
0.1
F
50pF
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
139
A d v a n c e i n f o r m a t i o n
Timing Diagrams
Read Timings
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 55. Read Timing #1 (Basic Timing)
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 56. Read Timing #2 (OE# Address Access
t
CE
VALID DATA OUTPUT
ADDRESS
CE1#
DQ
(Output)
OE#
t
CHZ
t
RC
t
OLZ
t
CHAH
t
CP
ADDRESS VALID
t
ASC
t
ASC
t
OHZ
t
OH
t
BHZ
LB#/ UB#
t
OE
t
BA
t
BLZ
t
CLZ
t
AA
VALID DATA OUTPUT
ADDRESS
CE1#
DQ
(Output)
t
OHZ
t
OE
t
RC
t
OLZ
ADDRESS VALID
VALID DATA OUTPUT
ADDRESS VALID
t
RC
t
OH
t
OH
OE#
t
Ax
Low
t
AA
t
OHAH
t
ASO
LB#/UB#
140
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 57. Read Timing #3 (LB#/UB# Byte Access)
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 58. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)
t
AA
VALID DATA
OUTPUT
ADDRESS
DQ1-8
(Output)
UB#
t
BHZ
t
BA
t
RC
t
BLZ
ADDRESS VALID
VALID DATA
OUTPUT
t
BHZ
t
OH
LB#
t
AX
Low
t
BA
t
Ax
DQ9-16
(Output)
t
BLZ
t
BA
t
BLZ
t
OH
t
BHZ
t
OH
VALID DATA OUTPUT
CE1#, OE#
VALID DATA OUTPUT
(Normal Access)
ADDRESS
(A2-A0)
CE1#
DQ
(Output)
OE#
t
CHZ
t
CE
t
RC
t
CLZ
ADDRESS VALID
VALID DATA OUTPUT
(Page Access)
ADDRESS
VALID
t
PRC
t
OH
t
OH
t
CHAH
t
PAA
ADDRESS
(A21-A3)
ADDRESS VALID
t
PAA
t
OH
t
PRC
t
PAA
t
PRC
t
OH
ADDRESS
VALID
ADDRESS
VALID
t
RC
t
ASC
LB#/UB#
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
141
A d v a n c e i n f o r m a t i o n
Notes:
1. This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 59. Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
Note: This timing diagram assumes CE2=H.
Figure 60. Write Timing #1 (Basic Timing)
VALID DATA OUTPUT
(Normal Access)
ADDRESS
(A2-A0)
CE1#
DQ
(Output)
OE#
t
OE
t
RC
t
OLZ
t
BLZ
t
AA
VALID DATA OUTPUT
(Page Access)
ADDRESS
VALID
t
PRC
t
OH
t
OH
t
RC
t
PAA
ADDRESS
(A21-A3)
ADDRESS VALID
t
AA
t
OH
ADDRESS VALID
t
RC
t
PAA
t
PRC
t
OH
ADDRESS
VALID
ADDRESS
VALID
t
RC
t
Ax
t
AX
t
BA
ADDRESS
VALID
Low
t
ASO
LB#/UB#
t
AS
VALID DATA INPUT
ADDRESS
CE1#
DQ
(Input)
WE#
t
DH
t
DS
t
WC
t
WR
t
WP
t
CW
LB#, UB#
t
AS
t
BW
ADDRESS VALID
t
AS
t
AS
t
WR
OE#
t
OHCL
t
AS
t
AS
t
WR
t
CP
t
WHP
t
BHP
142
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
Note:This timing diagram assumes CE2=H.
Figure 61. Write Timing #2 (WE# Control)
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 62. Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
t
AS
ADDRESS
WE#
CE1#
t
WC
t
WR
t
WP
LB#, UB#
ADDRESS VALID
t
AS
t
WR
t
WP
VALID DATA INPUT
DQ
(Input)
t
DH
t
DS
OE#
t
OES
t
OHZ
t
WC
VALID DATA INPUT
t
DH
t
DS
Low
ADDRESS VALID
t
OHAH
t
WHP
t
AS
ADDRESS
WE#
CE1#
t
WC
t
WR
t
WP
LB#
ADDRESS VALID
t
AS
t
WR
t
WP
VALID DATA INPUT
DQ1-8
(Input)
t
DH
t
DS
UB#
t
WC
t
DH
t
DS
Low
ADDRESS VALID
DQ9-16
(Input)
t
BS
t
BH
t
BS
t
BH
t
WHP
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
143
A d v a n c e i n f o r m a t i o n
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
t
AS
ADDRESS
WE#
CE1#
t
WC
t
WR
t
BW
LB#
ADDRESS VALID
t
AS
t
WR
t
BW
VALID DATA INPUT
DQ1-8
(Input)
t
DH
t
DS
UB#
t
WC
VALID DATA INPUT
t
DH
t
DS
Low
ADDRESS VALID
DQ9-16
(Input)
t
BS
t
BH
t
BS
t
BH
t
WHP
t
AS
ADDRESS
WE#
CE1#
t
WC
t
WR
t
BW
LB#
ADDRESS VALID
t
AS
t
WR
t
BW
DQ1-8
(Input)
t
DH
t
DS
UB#
t
WC
t
DH
t
DS
Low
ADDRESS VALID
DQ9-16
(Input)
t
DH
t
DS
t
AS
t
WR
t
BW
t
AS
t
WR
t
BW
t
DH
t
DS
VALID
DATA INPUT
VALID
DATA INPUT
VALID
DATA INPUT
VALID
DATA INPUT
t
BWO
t
BWO
t
BHP
t
BHP
144
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
Read/Write Timings
Notes:
1. This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
Figure 65. Read/Write Timing #1-1 (CE1# Control)
Notes:
1. This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 66. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
t
WC
t
CW
OE#
t
OHCL
UB#, LB#
t
CHAH
t
CP
WRITE ADDRESS
t
AS
t
RC
WRITE DATA INPUT
t
DS
t
CHZ
t
OH
t
CP
t
CE
t
ASC
READ ADDRESS
t
WR
t
CHAH
t
DH
t
CLZ
t
OH
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
t
WC
t
WP
OE#
t
OHCL
UB#, LB#
t
OE
t
CHAH
t
CP
WRITE ADDRESS
t
AS
t
RC
WRITE DATA INPUT
t
DS
t
CHZ
t
OH
t
CP
t
CE
t
ASC
READ ADDRESS
t
WR
t
CHAH
t
DH
t
OLZ
t
OH
READ DATA OUTPUT
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
145
A d v a n c e i n f o r m a t i o n
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 67. Read / Write Timing #2 (OE#, WE# Control)
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
t
WC
t
WP
OE#
UB#, LB#
t
OE
WRITE ADDRESS
t
AS
t
RC
WRITE DATA INPUT
t
DS
t
OHZ
t
OH
t
AA
READ ADDRESS
t
WR
t
DH
t
OLZ
t
OH
READ DATA OUTPUT
t
OHZ
Low
t
ASO
t
OHAH
t
OES
t
OHAH
t
WHOL
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
t
WC
t
BW
OE#
UB#, LB#
t
BA
WRITE ADDRESS
t
AS
t
RC
WRITE DATA INPUT
t
DS
t
BHZ
t
OH
t
AA
READ ADDRESS
t
DH
t
BLZ
t
OH
READ DATA OUTPUT
t
BHZ
Low
t
ASO
t
OHAH
t
OHAH
t
OES
t
WHOL
t
WR
146
pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
A d v a n c e I n f o r m a t i o n
Note: The t
C2LH
specifies after V
DD
reaches specified minimum level.
Figure 69. Power-up Timing #1
Note: The t
CHH
specifies after V
DD
reaches specified minimum level and applicable to both CE1# and CE2.
Figure 70. Power-up Timing #2
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and
Power-Down program was not performed prior to this reset.
Figure 71. Power Down Entry and Exit Timing
t
C2LH
CE1#
V
DD
V
DD
min
0V
CE2
t
CHH
t
CHS
CE1#
V
DD
V
DD
min
0V
CE2
t
CHH
t
CSP
CE1#
Power Down Entry
CE2
t
C2LP
t
CHH
(t
CHHP
)
Power Down Mode
Power Down Exit
t
CHS
DQ
High-Z
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
147
A d v a n c e i n f o r m a t i o n
Note: Both t
CHOX
and t
CHWX
define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
t
RC
(min) period for Standby mode from CE1# Low to High transition.
Figure 72. Standby Entry Timing after Read or Write
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in page 132. If not, the operation and data are not guaranteed.
3. After t
CP
following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 73. Power Down Program Timing (for 32M/64M Only)
t
CHOX
CE1#
OE#
WE#
Active (Read)
Standby
Active (Write)
Standby
t
CHWX
ADDRESS
CE1#
DQ*
3
WE#
t
RC
OE#
LB#, UB#
RDa
MSB*
1
MSB*
1
MSB*
1
MSB*
1
MSB*
1
Key*
2
t
WC
t
WC
t
WC
t
WC
t
RC
t
CP
t
CP
t
CP
t
CP
t
CP
t
CP
*
3
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
RDa
RDa
X
X
RDb
148
Revision Summary
S71PL129Jxx_00_A5_E December 23, 2004
A d v a n c e I n f o r m a t i o n
Revision Summary
Revision A0 (June 9, 2004)
Initial release.
Revision A1 (July 19, 2004)
Global Change
Change all instances of FASL to Spansion
Added Colophon text.
"Product Selector Guide" on page 2
Replaced "S71PL129JA0-9Z" with "S71PL129JA0-9P".
"Ordering Information" on page 9
In Model Number section replaced pSRAM part number with "See valid combinations table".
Revision A2 (July 21, 2004)
"Connection Diagram" on page 7
Changed Row D of pinout for accuracy.
Added the following note: "May be shared depending on density:A21 is shared for the 64M pSRAM
configuration;A20 is shred for the 32M pSRAM configuration; A19 is shared for the 16M pSRAM
configuration.
Revision A3 (October 18, 2004)
Core Flash Module
Replaced core flash module from S29PL127J_064J_032J_MCP_00_A1_E to
S29PL129J_MCP_00_A0
Revision A4 (November 30, 2004)
Product Selector Guide
Added a new model number.
Valid Combinations Table
Whole table updated with new OPNs.
Revision A5 (December 23, 2004)
Connection Diagram
Updated pin L5.
Valid Combinations Table
Added a note to the bottom of the table.
December 23, 2004 S71PL129Jxx_00_A5_E
Revision Summary
149
A d v a n c e I n f o r m a t i o n
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for
any
use
that
includes
fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2)
for any use where chance of failure is intolerable
(i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable
to
you and/or any third party for any claims or damages arising in connection with above-
mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on ex-
port under the Foreign Exchange and Foreign Trade Law of Japan
, the US Export Administration Regulations or the applicable laws of any other country,
the
prior authorization by
the respective government entity
will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright 2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product
names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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