Preliminary Rev. 0.33 6/02
Copyright 2002 by Silicon Laboratories
Si5364-EVB-033
S i 5 3 6 4 - E V B
E
V A L U A T I O N
B
O A R D
F O R
Si 5 3 6 4 S O N E T / S D H P
R E C I S I O N
P
O R T
C
A R D
C
L O C K
I C
Description
The Si5364-EVB is the evaluation board for the Si5364
SONET/SDH Precision Port Card Clock IC. This
evaluation board provides access to all signals
associated with normal operation of the device. This
circuit board also is designed to provide access to signals
that are reserved for factory testing purposes.
Features
Si5364 device can be powered directly from either a
3.3 or 2.5 V supply
Differential I/Os ac-coupled on board
Differential inputs terminated on board
Control input signals are switch/jumper configurable
Status outputs brought out to headers for access
LED status indicators reflect state of status outputs
LED status indicators can be disabled for device
power measurements
Function Block Diagram
C LKIN _B
t
e
x
t
t
e
x
t
t
e
x
t
t
e
x
t
t
e
x
t
t
e
x
t
t
e
x
t
t
e
x
t
S i5364
+
+
+
+
+
+
+
C LKIN_A
C LKIN_B
R EF/CLK IN_ F
C LKO UT _1
C LKO UT _2
C LKO UT _3
C LKO UT _4
Co ntro l
In p uts
Sta tu s
Ou tp uts
Co ntro l
In pu t
J um p er
He a de r
Sta tu s
O utpu t
Sig na l
He a de r
L ED
D riv ers
L ED
Statu s
Ind ica to rs
F a cto ry
T e st
In pu t
He a de r
Fa cto ry
T es t
O utpu t
He a de r
Fa cto ry
T e st
Se rial
In p ut
Fa ctory
T e st
Serial
O u tpu t
Po wer
S up ply
In pu t
3 .3 V/2 .5 V
Su p ply
Sele ction
F ac tory
T e st
An a log
Ou tp ut
C LKIN _A
R E F/C LK IN _F
C LKO U T_1
C LKO U T_2
C LKO U T_3
C LKO U T_4
50
50
50
50
50
50
50
50
3.3 V or 2.5 V
S upply
2.5 V L DO
R egula tor
S i 5 3 6 4 - E V B
2
Preliminary Rev. 0.33
Functional Description
The Si5364-EVB is the evaluation board for the Si5364
SONET/SDH Precision Port Card Clock IC. This
evaluation board provides access to all signals
associated with normal operation of the device. This
circuit board also is designed to provide access to signals
that are reserved for factory testing purposes.
Power Supply Selection and Connections
The Si5364-EVB board is switch selectable for
operation using either a single 3.3 V or a single 2.5 V
supply.
For operation using a 3.3 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board's power connector, J15.
2. Remove the connection between VDD33 and VDD25 by
removing the jumper on header JPI.
3. Set VSEL33 high by sliding the switch on the VSEL33
(JP3) to the side marked "1".
4. Connect the power supply ground lead and 3.3 V supply
lead to the GND and VDD terminals of the board's power
connector, J15.
For operation using a 2.5 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board's power connector, J15.
2. Set VSEL33 low by sliding the switch on the VSEL33 (JP3)
to the side marked "0".
3. Connect VDD33 and VDD25 by installing a jumper
between one of the 3.3 V pins and one of the 2.5 V pins on
header JPI.
4. Connect the power supply ground lead and 2.5 V supply
lead to the GND and VDD terminals of the board's power
connector, J15.
Power Consumption
Typical supply current draw for the Si5364-EVB with LED
indicators disabled and one clock output enabled is
120 mA. Each additional clock output that is enabled
adds approximately 15 mA. LED indicators, when
enabled, adds approximately 8 mA for each indicator that
is illuminated.
Si5364 Control Inputs
Most of the control inputs to the Si5364 are routed to the
center post of a SPDT switch located at JP1. The
switches are wired with the signal on the center pin,
VDD33 on one side pin, and GND on the other side pin.
Each input is easily configurable to a high or a low state.
There are three inputs to the Si5364 that are not routed to
switches at JP1. Two of these signals are INCDELAY and
DECDELAY. They are routed to push button switches
SW1 and SW2, respectively, through headers JP4 and
JP5. Inverters U6 and U7 condition the action of these
switches before being sent to the Si5364 device.
Pressing and releasing these switches provides a single
pulse to the control input for the Si5364. This is a
convenient method for evaluating the operation of the
INCDELAY and DECDELAY functions. Resistors R26
and R27 allow the user to disconnect the switches from
the device and drive the inputs from another source. JP4
and JP5 are not populated when shipped from the
factory. If an external source is required to drive the
INCDELAY and DECDELAY inputs, then populate these
two headers. This provides the user a convenient location
to connect the source.
Each LVTTL input on the Si5364 device has an internal
pull-down mechanism. The control inputs default to a low
state if no device drives the input.
RSTN/CAL Settings for Normal Operation
and Self-Calibration
The RSTN/CAL signal is an LVTTL input to the Si5364
and has an on-chip pull down mechanism. This pin must
be set high to enable normal operation of the Si5364
device.
Setting RSTN/CAL low forces the Si5364 into a reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence.
The Si5364 device automatically initiates a self-
calibration at power-up if the RSTN/CAL signal is held
high. A self-calibration of the device also can be manually
initiated by pushing the RSTN/CAL switch, SW3, then
releasing. Self-calibration must be initiated manually after
changing the state of either the BWSEL[1:0] control
inputs or the FEC[1:0] inputs.
Whether manually initiated or automatically initiated at
power-up, the self-calibration process requires the
presence of a valid input clock. If the self-calibration is
initiated without a valid clock present, the device waits for
a valid clock before completing the self-calibration. The
Si5364 clock outputs drift to the lower end of the
operating frequency range as the device waits for a valid
clock. After the input clock is validated, the calibration
process runs to completion, the device locks to the input,
and the clock outputs shifts to their target frequencies.
Subsequent losses of the input clock do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.
S i 53 64 -E V B
Preliminary Rev. 0.33
3
Status Signals
The status outputs from the Si5364 device are each
routed to one pin of a two-row header, JP11. The header
is wired so that the signals are present on one side of the
header and a ground reference is present on the other.
The letter S marks the row of signal pins and the row of
ground pins is marked with the letter G.
On the Si5364-EVB board, the status outputs are also
routed to two buffer/driver ICs (U4 and U5) that drive one
LED indicator for each status signal.
Enabling and Disabling the Status Indicator
LEDs
The status LED driver outputs can be disabled. The
disabled driver outputs are placed into a high impedance
state to get a more accurate measurement of the current/
power being consumed by the Si5364 device. The LED
drivers are enabled when the switch at JP9 is switched to
ON. The driver outputs are disabled when the switch is
set to OFF.
Factory Test Headers
Locations for headers JP8 and JP10 are included on the
SI5364-EVB for factory testing. For customer evaluation,
these locations are not populated.
Differential Clock Input Signals
The differential clock inputs to the Si5364-EVB are
terminated on the board at a location near the input SMA
connectors. The input SMA connectors are ac coupled to
the termination circuit. The termination circuit consists of
two 50
resistors and a 0.1
F capacitor, connected so
that the positive and negative inputs of the differential pair
each see a 50
termination to "ac ground", and the line-
to-line termination impedance is 100
. The signals are
then routed to the Si5364 device.
Single-ended operation is accomplished by supplying a
signal to one of the differential inputs, typically the
positive input. The other input should be shorted to
ground with an SMA shorting plug.
Differential Clock Output Signals
The differential clock outputs from the Si5364 device are
routed to the perimeter of the circuit board using 50
transmission structures. The capacitors that provide ac-
coupling are located near the clock output SMA
connectors.
Internal Regulator Compensation
The Si5364-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0
resistor. The
capacitor pads are populated with a low ESR 33
F
tantalum capacitor. This is the suggested compensation
circuit for Si5364 devices.
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
The acceptable range for the time constant at this node
is 15
s to 50
s. The capacitor used on the board is a
33
F capacitor with an ESR of .8
. This yields a time
constant of 26.4
s. The designer could decide to use a
330
F capacitor with an ESR of .15
. This yields a
time constant of 49.5
s. Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330
F case provides greater
noise filtering. However, the large case size of the
330
F capacitor might make it impractical for many
applications. The Si5364 device is specified with the
33
F cap.
Default Jumper Settings
The default jumper settings for the Si5364-EVB board are
given in Table 1 on page 4. These settings configure the
board for operation from a 3.3 V supply.
S i 5 3 6 4 - E V B
4
Preliminary Rev. 0.33
Table 1. Si5364-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
Signal
State
Notes
JP3
VSEL33
1
Si5364 device Internal Regulator enabled
JP12
VDD33
Open
Si5364 device VDD33 pins not connected to 2.5 V supply
plane
JP1
VALTIME
0
100 ms Validation Time
SMC/S3N
1
SONET Minimum Clock criteria selected
DSBLFOS
0
Frequency Offset alarms enabled
RVRT
1
Revertive clock switching mode selected
AUTOSEL
1
Automatic input Selection enabled
DSBLFSYNC
0
FSYNC output enabled
MANCNTRL[0]
0
CLKIN_A would be selected if AUTOSEL = 0
MANCNTRL[1]
1
CLKIN_A would be selected if AUTOSEL = 0
FEC[0]
0
FEC scaling factor = 1/1 (no FEC scaling)
FEC[1]
0
FEC scaling factor = 1/1 (no FEC scaling)
BWSEL[0]
1
Loop Bandwidth = 6400 Hz
BWSEL[1]
1
Loop Bandwidth = 6400 Hz
FRQSEL_1[0]
1
CLKOUT_1 = 622 MHz Range
FRQSEL_1[1]
1
CLKOUT_1 = 622 MHz Range
FRQSEL_2[0]
1
CLKOUT_2 = 622 MHz Range
FRQSEL_2[1]
1
CLKOUT_2 = 622 MHz Range
FRQSEL_3[0]
1
CLKOUT_3 = 622 MHz Range
FRQSEL_3[1]
1
CLKOUT_3 = 622 MHz Range
FRQSEL_4[0]
1
CLKOUT_4 = 622 MHz Range
FRQSEL_4[1]
1
CLKOUT_4 = 622 MHz Range
FXD_DELAY
0
Fixed Delay mode disabled
JP9
LED ENABLE_N
ON
LED Status Indicators enabled
JP2
SYNCIN
No Jumper
Installed
Header for SYNCIN input signal
JP15
FSYNC
No Jumper
Installed
Header for FSYNC output signal
S i 53 64 -E V B
Preliminary Rev. 0.33
5
For engineering test purposes only. Not
needed for customer application.
CLKIN_A+
CLKIN_B+
REF/CLKIN_F+
CLKIN_B-
CLKIN_A-
REF/CLKIN_F-
FRQSEL_1[0] FRQSEL_1[1] FRQSEL_2[0] FRQSEL_2[1] FRQSEL_3[0] FRQSEL_3[1] FRQSEL_4[0] FRQSEL_4[1] BWSEL[0] BWSEL[1] FEC[0] FEC[1] MANCNTRL[0] MANCNTRL[1] DSBLFSYNC AUTOSEL RVRT RSTN/CAL VALTI
M
E
SMC/S3N DSBLFOS FXDDELAY SYNCIN INCDELAY DECDELAY VSEL33
RSTN/CAL
VALTI
M
E
SMC/S3N
DSBLFOS
RVRT
AUTOSEL
DSBLFSYNC
MANCNTRL[0]
MANCNTRL[1]
FEC[0]
FEC[1]
BWSEL[0]
BWSEL[1]
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
FXDDELAY
SYNCIN
VSEL33
CLKOUT_1+ CLKOUT_1- CLKOUT_2+ CLKOUT_2- CLKOUT_3+ CLKOUT_3- CLKOUT_4+ CLKOUT_4-
LOS_A LOS_B LOS_F FOS_A FOS_B A_ACTV B_ACTV F_ACTV DH_ACTV CAL_ACTV FSYNC
RES/DEV_ID[0] RES-DEV)ID[1] REV/DEV_ID[2] RES/ANAOUT
RES/TMODE[0] RES/TMODE[1] RES/TMODE[2] RES/REFIN[0] RES/REFIN[1] RES/REFIN[2] RES/PFDTEST
INCDELAY
RES/DEV_ID[0] RES-DEV)ID[1] REV/DEV_ID[2] RES/ANAOUT
LOS_A LOS_B LOS_F FOS_A FOS_B A_ACTV B_ACTV F_ACTV DH_ACTV CAL_ACTV
FSYNC
LOS_A
LOS_B
LOS_F
FOS_A FOS_B
A_ACTV
B_ACTV
F_ACTV
DH_ACTV CAL_ACTV
RES/PFDTEST
DECDELAY
RES/TMODE[0]
RES/REFIN[2]
RES/TMODE[1]
RES/TMODE[2]
RES/REFIN[0]
RES/REFIN[1]
2.5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
JP1
1
2
3 4
5
6 7
8
9 10
11
12 13
14
15 16
17
18 19
20
21 22
23
24 25
26
27 28
29
30 31
32
33 34
35
36 37
38
39 40
41
42 43
44
45 46
47
48 49
50
51 52
53
54 55
56
57 58
59
60 61
62
63
D10
JP11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R4
1k, 0603
R5
1k, 0603
R6
1k, 0603
R7
1k, 0603
JP4
1
2
3
12 3
R8
1k, 0603
R9
120, 0603
R10
120, 0603
R11
120, 0603
R12
120, 0603
JP9
1x3 HEADER
1
2
3
12 3
JP10
1
2
3
4
5
6
7
8
12 34 56 78
SW3
101-01
6
1
R13
1k, 0603
JP6
1
2
3
12 3
C1
0.1uf, 0603
R29
0, 0402
C2
0.1uf, 0603
JP15
12
U7
74SZ14
2
3
4
5
U4
74LCX
244
1
2 4 6 8
11 13 15 17
19
18 16 14 12
9 7 5 3
20
10
1OE
1A1 1A2 1A3 1A4
2A1 2A2 2A3 2A4
2OE
1Y1 1Y2 1Y3 1Y4
2Y1 2Y2 2Y3 2Y4
VCC
GND
U5
74LCX
244
1
2 4 6 8
11 13 15 17
19
18 16 14 12
9 7 5 3
20
10
1OE
1A1 1A2 1A3 1A4
2A1 2A2 2A3 2A4
2OE
1Y1 1Y2 1Y3 1Y4
2Y1 2Y2 2Y3 2Y4
VCC
GND
JP8
7x3 HEADER
1
2
3 4
5
6 7
8
9 10
11
12 13
14
15 16
17
18 19
20
21
12 3 45 6 78 9 10
11
12 13
14
15 16
17
18 19
20
21
JP2
1x3 HEADER
1
2
3
12 3
U1
Si5364_revB
A2
A3
A4
A5 A6 A7 A8 A9 A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3 C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1 F2
F3
F4
F5
F6
F7
F8
F9
F10
G1 G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3 J4
J5
J6 J7
J8
J9
J10
K1
K2
K3
K4
K5
K6 K7
K8
K9
K10
H10
BWSEL[0]
FEC[0]
MANCNTRL[0]
FOS_A FOS_B A_ACTV B_ACTV F_ACTV
DH_ACTV
AUTOSEL
BWSEL[1]
FEC[1]
MANCNTRL[1]
DSBLFOS
RES/DEV_ID[2]
RES/DEV_ID[1]
RES/DEV_ID[0]
SMC/S3N
CAL_ACTV
CLKIN_A-
CLKIN_A+
INCDELAY DECDELAY
FXDDELAY
RES/ANAOUT
RES/TMODE[2]
RES/TMODE[1]
RES/TMODE[0]
RVRT
RES/PFDTEST
RES/REFIN[0]
VSEL33
GND
GND
GND
GND
GND
GND
LOS_F
REF/CLKIN_F-
REF/CLKIN_F+
GND
VDD33
VDD33
VDD33
VDD25
VDD25
VDD25
LOS_B
RES/REFIN[1] RES/REFIN[2]
GND
VDD33
VDD33
VDD33
VDD25
VDD25
VDD25
LOS_A
CLKIN_B+ CLKIN_B-
GND
VDD25
VDD25
VDD25
VDD25
VDD25
FRQSEL_4[0]
CLKOUT_4-
SYNCIN
DSBLFSYNC
GND
GND
GND
GND
GND
VDD25
FRQSEL_4[1]
FSYNC
VALTIME
FRQSEL_1[0] FRQSEL_1[1]
GND
FRQSEL_2[0] FRQSEL_2[1]
VDD25
FRQSEL_3[1]
FRQSEL_3[0]
REXT
RSTN/CAL
CLKOUT_1-
CLKOUT_1+
GND
CLKOUT_2+ CLKOUT_2-
VDD25
CLKOUT_3-
CLKOUT_3+
CLKOUT_4+
R28
4.99k, 0603
JP3
1x3 HEADER
1
2
3
12 3
U6
74SZ14
2
3
4
5
R26
0, 0402
R27
0, 0402
D1
JP5
1
2
3
12 3
D2
D3
R1
10k, 0603
D4
D5
D6
D7
SW1
101-01
6
1
D8
SW2
101-01
6
1
R2
100k, 0402
D9
R3
100k, 0402
C3 0.1uf, 0603
C4 0.1uf, 0603
F
i
g
u
r
e 1.
Si
53
64
-EV
B
T
y
p
i
cal
A
p
p
l
i
c
ati
o
n
Sc
h
e
m
a
t
i
c
(p
ag
e 1
o
f
2
)
S i 5 3 6 4 - E V B
6
Preliminary Rev. 0.33
CLKIN_A-
CLKIN_A+
CLKIN_B-
CLKIN_B+
REF/CLKIN_F+
REF/CLKIN_F-
CLKOUT_1+
CLKOUT_1-
CLKOUT_2+
CLKOUT_2-
CLKOUT_3+
CLKOUT_3-
CLKOUT_4+
CLKOUT_4-
3.3V
2.5V
C34
0.1uf, 0603
C35
0.1uf, 0603
J3
SMA, thruhole RA
1
2
SIG
BODY
C19
0.1uf, 0603
R14 49.9, 0603
C20
0.1uf, 0603
+
C26 33uf, 3528
C36
0.1uf, 0603
+
C33 33uf, 3528
C29 22pf, 0603
C37
0.1uf, 0603
L1
600 ohm, 1206
C21
0.1uf, 0603
R15 49.9, 0603
JP12
12
C38
0.1uf, 0603
C39
0.1uf, 0603
J12
SMA, thruhole RA
1
2
SIG
BODY
R20
49.9, 0603
J9
SMA, thruhole RA
1
2
SIG
BODY
C40
0.1uf, 0603
C12
0.1uf, 0603
J6
SMA, thruhole RA
1
2
SIG
BODY
C41
0.1uf, 0603
R21
49.9, 0603
C13
0.1uf, 0603
C27 0.1uf, 0603
C14
0.1uf, 0603
R22
49.9, 0603
J2
SMA, thruhole RA
1
2
SIG
BODY
R23
49.9, 0603
C8 Spare, 0402
C5
0.1uf, 0603
C9 Spare, 0402
J15
power connector, 2 pin
POS1
POS2
C15 Spare, 0402
J14
SMA, thruhole RA
1
2
SIG
BODY
C16 Spare, 0402
C6
0.1uf, 0603
C22 Spare, 0402
J11
SMA, thruhole RA
1
2
SIG
BODY
C23 Spare, 0402
J8
SMA, thruhole RA
1
2
SIG
BODY
C7
0.1uf, 0603
J5
SMA, thruhole RA
1
2
SIG
BODY
C28 2200pf, 0603
R16
0, 0402
J4
SMA, thruhole RA
1
2
SIG
BODY
R17
0, 0402
R18
0, 0402
J1
SMA, thruhole RA
1
2
SIG
BODY
R19
0, 0402
R24
0, 0402
R25
0, 0402
J13
SMA, thruhole RA
1
2
SIG
BODY
R32
0, 0402
J10
SMA, thruhole RA
1
2
SIG
BODY
+
C30 330uf, 7343
+
C31 330uf, 7343
J7
SMA, thruhole RA
1
2
SIG
BODY
+
C32 330uf, 7343
F
i
g
u
r
e 2.
Si
53
64
-EV
B
T
y
p
i
cal
A
p
p
l
i
c
ati
o
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Sc
h
e
m
a
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i
c
(p
ag
e 2
o
f
2
)
S i 53 64 -E V B
Preliminary Rev. 0.33
7
Bill of Materials
Reference
Description
Manufacturer
Part Number
C1-C7,C12-C14,C19-C21
0.1uf, 0603
Venkel
C0603X7R160-104KNE
C27,C34-C41
C8,C9,C15,C16,C22,C23
Spare, 0402
C26,C33
33uf, 3528
Venkel
TA6R3TCR336KBR
C28
2200pf, 0603
Venkel
C0603X7R160-222KNE
C29
22pf, 0603
Venkel
C0603C0G500-220KNE
C30,C31,C32
330uf, 7343
Venkel
TA6R3TCR337KER
D1,D2,D3,D4,D5,D10
LED, SM, red, superbright
Panasonic
LN1271RAL
D6,D7,D8,D9
LED, SM, green
Panasonic
LN1371G
JP1
21x3 HEADER
JP2,JP3,JP4,JP5,JP6,JP9
1x3 HEADER
JP8
7x3 HEADER
JP10
4x2 HEADER
JP11
10x2 Header
JP12,JP15
HEADER 2X1
J1,J2,J3,J4,J5,J6,J7,J8,
SMA, thruhole RA
Johnson Components 142-0701-301
J9,J10,J11,J12,J13,J14
J15
power connector, 2 pin
Phoenix Contact
140-A-111-02 1729018
L1
600 ohm, 1206
MURATA
BLM31A601S
R1
10k, 0603
Venkel
CR0603-16W-1002FT
R2,R3
100k, 0402
Venkel
CR0402-16W-1003FT
R4,R5,R6,R7,R8,R13
1k, 0603
Venkel
CR0603-16W-1001FT
R9,R10,R11,R12
120, 0603
Venkel
CR0603-16W-121JT
R14,R15,R20,R21,R22,R23
49.9, 0603
Venkel
CR0603-16W-49R9FT
R16,R17,R18,R19,R24,R25,
0, 0402
Venkel
CR0402-16W-000T
R26,R27,R29,R32
R28
4.99k, 0603
Venkel
CR0603-16W-4991FT
SW1,SW2,SW3
101-0161
Mouser
101-0161
U1
Si5364_revB
U4,U5
74LCX244
Fairchild
74LCX244MTC
U7,U6
74SZ14
Fairchild
NC7SZ14M5X
S i 5 3 6 4 - E V B
8
Preliminary Rev. 0.33
Figure 3. Si5364-EVB Top Silkscreen
Figure 4. Si5364-EVB--Layer 1, Component Side
S i 53 64 -E V B
Preliminary Rev. 0.33
9
Figure 5. Si5364-EVB--Layer 2, High Speed Signals
Figure 6. Si5364-EVB--Layer 3, GND
S i 5 3 6 4 - E V B
10
Preliminary Rev. 0.33
Figure 7. Si5364-EVB--Layer 4, VDD 2.5
Figure 8. Si5364-EVB--Layer 5, GND
S i 53 64 -E V B
Preliminary Rev. 0.33
11
Figure 9. Si5364-EVB--Layer 6, VDD 3.3
Figure 10. Si5364-EVB--Layer 7, GND
S i 5 3 6 4 - E V B
12
Preliminary Rev. 0.33
Figure 11. Si5364-EVB--Layer 8, Bottom
Figure 12. Si5364-EVB Bottom Silkscreen
S i 53 64 -E V B
Preliminary Rev. 0.33
13
Document Revision Change List
Revision 0.28 to Revision 0.33
Updated to reflect Rev. D printed circuit boards.
Evaluation Board Assembly Revision History
Assembly Level
PCB Rev.
Si5364 Rev.
Assembly Notes
C-01
Rev. D
Rev. C
Assemble per BOM rev C-01
S i 5 3 6 4 - E V B
14
Preliminary Rev. 0.33
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