- 1 -
Swindon Silicon Systems Limited
Oct 95
SSSB151
STM1 Clock and Data Receiver
SDH Product Range
High performance Silicon Bipolar process
Differential High Speed Serial Data Input
155.52Mbit/s NRZ or 311.04MBaud CMI serial
data input format
ECL100k compatible 155.52MBit/s serial data
outputs
8 bit TTL compatible 19.44MByte/s parallel data
outputs
155.52MHz and 19.44MHz Clock outputs
Excellent Jitter Transfer Characteristics
Complete on-chip VCO
Twin power supply (-5V & +5V)
Low dissipation
44 pin J-leaded ceramic package
Meets ITU-T Recommendations
STM1 Clock and Data Receiver
FEATURES
The SSSB151 accepts an STM1 serial data stream as either 155.52MBit/s NRZ or 311.04MBaud CMI data format. The
device recovers the clock and data, then outputs the retimed data in both bit serial and byte parallel form, along with
the associated 155.52MHz and 19.44MHz clock signals.
An on-chip Phase Locked Loop and Voltage Controlled Oscillator (VCO) are used to provide a stable on-chip clock
signal. The device uses a sample and hold phase detector to lock the VCO onto the received serial data stream. This
gives the SSSB151 an excellent jitter transfer characteristic. The device includes additional circuits which, in the absence
of a valid serial data stream, switch to a phase-frequency detector to lock the VCO onto an external reference clock.
This holds the VCO close to the required frequency, reduces the time taken to lock onto the serial data stream and
prevents the VCO locking onto harmonics.
FUNCTIONAL OVERVIEW
SSSB151
DATE CODE
RBCLK
GND
VEE
GND
RBCLKB
GND
SRD
A
T
A
SRD
A
T
AB
n/c
GND
DCHKB
The SSSB151 recovers clock and data signals from an STM1 serial data stream. The device accepts the serial data stream
in either 155.52MBit/s NRZ format or 311.04MBaud CMI format.
GND
SDIB
LSCLKB
VEE
EN
LOCKB
n/c
GND
VCC
SDI
LSCLK
RDATA(4)
RDATA(6)
RDATA(5)
VCC
GND
RDATA(3)
RDATA(2)
RDATA(1)
RDATA(0)
RSCLK
RDATA(7)
TESTB
LTXD
LOOPBACK
RCVDA
RCVDAB
VEE
FLTR
GND
BGFLTR
VEE
CMI
SSSB151
STM1 Clock and Data Receiver
- 2 -
Swindon Silicon Systems Limited
Oct 95
Block Diagram
MUX
CMI
SERIAL TO
PARALLEL
EN
LOOPBACK
LTXD
PD1
VCO
RCVDA
LSCLK
SD1
DCHKB
RBCLK
RDATA
SRDATA
RSCLK
PD2
FLTR
FREQUENCY
COUNTER
MODE
SELECT
DATA
RETIMING
MUX
~
DATA
CHECK
LOCKB
~
8
.
.
SSSB151
STM1 Clock and Data Receiver
- 3 -
Swindon Silicon Systems Limited
Oct 95
SSSB151 FUNCTIONAL DESCRIPTION
Data Path
The SSSB151 accepts STM1 frames as a serial data stream through the differential RCVDA Received Data inputs.
The received data passes to a Multiplexer which allows the selection of an alternative data input path through the
ECL compatible LTXD input for Loopback operation. The output from the Multiplexer passes to the Data Retiming
circuit, the on-chip Phase Locked Loop (PLL) for clock recovery, and the Data Check circuit.
The Data Retiming circuit uses the recovered clock to produce a low jitter serial data stream. The Data Retiming
circuit also allows code conversion of 311.04MBaud CMI received data to 155.52MBit/s NRZ format. Code
conversion is controlled by the TTL compatible CMI input. This input must be high if the received data is in CMI
format and must be low if the received data is in NRZ format.
The Serial Retimed Data and the associated 155.52MHz Recovered Bit Clock are output from the device on the
differential ECL100k outputs SRDATA and RBCLK.
The retimed data is converted from bit serial to byte parallel form. Byte parallel data is not aligned to STM1 frame
boundaries. The parallel Received Data is output from the device along with the associated 19.44MHz Receive
Symbol Clock on the TTL compatible RDATA(7:0) and RSCLK outputs. The RDATA and RSCLK outputs are
three-state outputs which will be in the high impedance state if the Enable input (EN) is low.
Clock Recovery
The SSSB151 uses an on-chip Phase Locked Loop (PLL) and Voltage Controlled Oscillator (VCO) to generate a
stable clock signal that is phase locked to the received serial data stream. Phase locking is a two-stage process. A
phase-frequency detector (PD2) is used to lock the VCO onto an external reference clock to aid frequency capture,
then a sample and hold phase detector (PD1) is used to achieve an accurate low jitter phase lock onto the received
serial data stream. The PLL frequency compensation components which set the loop response times are connected
to the FLTR pin. These components are shown on the SSSB151 Application Diagram. Switching between phase
detectors is controlled by the Mode Selection circuit.
PD1 is a sample and hold phase detector which compares the on-chip Voltage Controlled Oscillator (VCO) to the
received serial data stream. This allows the VCO to phase lock onto the serial data stream. The design of this phase
detector gives the SSSB151 an excellent jitter transfer characteristic. The Jitter Tolerance Diagram shows that the
SSSB151 comfortably exceeds the ITU recommendations. The SRDATA Output Eye Diagram shows the low level
of jitter generated by the SSSB151. Worst case jitter is specified in the Electrical Characteristics tables later in this
document.
PD2 is a phase-frequency detector which compares the VCO to an external reference clock. The SSSB151 uses PD2
to lock the VCO onto the external reference clock in the absence of a valid serial data stream. This holds the VCO
close to the required centre frequency, reduces the time taken to lock onto the serial data stream, and prevents the
PLL from locking onto harmonics of the required frequency. The external reference clock is a differential signal at
the LSCLK inputs. The external oscillator frequency must be one eighth of the serial data rate, i.e. nominally
19.44MHz for either 155.52MBit/s NRZ data or 311.04MBaud CMI data.
SSSB151
STM1 Clock and Data Receiver
- 4 -
Swindon Silicon Systems Limited
Oct 95
Mode Selection
With a valid received serial data stream, the SSSB151 uses the sample and hold phase detector, PD1, to lock the
VCO onto the serial data stream. In the absence of a valid received serial data stream, the device uses the phase-
frequency detector, PD2, to lock the VCO onto an external reference clock. The serial data stream is assumed to be
invalid if any of the following three conditions apply:
The on-chip frequency counter detects a VCO frequency error
SDI is low (with respect to SDIB)
The on-chip data integrity check circuit reports data errors
If any of these conditions apply, the Mode Selection circuit selects PD2 to lock the VCO onto the external reference
clock. When PD2 is selected, the LOCKB output will be high.
Frequency Counter Check
The Frequency Counter circuit compares the VCO divided by 8 and the external reference clock frequency. A
frequency error greater than 3 parts in 200 forces the SSSB151 to use PD2 to lock the VCO onto the external
reference clock. When the frequency error is reduced to less than 1 part in 200, the SSSB151 will switch to PD1 to
lock the VCO onto the received serial data stream, provided that the SDI input is high and that the data integrity
check circuit is not reporting an error.
Signal Detect Inputs
The Signal Detect Inputs (SDI/SDIB) are a differential input pair. These inputs are designed to be connected to an
external circuit which monitors the inbound STM1 optical signal levels. A low level on SDI (with respect to SDIB)
indicates that the inbound optical signal level is below the signal detect threshold and forces the SSSB151 to use
PD2 to lock the VCO onto the external reference clock. When SDI goes high, the SSSB151 will switch to PD1 to
lock the VCO onto the received serial data stream, provided that the VCO frequency is close to the external
reference frequency and that the data integrity check circuit is not reporting an error.
Data Integrity Checks
The SSSB151 Data Check circuit is controlled by the TTL compatible DCHKB input. A high level on this input
inhibits the Data Check circuit. A low level on this input enables the Data Check circuit. The Data Check circuit
divides the serial data stream into consecutive windows, each window having a length of 32 bits, i.e. 32 cycles of the
155.52MHz clock, or approximately 206ns. The Data Check circuit looks for data errors in each window of the
serial data stream.
The data integrity checking criteria used to define an error depend on whether the device is in CMI or NRZ mode.
When the device is in CMI mode, the criteria used is that a CMI error has occurred if, within a 32 bit window of the
serial data stream, there are four or more consecutive 155.52MHz clock cycles without a change of state of the input
data. When the device is in NRZ mode, it is more difficult to define a data error. The criteria used is that an NRZ
error has occurred if, within a 32 bit window of the serial data stream, there are sixteen or more consecutive
155.52MHz clock cycles without a change of state of the input data.
SSSB151
STM1 Clock and Data Receiver
- 5 -
Swindon Silicon Systems Limited
Oct 95
With the VCO locked onto the received serial data stream and DCHKB low, the serial data stream is continuously
monitored and, if a period of 128 windows of the serial data stream (approximately 26
s) passes with data errors
occurring in every window, then the data stream is considered to be invalid and the SSB151 will switch to PD2 to
lock the VCO onto the external reference clock.
With the VCO locked onto the external reference clock and DCHKB low, the received serial data stream is
continuously monitored and, if a period of 32 windows (approximately 6.6
s) passes no data errors, then the serial
data stream is considered valid and the SSSB151 will switch to PD1 to lock the VCO onto the serial data stream.
This requirement is in addition to the requirements that the SDI input is high and that the VCO frequency is close
to the external reference clock frequency.
Loopback and Test Mode
The LOOPBACK pin controls the multiplexer in the data input path. For normal operation, this pin is held high and
the data path into the device is through the Received Data input (RCVDA). With LOOPBACK held low, then the
data path into the device is through the Loopback Transmit Data input (LTXD).
The TESTB pin is used by Swindon Silicon Systems for test purposes. For normal operation, TESTB must be held
high or left open circuit.
LOOPBACK and TESTB are TTL compatible inputs.
Data Check Operation
Continuous Errors
ERROR
RATE
MODE
PD1
26
s
6.6
s
PD2
PD1
No Errors
SSSB151
STM1 Clock and Data Receiver
- 6 -
Swindon Silicon Systems Limited
Oct 95
Pin Descriptions
ECL Inputs
RCVDA, RCVDAB
Differential data inputs for the STM1 Received Serial Data Stream.
These inputs can be driven differentially or single ended with AC or DC coupling.
Note that for the single ended DC coupled case, an external reference voltage is required.
LSCLK, LSCLKB
Differential clock inputs for the External Reference clock.
These inputs can be driven differentially or single ended with AC or DC coupling.
Note that for the single ended DC coupled case, an external reference voltage is required.
The frequency of the reference clock is one eighth of the data rate, i.e. nominally 19.44MHz.
LTXD
ECL100k data input for Loopback operation.
SDI, SDIB
Differential control inputs for the Mode Selection circuit.
These inputs can be driven differentially or single ended with DC coupling.
Note that for the single ended DC coupled case, an external reference voltage is required.
AC coupling is not appropriate because the SDI switching rate may be very low.
SDI is high (with respect to SDIB) to allow the VCO to lock onto the received serial data stream.
SDI is low (with respect to SDIB) to force the VCO to lock onto the external reference clock.
ECL Outputs
SRDATA, SRDATAB
Differential ECL100k data outputs for the Retimed Serial Data in NRZ format.
RBCLK, RBCLKB
Differential ECL100k 155.52MHz Clock outputs.
RBCLK and RBCLKB are the clock outputs associated with the SRDATA outputs.
The SRDATA outputs change following the rising edge on RBCLK.
Analogue Pins
FLTR
FLTR is an analogue connection for the PLL Filter components. Recommended values are shown on the
application diagram.
BGFLTR
BGFLTR is the decoupling connection for an internal reference voltage.
SSSB151
STM1 Clock and Data Receiver
- 7 -
Swindon Silicon Systems Limited
Oct 95
TTL Inputs
CMI
TTL control input for received data format selection.
CMI is high if the received data is in CMI format.
CMI is low if the received data is in NRZ format.
DCHKB
TTL control input for Data Check enable.
DCHKB is high to inhibit the data check circuit.
DCHKB is low to enable the data check circuit.
EN
TTL control input to enable the RDATA and RSCLK output buffers.
EN is high to enable the output buffers.
EN is low to force the buffers to be high impedance.
LOOPBACK
TTL control input for Loopback operation.
LOOPBACK is high for normal operation.
LOOPBACK is low to select the LTXD data input for loopback operation.
TESTB
TTL control input for test operation.
TESTB is high or open circuit for normal operation.
TTL Outputs
RDATA(7:0)
TTL data outputs for the byte parallel Received Data output.
RDATA is an 8 bit port.
These outputs are three-state outputs controlled from the EN pin.
RSCLK
TTL 19.44MHz Clock output.
RSCLK is the clock output associated with the RDATA data outputs.
The RDATA outputs change following the falling edge on RSCLK.
RSCLK output is a three-state output controlled from the EN pin.
LOCKB
TTL open collector output from the PLL control logic.
LOCKB is high when the device is using PD2 to lock onto the external reference oscillator.
LOCKB is low when the device is using PD1 to lock onto the received serial data stream.
SSSB151
STM1 Clock and Data Receiver
- 8 -
Swindon Silicon Systems Limited
Oct 95
V
CC
OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Units
Conditions
Operating Supply Voltage
70
V
TT
V
ECL Terminating Voltage
4.5
5.5
Typ
No forced air cooling
These operating conditions apply to all subsequent characteristics, unless otherwise stated
GENERAL
Parameter
Symbol
Min
Max
Units
Conditions
Typ
V
IH
ECL INPUTS
Parameter
Symbol
Min
Max
Units
Conditions
Input High Level
-1.49
V
IL
V
Input Low Level
V
Input High Current
I
IH
A
-1.15
-0.87
Typ
-1.83
V
IN
= V
IH(Max)
150
LTXD
C
(ECL100k inputs with 50k
pulldown resistors
)
Input Low Current
I
IL
A
V
IN
= -2V
V
EE
Operating Supply Voltage
V
-5.5
-4.75
25
V
CC
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
Conditions
Supply Voltage
+0.5
V
EE
V
Supply Voltage
V
Input Voltage (TTL)
V
IT
V
-0.5
Output Current (TTL)
+6.0
Typ
-6.0
Gnd = 0v
I
OUT
mA
Output Current (ECL)
Junction Temperature
T
j
Useful life may be impaired if the device is operated outside these limits
Input Voltage (ECL)
V
IE
Storage Temperature
T
stg
ELECTRICAL CHARACTERISTICS
Gnd = 0v
-0.5
V
CC
V
EE
0.5
V
40
I
OUT
mA
40
+150
C
+150
C
All pins are protected against ESD, however, the normal ESD precautions for high speed devices must be observed at all times.
T
a
Ambient Temperature
0
-2.0
5.0
-5.0
V
I
EE
Supply Current
I
CC
Supply Current
mA
mA
V
EE
= -5.00V
V
CC
= +5.00V
200
40
-55
SSSB151
STM1 Clock and Data Receiver
- 9 -
Swindon Silicon Systems Limited
Oct 95
F
NRZ
ECL INPUTS
Parameter
Symbol
Min
Max
Units
Conditions
Data Rate
F
CMI
MBit/s
Data Rate
MBaud
Single Ended DC Coupled Inputs (*1)
140
P-P Amplitude
Typ
311.04
V
IP
-100ppm
Input High Level
-0.87
V
RCVDA/RCVDAB, SDI/SDIB and LSCLK/LSCLKB
CMI = low
155.52
V
IH
-1.15
Input Low Level
V
IL
-1.83
-1.49
V
Differential DC Coupled Inputs
Input High Level
-0.87
V
V
IH
Input Low Level
V
IL
-1.83
V
Input Differential
V
DIFF
400
mV
900
*1
If the SDI/SDIB inputs are unused, then for correct device operation SDI may be tied to GND, and SDIB may be tied to
V
TT
or left DC open-circuit and decoupled through a 10nF capacitor to GND.
Clock Frequency
(LSCLK/LSCLKB)
MHz
Single Ended AC Coupled Inputs (Not SDI/SDIB
400
900
mV
P-P Amplitude
V
IP
Differential AC Coupled Inputs
600
900
mV
19.44
+100ppm
INPUT
BIAS
GENERATOR
V
EE
0V
-5V
R
T
DEVICE
Single Ended DC Coupled (ECL100k) Input
V
TT
R
T
1k
1k
INPUT
BIAS
GENERATOR
0V
DEVICE
INPUT
BIAS
GENERATOR
R
T
DEVICE
Differential DC Coupled Input
INPUT
BIAS
GENERATOR
DEVICE
(Differential ECL compatible inputs)
165
CMI = high
F
CLK
V
REF
= - 1.32V
V
REF
= - 1.32V
Single Ended AC Coupled Input
Differential AC Coupled Input
V
REF
GND
GND
R
T
R
T
V
TT
1k
1k
V
EE
-5V
GND
R
T
0V
V
TT
1k
1k
V
EE
-5V
GND
0V
R
T
R
T
V
TT
V
EE
-5V
1k
1k
SSSB151
STM1 Clock and Data Receiver
- 10 -
Swindon Silicon Systems Limited
Oct 95
Serial Data Output Timing Diagram
RBCLK
RBCLKB
t
sdo
VALID
VALID
SRDATA
6.43ns
t
sdo
t
sdo
Parallel Data Output Timing Diagram
t
pdo
VALID
VALID
RDATA
51.44ns
t
pdo
t
pdo
RSCLK
SSSB151
STM1 Clock and Data Receiver
- 11 -
Swindon Silicon Systems Limited
Oct 95
V
IH
Parameter
Symbol
Min
Max
Units
Conditions
Input High Level
0.8
V
IL
A
Input Low Level
V
Typ
2.0
I
IH
-660
I
IL
TTL INPUTS
CMI, DCHKB, EN, LOOPBACK and TESTB
A
Input High Current
Input Low Current
V
(TTL inputs with 11k
pullup resistors to V
CC
)
V
IH
= 2.4V
V
IL
= 0.4V
-140
V
OH
TTL OUTPUTS
Parameter
Symbol
Min
Max
Units
Conditions
Output High Level
V
OL
V
Output Low Level
V
2.4
Typ
Fall Time
0.4
ns
RDATA(7:0) and RSCLK
I
OH
= -0.4 mA
6
t
f
Clock to Data Delay
t
pdo
+6.0
ns
Rise Time
t
r
ns
I
OL
= 4 mA
20% - 80%
20% - 80%
6
V
OH
Parameter
Symbol
Min
Max
Units
Conditions
Output High Level
-1.605
V
OL
V
Output Low Level
V
-1.0
Typ
-1.83
t
r
1.5
t
f
ns
1.5
20% - 80%
0.6
ECL OUTPUTS
SRDATA, SRDATAB and RBCLK, RBCLKB
(ECL 100k outputs)
+1.0
t
sdo
Fall Time
Clock to data delay
40
ns
Jitter
ps RMS
-0.87
EN input low
20% - 80%
Rise Time
ns
ELECTRICAL CHARACTERISTICS (cont)
These characteristics apply when the outputs are terminated by a 50
1% resistor to -2 V (V
TT
)
-1.035
0.6
These characteristics apply with a load of 15pF on all outputs
-6.0
I
OH
Parameter
Symbol
Min
Max
Units
Conditions
0.4
V
OL
V
Typ
TTL OPEN COLLECTOR OUTPUT
LOCKB
Output High Current
Output Low Level
A
(Open collector output with 25k
pulldown resistor to ground)
V
OH
= + 2.4V
I
OL
= 4 mA
125
SSSB151
STM1 Clock and Data Receiver
- 12 -
Swindon Silicon Systems Limited
Oct 95
Jitter Tolerance Diagram
0.1
1.0
10
100
3.3k
10k
33k
100k
330k
1M
Jitter Frequency (Hz)
Jitter (UI pk-pk)
ITU-T G.958 Specification
STM1 Type A Mask
SSSB151 Characteristic
SRDATA Output Eye Diagram
Jitter (rms) 21.4 ps
1 ns/div
SRDATA Output Eye Diagram
SSSB151
STM1 Clock and Data Receiver
- 13 -
Swindon Silicon Systems Limited
Oct 95
6
1
40
18
28
39
29
7
17
SSSB151
(Top View)
SSB151 Application Diagram
10n
LOCKB
EN
GND
RSCLK
RDATA7
V
CC
SRDATA
RBCLK
V
CC
100n
56R
V
EE
LOOPBACK
CMI
DCHKB
LTXD
RCVDA
82R
SDI
SDIB
GND
V
CC
19.44MHz
TTL
Oscillator
330R
75R
GND
GND
V
EE
4 off
50R
V
TT
GND
1 : 1 Fibre Channel Transformer
Pulse Engineering PE-65507
All unmarked Capacitors are 10nF ceramic
All lines to the RCVDA, RBCLK and SRDATA connections should be transmission lines at the operating
frequency of 155.52MHz.
Layout should be designed to minimise the noise induced to the PLL feedback components at pin 3.
RDATA0
10n
10k
SSSB151
STM1 Clock and Data Receiver
- 14 -
Swindon Silicon Systems Limited
Oct 95
PIN ASSIGNMENT TABLE
Pin No.
Name
Description
1
Test Mode Enable
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
TESTB
VEE
FLTR
GND
VEE
LSCLK
LOCKB
VCC
GND
GND
GND
EN
RBCLK
Analogue Ground
Signal Detect In
Inverse Reference Clock Input
PLL Mode Signal
Positive Supply (+5V)
Ground
Analogue Negative Supply (-5V)
PLL Filter
BGFLTR
Analogue Negative Supply (-5V)
SDI
SDIB
LSCLKB
Reference Clock Input
VEE
Negative Supply (-5V)
Ground
Output Buffer Enable
n/c
No connection
Ground
RSCLK
19.44MHz Clock Output
RDATA(0)
Parallel Data Output
VCC
Positive Supply (+5V)
GND
n/c
SRDATAB
Ground
No Connection
Inverse Serial Data Output
GND
Ground
Levels
TTL
TTL 3-state
ECL100k
Type
Input
Output
Output
38
39
40
41
42
DCHKB
Data Check Enable
CMI
CMI Mode Enable
LOOPBACK
LTXD
Test Data Input
TTL
TTL
Input
Input
ECL100k
Input
ECL100k
Input
ECL100k
Input
Inverse Signal Detect In
ECL100k
Input
ECL100k
Input
TTL
Input
TTL
TTL 3-state
Output
RDATA(1)
Parallel Data Output
TTL 3-state
Output
RDATA(2)
Parallel Data Output
TTL 3-state
Output
RDATA(3)
Parallel Data Output
TTL 3-state
Output
RDATA(4)
Parallel Data Output
TTL 3-state
Output
RDATA(5)
Parallel Data Output
TTL 3-state
Output
RDATA(6)
Parallel Data Output
TTL 3-state
Output
RDATA(7)
Parallel Data Output
TTL 3-state
Output
Output
SRDATA
Serial Data Output
ECL100k
Output
GND
Ground
155.52MHz Clock Output
ECL100k
Output
RBCLKB
Inverse 155.52MHz Clock Output
ECL100k
Output
VEE
Negative Supply (-5V)
GND
Ground
Test Mode Enable
TTL
Input
43
RCVDA
STM1 Input
ECL100k
Input
44
RCVDAB
Inverse STM1 Input
ECL100k
Input
To ensure correct operation:
V
EE
pins (2, 6, 11 and 37) and V
CC
pins (17 and 25) must be decoupled to ground through high frequency
ceramic capacitors close to the device pins.
The PLL filter components must be connected between the FLTR pin and the adjacent V
EE
pin (pin 2).
The internal reference decoupling capacitor must be connected between the BGFLTR pin and the adjacent
V
EE
pin (pin 6).
Reference Decoupling
SSSB151
STM1 Clock and Data Receiver
- 15 -
Swindon Silicon Systems Limited
Oct 95
SSSB151
DATE CODE
Pin 1
40
6
39
29
28
18
17
7
0.500 SQ
0.650 SQ
0.690
0.010
SQ
0.630
0.020
SQ
0.050 typ
0.030 typ
0.017 typ
0.009
+0.002
-0.001
0.037
0.010
0.040
.010
0.020
.010
PACKAGE DIMENSIONS
44 pin .050 inch pitch
J leaded ceramic chip carrier
Cavity up
Leads are Kovar or Alloy 42
All exposed metal is Gold plated, 60 micro inch minimum
over Nickel plated, 100 micro inch minimum
Lid is isolated from all leads
0.115
0.020
- 16 -
Swindon Silicon Systems Limited Oct 95
INTERNATIONAL REPRESENTATIVES / DISTRIBUTORS
HEAD OFFICE
Swindon Silicon Systems
Radnor Street
Swindon
Wiltshire
SN1 3PR
Tel : 01793 614039
Fax : 01793 616215
EUROPE
FRANCE :
Rep Design
5 Rue Carle Vernet
92310 Sevres
Tel : 33-1-4623-7990
Fax : 33-1-4623-7993
ITALY :
Special-IND
Piazza Spotorno, 3
20159 Milan
Tel : 39-2-66805177
Fax : 39-2-66800493
FAR EAST
ISRAEL :
IES Ltd
32 Ben-Gurion St
Ramat-Gan 52573
Tel : 972-3-753 0700
Fax : 972-3-753 0701
JAPAN :
Nissho Electronics Corp
3-1, Tsukiji 7-chome
Chuo-ku
Tokyo 104
Tel : 81-3-3544-8495
Fax : 81-3-3544-8280
SOUTH KOREA :
Advance Technology Ltd
Suite 312, Jay 11 B/D
44-35 Yoido-dong
Young Deung Po - Ku
Seoul
Tel : 82-2-786-5387
Fax : 82-2-786-5389
This publication is issued to provide outline information only and (unless specifically agreed to the contrary by the company in writing)
is not to be reproduced or to form part of any order or contract or to be regarded as a representation relating to the products or services
concerned. Any applications of product shown in this publication are for illustration purposes only. We reserve the right to alter without
notice the specification, design price or condition of supply of the product.
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