5/01

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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FEATURES:

Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

Single Voltage Read and Write Operations

5.0V-only for SST29SF512/010/020/040
2.7-3.6V for SST29VF512/010/020/040

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 10 mA (typical)
Standby Current:

30 µA (typical) for SST29SF512/010/020/040

1 µA (typical) for SST29VF512/010/020/040

Sector-Erase Capability

Uniform 128 Byte sectors

Fast Read Access Time:

55 ns
70 ns

Latched Address and Data

Fast Erase and Byte-Program:

Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:

1 second

(typical) for SST29SF/VF512

2 seconds (typical) for SST29SF/VF010
4 seconds (typical) for SST29SF/VF020
8 seconds (typical) for SST29SF/VF040

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling

TTL I/O Compatibility for SST29SFxxx

CMOS I/O Compatibility for SST29VFxxx

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP

PRODUCT DESCRIPTION

The SST29SF512/010/020/040 and SST29VF512/010/
020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS
Small-Sector Flash (SSF) manufactured with SST's propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST29SFxxx devices write
(Program or Erase) with a 4.5-5.5V power supply. The
SST29VFxxx devices write (Program or Erase) with a 2.7-
3.6V power supply. These devices conform to JEDEC stan-
dard pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST29SFxxx and SST29VFxxx devices provide a maxi-
mum Byte-Program time of 20 µsec. To protect against
inadvertent write, they have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of at least
10,000 cycles. Data retention is rated at greater than 100
years.

The SST29SFxxx and SST29VFxxx devices are suited for
applications that require convenient and economical updat-
ing of program, configuration, or data memory. For all sys-
tem applications, they significantly improve performance

and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. They also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.

To meet high density, surface mount requirements, the
SST29SFxxx and SST29VFxxx devices are offered in 32-
pin PLCC and 32-pin TSOP packages. A 600 mil, 32-pin
PDIP is also offered for SST29SFxxx devices. See Figures
1, 2, and 3 for pinouts.

SST29SF/VF512 / 010 / 020 / 0405.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) Byte-Program, Small Erase Sector flash memories

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

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505

Device Operation

Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST29SFxxx and SST29VFxxx
devices are controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is
used for device selection. When CE# is high, the chip is
deselected and only standby power is consumed. OE# is
the output control and is used to gate data from the output
pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing dia-
gram for further details (Figure 4).

Byte-Program Operation

The SST29SFxxx and SST29VFxxx devices are pro-
grammed on a byte-by-byte basis. The Program operation
consists of three steps. The first step is the three-byte-load
sequence for Software Data Protection. The second step is
to load byte address and byte data. During the Byte-Pro-
gram operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed, within 20 µs.
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation
will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The SST29SFxxx and
SST29VFxxx offer Sector-Erase mode. The sector archi-
tecture is based on uniform sector size of 128 Bytes. The
Sector-Erase operation is initiated by executing a six-byte-
command sequence with Sector-Erase command (20H)
and sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (20H) is latched on the rising

edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle
Bit methods. See Figure 9 for timing waveforms. Any com-
mands issued during the Sector-Erase operation are
ignored.

Chip-Erase Operation

The SST29SFxxx and SST29VFxxx devices provide a
Chip-Erase operation, which allows the user to erase the
entire memory array to the "1s" state. This is useful when
the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 19 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.

Write Operation Status Detection

The SST29SFxxx and SST29VFxxx devices provide two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
write cycle time. The software detection includes two sta-
tus bits: Data# Polling (DQ

) and Toggle Bit (DQ

). The

End-of-Write detection mode is enabled after the rising
edge of WE# which initiates the internal Program or
Erase operation.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

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505

Data# Polling (DQ

)

When the SST29SFxxx and SST29VFxxx devices are in
the internal Program operation, any attempt to read DQ

will produce the complement of the true data. Once the
Program operation is completed, DQ

will produce true

data. The device is then ready for the next operation. Dur-
ing internal Erase operation, any attempt to read DQ

will

produce a `0'. Once the internal Erase operation is com-
pleted, DQ

will produce a `1'. The Data# Polling is valid

after the rising edge of fourth WE# (or CE#) pulse for Pro-
gram operation. For Sector- or Chip-Erase, the Data# Poll-
ing is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 7 for Data# Polling timing diagram and
Figure 17 for a flowchart.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-
gram and Figure 17 for a flowchart.

Data Protection

The SST29SFxxx and SST29VFxxx devices provide both
hardware and software features to protect nonvolatile data
from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 2.5V for SST29SFxxx. The

Write operation is inhibited when V

is less than 1.5V. for

SST29VFxxx.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29SFxxx and SST29VFxxx provide the JEDEC
approved Software Data Protection scheme for all data
alteration operation, i.e., Program and Erase. Any Program
operation requires the inclusion of a series of three byte
sequence. The three byte-load sequence is used to initiate

the Program operation, providing optimal protection from
inadvertent write operations, e.g., during the system power-
up or power-down. Any Erase operation requires the inclu-
sion of six byte load sequence. These devices are shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode, within T

Product Identification

The Product Identification mode identifies the devices as
SST29SF512, SST29SF010, SST29SF020, SST29SF040
and SST29VF512, SST29VF010, SST29VF020,
SST29VF040 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry and Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 18 for a flowchart.

TABLE

1: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

BFH

Device ID

SST29SF512

0001H

20H

SST29VF512

0001H

21H

SST29SF010

0001H

22H

SST29VF010

0001H

23H

SST29SF020

0001H

24H

SST29VF020

0001H

25H

SST29SF040

0001H

13H

SST29VF040

0001H

14H

T1.1 505

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 1: P

SSIGNMENTS

FOR

32-

PIN

PLCC

Y-Decoder

I/O Buffers and Data Latches

505 ILL B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory
Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

UNCTIONAL

LOCK

IAGRAM

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

WE#

A12

A15

A16

WE#

A12

A15

A16

WE#

A17

A12

A15

A16

A18

WE#

A17

32-pin PLCC

Top View

505 ILL F02a.3

14 15 16 17 18 19 20

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

SST29SF/VF512

SST29SF/VF010

SST29SF/VF020

SST29SF/VF040

SST29SF/VF010 SST29SF/VF020 SST29SF/VF040

SST29SF/VF512

SST29SF/VF010

SST29SF/VF020

SST29SF/VF040

SST29SF/VF010

SST29SF/VF020

SST29SF/VF040

SST29SF/VF512

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 2: P

SSIGNMENTS

FOR

32-

PIN

TSOP (8

)

FIGURE 3: P

SSIGNMENTS

FOR

32-

PIN

PDIP

A11

A9
A8

A13
A14

WE#

VDD

NC
NC

A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A18
A16
A15
A12

A7
A6
A5
A4

SST29SF/VF512

SST29SF/VF010

SST29SF/VF020

SST29SF/VF040

SST29SF/VF010 SST29SF/VF020 SST29SF/VF040

SST29SF/VF512

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

505 ILL F01.2

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

505 ILL F02b.4

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

SST29SF512

SST29SF010

SST29SF020

SST29SF040

SST29SF010 SST29SF020 SST29SF040

SST29SF512

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

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505

TABLE

2: P

ESCRIPTION

Symbol

Pin Name

Functions

-A

Address Inputs

To provide memory addresses. During Sector-Erase A

-A

address lines will select the

sector.

-DQ

Data Input/output

To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers.

WE#

Write Enable

To control the Write operations.

Power Supply

To provide power supply voltage:

4.5-5.5V for SST29SF512/010/020/040

2.7-3.6V for SST29VF512/010/020/040

Ground

No Connection

Pin not connected internally

T2.3 505

1. A

= Most significant address

= A

for SST29SF/VF512, A

for SST29SF/VF010, A

for SST29SF/VF020, and A

for SST29SF/VF040

TABLE

3: O

PERATION

ODES

ELECTION

Mode

CE#

OE#

WE#

Address

Read

OUT

Program

Erase

1. X can be V

or V

, but no other value.

Sector address,
XXH for Chip-Erase

Standby

High Z

Write Inhibit

High Z/ D

OUT

High Z/ D

OUT

Product Identification

Software Mode

See Table 4

T3.4 505

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

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505

TABLE

4: S

OFTWARE

OMMAND

EQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Byte-Program

555H

AAH

2AAH

55H

555H

A0H

Data

Sector-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

20H

Chip-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Software ID Entry

4,5

555H

AAH

2AAH

55H

555H

90H

Software ID Exit

XXH

F0H

Software ID Exit

555H

AAH

2AAH

55H

555H

F0H

T4.4 505

1. Address format A

-A

(Hex),

Address A

can be V

or V

, but no other value, for the Command sequence for SST29SF/VF512.

Addresses A

- A

can be V

or V

, but no other value, for the Command sequence for SST29SF/VF010.

Addresses A

- A

can be V

or V

, but no other value, for the Command sequence for SST29SF/VF020.

Addresses A

- A

can be V

or V

, but no other value, for the Command sequence for SST29SF/VF040.

2. BA = Program Byte address
3. SA

for Sector-Erase; uses A

-A

address lines for SST29SF/VFxxx

= Most significant address

= A

for SST29SF/VF512, A

for SST29SF/VF010, A

for SST29SF/VF020, and A

for SST29SF/VF040

4. The device does not remain in Software Product ID Mode if powered down.
5. With A

-A

=0;

SST Manufacturer's ID= BFH, is read with A

= 0,

SST29SF512 Device ID = 20H, is read with A

= 1

SST29SF512 Device ID = 21H, is read with A

= 1

SST29SF010 Device ID = 22H, is read with A

= 1

SST29VF010 Device ID = 23H, is read with A

= 1

SST29SF020 Device ID = 24H, is read with A

= 1

SST29SF020 Device ID = 25H, is read with A

= 1

SST29SF040 Device ID = 13H, is read with A

= 1

SST29VF040 Device ID = 14H, is read with A

= 1

6. Both Software ID Exit operations are equivalent

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V

+ 1.0V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Output Short Circuit Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

PERATING

ANGE

FOR

SST29SF512/010/020/040

Range

Ambient Temp

Commercial

0°C to +70°C

5V±10%

Industrial

-40°C to +85°C

5V±10%

PERATING

ANGE

FOR

SST29VF512/010/020/040

Range

Ambient Temp

Commercial

0°C to +70°C

2.7-3.6V

Industrial

-40°C to +85°C

2.7-3.6V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

30 pF for 55 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

= 100 pF for 70 ns

See Figures 13, 14, and 15

TABLE

5: DC O

PERATING

HARACTERISTICS

= 5.0V±10%

FOR

SST29SF

XXX

Symbol

Parameter

Limits

Test Conditions

Min

Max

Units

Power Supply Current

Address input=V

, at f=1/T

Min

Max

Read

CE#=OE#=V

, WE#=V

, all I/Os open

Write

CE#=WE#=V

, OE#=V

SB1

Standby V

Current (TTL input)

CE#=V

, V

Max

SB2

Standby V

Current (CMOS input)

100

µA

CE#=V

IHC

, V

Max

Input Leakage Current

µA

=GND to V

, V

Max

Output Leakage Current

µA

OUT

=GND to V

, V

Max

Input Low Voltage

0.8

Min

Input High Voltage

2.0

Max

IHC

Input High Voltage (CMOS)

-0.3

Max

Output Low Voltage

0.4

=2.1 µA, V

Min

Output High Voltage

2.4

=-400 µA, V

Min

T5.3 505

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

TABLE

6: DC O

PERATING

HARACTERISTICS

= 2.7-3.6V

FOR

SST29VF

XXX

Symbol

Parameter

Limits

Test Conditions

Min

Max

Units

Power Supply Current

Address input=V

, at f=1/T

Min

Max

Read

CE#=OE#=V

, WE#=V

, all I/Os open

Write

CE#=WE#=V

, OE#=V

Standby V

Current

µA

CE#=V

IHC

, V

Max

Input Leakage Current

µA

=GND to V

, V

Max

Output Leakage Current

µA

OUT

=GND to V

, V

Max

Input Low Voltage

0.8

Min

Input High Voltage

0.7V

Max

IHC

Input High Voltage (CMOS)

-0.3

Max

Output Low Voltage

0.2

=100 µA, V

Min

Output High Voltage

-0.2

=-100 µA, V

Min

T6.5 505

TABLE

7: R

ECOMMENDED

YSTEM

OWER

IMINGS

Symbol

Parameter

Minimum

Units

PU-READ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation

100

µs

PU-WRITE

Power-up to Program/Erase Operation

100

µs

T7.1 505

TABLE

8: C

APACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance

I/O

= 0V

12 pF

Input Capacitance

= 0V

6 pF

T8.1 505

TABLE

9: R

ELIABILITY

HARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

END

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance

10,000

Cycles

JEDEC Standard A117

Data Retention

100

Years

JEDEC Standard A103

LTH

Latch Up

100 + I

JEDEC Standard 78

T9.2 505

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

AC CHARACTERISTICS

TABLE 10: R

EAD

YCLE

IMING

ARAMETERS

= 5V±10%

FOR

SST29SF

XXX

AND

2.7-3.6V

FOR

SST29VF

XXX

Symbol

Parameter

SST29SF/VFxxx-55

SST29SF/VFxxx-70

Units

Min

Max

Min

Max

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

CE# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

T10.5 505

TABLE 11: P

ROGRAM

RASE

YCLE

IMING

ARAMETERS

= 5V±10%V

FOR

SST29SF

XXX

AND

2.7-3.6V

FOR

SST29VF

XXX

Symbol

Parameter

Min

Max

Units

Byte-Program Time

µs

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OES

OE# High Setup Time

OEH

OE# High Hold Time

CE# Pulse Width

WE# Pulse Width

WPH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High

CPH

CE# Pulse Width High

Data Setup Time

Data Hold Time

IDA

Software ID Access and Exit Time

150

Sector-Erase

SCE

Chip-Erase

100

T11.6 505

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 4: R

EAD

YCLE

IMING

IAGRAM

FIGURE 5: WE# C

ONTROLLED

ROGRAM

YCLE

IMING

IAGRAM

505 ILL F03.1

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE#

TCE

TRC

TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ

TOH

TCHZ

HIGH-Z

DATA VALID

TOHZ

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

505 ILL F04.1

ADDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0

SW1

SW2

555

2AA

555

ADDR

DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 6: CE# C

ONTROLLED

ROGRAM

YCLE

IMING

IAGRAM

FIGURE 7: D

ATA

# P

OLLING

IMING

IAGRAM

505 ILL F05.1

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0

SW1

SW2

555

2AA

555

ADDR

DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

505 ILL F06.1

ADDRESS AMS-0

DQ7

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 8: T

OGGLE

IMING

IAGRAM

FIGURE 9: WE# C

ONTROLLED

ECTOR

-E

RASE

IMING

IAGRAM

505 ILL F07.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most Significant Address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

505 ILL F10.2

ADDRESS AMS-0

DQ7-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

555

2AA

555

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 11)
AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 10: WE# C

ONTROLLED

HIP

-E

RASE

IMING

IAGRAM

FIGURE 11: S

OFTWARE

ID E

NTRY

AND

EAD

505 ILL F17.2

ADDRESS AMS-0

DQ7-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

555

2AA

555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 11)

Note:

AMS = Most Significant Address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040

505 ILL F08.2

ADDRESS A14-0

DQ7-0

WE#

Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040

21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040

SW1

SW0

SW2

Device ID

555

2AA

555

0000

0001

OE#

CE#

Three-Byte Sequence for

Software ID Entry

TWP

TWPH

TAA

TIDA

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

FIGURE 13: AC I

NPUT

UTPUT

EFERENCE

AVEFORMS

FOR

SST29SF

XXX

FIGURE 14: AC I

NPUT

UTPUT

EFERENCE

AVEFORMS

FOR

SST29VF

XXX

FIGURE 15: T

EST

OAD

XAMPLES

505 ILL F11.0

REFERENCE POINTS

OUTPUT

INPUT

VIT

VIHT

VILT

VOT

AC test inputs are driven at V

IHT

(3.0 V) for a logic "1" and V

ILT

(0 V) for a logic "0". Measurement reference points for

inputs and outputs are V

(1.5 V

) and V

(1.5 V

). Input rise and fall times (10%

90%) are <10 ns.

Note: V

- V

INPUT

Test

- V

OUTPUT

Test

IHT

- V

INPUT

HIGH Test

ILT

- V

INPUT

LOW Test

505 ILL F11.0

REFERENCE POINTS

OUTPUT

INPUT

VIT

VIHT

VILT

VOT

AC test inputs are driven at V

IHT

(0.9 V

) for a logic "1" and V

ILT

(0.1 V

) for a logic "0". Measurement reference points

for inputs and outputs are V

(0.5 V

) and V

(0.5 V

). Input rise and fall times (10%

90%) are <5 ns.

Note: V

- V

INPUT

Test

- V

OUTPUT

Test

IHT

- V

INPUT

HIGH Test

ILT

- V

INPUT

LOW Test

505 ILL F12b.2

TO TESTER

TO DUT

TEST LOAD EXAMPLE FOR SST29VF512/010/020/040

505 ILL F12.2

TEST LOAD EXAMPLE FOR SST29SF512/010/020/040

TO TESTER

TO DUT

RL LOW

RL HIGH

VDD

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

SST29SF512 Valid combinations

SST29SF512-55-4C-NH

SST29SF512-55-4C-WH

SST29SF512-70-4C-NH

SST29SF512-70-4C-WH

SST29SF512-70-4C-PH

SST29SF512-55-4I-NH

SST29SF512-55-4I-WH

SST29SF512-70-4I-NH

SST29SF512-70-4I-WH

SST29VF512 Valid combinations

SST29VF512-55-4C-NH

SST29VF512-55-4C-WH

SST29VF512-70-4C-NH

SST29VF512-70-4C-WH

SST29VF512-55-4I-NH

SST29VF512-55-4I-WH

SST29VF512-70-4I-NH

SST29VF512-70-4I-WH

SST29SF010 Valid combinations

SST29SF010-55-4C-NH

SST29SF010-55-4C-WH

SST29SF010-70-4C-NH

SST29SF010-70-4C-WH

SST29SF010-70-4C-PH

SST29SF010-55-4I-NH

SST29SF010-55-4I-WH

SST29SF010-70-4I-NH

SST29SF010-70-4I-WH

SST29VF010 Valid combinations

SST29VF010-55-4C-NH

SST29VF010-55-4C-WH

SST29VF010-70-4C-NH

SST29VF010-70-4C-WH

SST29VF010-55-4I-NH

SST29VF010-55-4I-WH

SST29VF010-70-4I-NH

SST29VF010-70-4I-WH

SST29SF020 Valid combinations

SST29SF020-55-4C-NH

SST29SF020-55-4C-WH

SST29SF020-70-4C-NH

SST29SF020-70-4C-WH

SST29SF020-70-4C-PH

SST29SF020-55-4I-NH

SST29SF020-55-4I-WH

SST29SF020-70-4I-NH

SST29SF020-70-4I-WH

SST29VF020 Valid combinations

SST29VF020-55-4C-NH

SST29VF020-55-4C-WH

SST29VF020-70-4C-NH

SST29VF020-70-4C-WH

SST29VF020-55-4I-NH

SST29VF020-55-4I-WH

SST29VF020-70-4I-NH

SST29VF020-70-4I-WH

SST29SF040 Valid combinations

SST29SF040-55-4C-NH

SST29SF040-55-4C-WH

SST29SF040-70-4C-NH

SST29SF040-70-4C-WH

SST29SF040-70-4C-PH

SST29SF040-55-4I-NH

SST29SF040-55-4I-WH

SST29SF040-70-4I-NH

SST29SF040-70-4I-WH

SST29VF040 Valid combinations

SST29VF040-55-4C-NH

SST29VF040-55-4C-WH

SST29VF040-70-4C-NH

SST29VF040-70-4C-WH

SST29VF040-55-4I-NH

SST29VF040-55-4I-WH

SST29VF040-70-4I-NH

SST29VF040-70-4I-WH

Example:

Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

PACKAGING DIAGRAMS

32-

PIN

LASTIC

EAD

HIP

ARRIER

(PLCC)

SST P

ACKAGE

ODE

: NH

32-

PIN

HIN

MALL

UTLINE

ACKAGE

(TSOP) 8

SST P

ACKAGE

ODE

: WH

.030
.040

.013
.021

.490
.530

.075
.095

.015 Min.

.125
.140

TOP VIEW

SIDE VIEW

BOTTOM VIEW

.026
.032

.400
BSC

32.PLCC.NH-ILL.2

Note:

1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050
BSC.

.026
.032

.023
.029

.447
.453

.042
.048

Optional

Pin #1 Identifier

.547
.553

.585
.595

.485
.495

.020 R.
MAX.

.106
.112

x 30°

32.TSOP-WH-ILL.4

Note:

1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

8.10
7.90

.270
.170

1.05
0.95

.50

BSC

0.15
0.05

12.50
12.30

Pin # 1 Identifier

14.20
13.80

0.70
0.50

Preliminary Specifications

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

S71160-05-000

5/01

505

32-

PIN

LASTIC

UAL

-L

INE

ACKAGE

(PDIP)

SST P

ACKAGE

ODE

: PH

32.pdipPH-ILL.2

Pin #1 Identifier

Base Plane

Seating Plane

Note:

1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (min/max).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.170
.200

7°

4 PLCS.

.600 BSC

.100 BSC

.120
.150

.016
.022

.045
.065

.070
.080

.015
.050

.065
.075

1.645
1.655

.008
.012

0°

15°

.600
.625

.530
.550

Silicon Storage Technology, Inc. · 1171 Sonora Court · Sunnyvale, CA 94086 · Telephone 408-735-9110 · Fax 408-735-9036

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SST29VF010-90-4I-EH

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SST29VF010-90-4I-EH