2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01
392
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
FEATURES:
Monolithic Flash + SRAM ComboMemory
SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM
Single 3.0-3.6V Read and Write Operations
Concurrent Operation
Read from or Write to SRAM while
Erase/Program Flash
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 10 mA (typical) for Flash and
20 mA (typical) for SRAM Read
Standby Current: 10 A (typical)
Flash Sector-Erase Capability
Uniform 4 KByte sectors
Latched Address and Data for Flash
Fast Read Access Times:
SST31LF021
Flash: 70 ns
SRAM: 70 ns
SST31LF021E
Flash: 300 ns
SRAM: 300 ns
Flash Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Bank-Erase Time: 70 ms (typical)
Byte-Program Time: 14 s (typical)
Bank Rewrite Time: 4 seconds (typical)
Flash Automatic Erase and Program Timing
Internal V
PP
Generation
Flash End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST31LF021/021E devices are a 256K x8 CMOS
flash memory bank combined with a 128K x8 or 32K x8
CMOS SRAM memory bank manufactured with SST's
proprietary, high performance SuperFlash technology. Two
pinout standards are available for these devices. The
SST31LF021 conform to JEDEC standard flash pinouts
and the SST31LF021E conforms to standard EPROM
pinouts. The SST31LF021/021E devices write (SRAM or
flash) with a 3.0-3.6V power supply. The monolithic
SST31LF021/021E devices conform to Software Data
Protect (SDP) commands for x8 EEPROMs.
Featuring high performance Byte-Program, the flash
memory bank provides a maximum Byte-Program time of
20 sec. The entire flash memory bank can be erased and
programmed byte-by-byte in typically 4 seconds, when
using interface features such as Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST31LF021/
021E devices have on-chip hardware and Software Data
Protection schemes. Designed, manufactured, and tested
for a wide spectrum of applications, the SST31LF021/
021E devices are offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.
The SST31LF021/021E operate as two independent mem-
ory banks with respective bank enable signals. The SRAM
and flash memory banks are superimposed in the same
memory address space. Both memory banks share com-
mon address lines, data lines, WE# and OE#. The memory
bank selection is done by memory bank enable signals.
The SRAM bank enable signal, BES# selects the SRAM
bank and the flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST31LF021/021E provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Byte-Program concurrently. All flash
memory Erase and Program operations will automatically
latch the input address and data signals and complete the
operation in background without further input stimulus
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories
2
Data Sheet
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01 392
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST31LF021/021E devices are suited for applications
that use both nonvolatile flash memory and volatile SRAM
memory to store code or data. For all system applications,
the SST31LF021/021E devices significantly improve per-
formance and reliability, while lowering power consumption,
when compared with multiple chip solutions. The
SST31LF021/021E inherently use less energy during
Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter Erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. The monolithic ComboMemory elimi-
nates redundant functions when using two separate mem-
ories of similar architecture; therefore, reducing the total
power consumption.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
The SST31LF021/021E devices also improve flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate
devices. To meet high density, surface mount requirements,
the SST31LF021/021E devices are offered in 32-lead
TSOP packages. See Figure 1 for the pinouts.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. Bus
contention is eliminated as the monolithic device will not
recognize both bank enables as being simultaneously
active. If both bank enables are asserted (i.e., BEF# and
BES# are both low), the BEF# will dominate while the
BES# is ignored and the appropriate operation will be exe-
cuted in the flash memory bank. SST does not recommend
that both bank enables be simultaneously asserted. All
other address, data, and control lines are shared; which
minimizes power consumption and area. The device goes
into standby when both bank enables are raised to V
IHC.
SRAM Operation
With BES# low and BEF# high, the SST31LF021/021E
operate as a 128K x8 or 32K x8 CMOS SRAM, with fully
static operation requiring no external clocks or timing
strobes. The SRAM is mapped into the first 128 KByte
address space of the device. Read and Write cycle times
are equal.
SRAM Read
The SRAM Read operation of the SST31LF021/021E are
controlled by OE# and BES#, both have to be low with
WE# high, for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. When BES# and
BEF# are high, both memory banks are deselected. OE#
is the output control and is used to gate data from the out-
put pins. The data bus is in high impedance state when
OE# is high. See Figure 2 for the Read cycle timing dia-
gram.
SRAM Write
The SRAM Write operation of the SST31LF021/021E are
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. BES# is used for SRAM bank
selection. During the Byte-Write operation, the addresses
and data are referenced to the rising edge of either BES#
or WE#, whichever occurs first. The Write time is measured
from the last falling edge to the first rising edge of BES# and
WE#. See Figure 3 for the Write cycle timing diagram.
Flash Operation
With BEF# active, the SST31LF021/021E operate as a
256K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and internally
timed Erase and Program operations.
Flash Read
The Read operation of the SST31LF021/021E devices are
controlled by BEF# and OE#, both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when OE# is high. See Figure 4
for the Read cycle timing diagram.
Data Sheet
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
3
2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01 392
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST31LF021/021E.
SDP commands are loaded to the flash memory bank
using standard microprocessor write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
Flash Byte-Program Operation
The flash memory bank of the SST31LF021/021E devices
are programmed on a byte-by-byte basis. Before the Pro-
gram operations, the memory must be erased first. The
Program operation consists of three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load byte address and byte data.
During the Byte-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either BEF# or WE#, whichever occurs first. The third step
is the internal Program operation which is initiated after the
rising edge of the fourth WE# or BEF#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted, within 20 s. See Figures 5 and 6 for WE# and
BEF# controlled Program operation timing diagrams and
Figure 16 for flowcharts. During the Program operation, the
only valid Flash Read operations are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any SDP commands
loaded during the internal Program operation will be
ignored.
Flash Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
flash memory bank on a sector-by-sector basis. The sector
architecture is based on uniform sector size of 4 KByte.
The Sector-Erase operation is initiated by executing a six-
byte command load sequence for Software Data Protec-
tion with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The address lines A
17
-A
12
will be
used to determine the sector address. The sector address
is latched on the falling edge of the sixth WE# pulse, while
the command (30H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Fig-
ure 9 for timing waveforms. Any SDP commands loaded
during the Sector-Erase operation will be ignored.
Flash Bank-Erase Operation
The SST31LF021/021E flash memory bank provides a
Bank-Erase operation, which allows the user to erase the
entire flash memory bank array to the `1's state. This is use-
ful when the entire bank must be quickly erased. The Bank-
Erase operation is initiated by executing a six-byte Software
Data Protection command sequence with Bank-Erase com-
mand (10H) with address 5555H in the last byte sequence.
The internal Erase operation begins with the rising edge of
the sixth WE# or BEF# pulse, whichever occurs first. During
the internal Erase operation, the only valid Flash Read oper-
ations are Toggle Bit and Data# Polling. See Table 4 for the
command sequence, Figure 10 for timing diagram, and Fig-
ure 19 for the flowchart. Any SDP commands loaded during
the Bank-Erase operation will be ignored.
Flash Write Operation Status Detection
The SST31LF021/021E flash memory bank provides two
software means to detect the completion of a flash memory
bank Write (Program or Erase) cycle, in order to optimize
the system Write cycle time. The software detection
includes two status bits: Data# Polling (DQ
7
) and Toggle Bit
(DQ
6
). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program
or Erase operation. The actual completion of the nonvola-
tile write is asynchronous with the system; therefore, either
a Data# Polling or Toggle Bit Read may be simultaneous
with the completion of the Write cycle. If this occurs, the
system may possibly get an erroneous result, i.e., valid
data may appear to conflict with either DQ
7
or DQ
6
. In
order to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Flash Data# Polling (DQ
7
)
When the SST31LF021/021E flash memory bank is in the
internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Pro-
gram operation is completed, DQ
7
will produce true data.
Note that even though DQ
7
may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 s. During inter-
nal Erase operation, any attempt to read DQ
7
will produce
a `0'. Once the internal Erase operation is completed, DQ
7
will produce a `1'. The Data# Polling is valid after the rising
edge of the fourth WE# (or BEF#) pulse for Program opera-
tion. For Sector or Bank-Erase, the Data# Polling is valid
4
Data Sheet
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01 392
after the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 7 for Data# Polling timing diagram and Figure 17 for
a flowchart.
Flash Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BE#) pulse for Program operation. For Sec-
tor or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 8 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
Flash Memory Data Protection
The SST31LF021/021E flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST31LF021/021E provide the JEDEC approved
Software Data Protection scheme for all flash memory
bank data alteration operations, i.e., Program and Erase.
Any Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST31LF021/021E devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid SDP commands will abort the device to
the Read mode, within T
RC.
Concurrent Read and Write Operations
The SST31LF021/021E provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the flash. The device will
ignore all SDP commands when an Erase or Program
operation is in progress. This allows data alteration code to
be executed from SRAM, while altering the data in flash.
The following table lists all valid states. SST does not rec-
ommend that both bank enables, BEF# and BES#, be
simultaneously asserted.
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
Product Identification
The Product Identification mode identifies the devices as
either SST31LF021 or SST31LF021E and the manufac-
turer as SST. This mode may be accessed by hardware or
software operations. The hardware device ID Read opera-
tion is typically used by a programmer to identify the correct
algorithm for the SST31LF021/021E flash memory banks.
Users may wish to use the software Product Identification
operation to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For
details, see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the software ID entry and
read timing diagram and Figure 18 for the ID entry com-
mand sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
T
ABLE
Flash
SRAM
Program/Erase
Read
Program/Erase
Write
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
Data
Manufacturer's ID
0000H
BFH
Device ID
SST31LF021
0001H
18H
SST31LF021E
0001H
19H
T1.4 392
Data Sheet
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
5
2001 Silicon Storage Technology, Inc.
S71137-03-000
10/01 392
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 12 for timing waveform and
Figure 18 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 F ceramic capac-
itor to be placed as close as possible between V
DD
and
V
SS
, e.g., less than 1 cm away from the V
DD
pin of the
device. Additionally, a low frequency 4.7 F electrolytic
capacitor from V
DD
to V
SS
should be placed within 1 cm of
the V
DD
pin.
FIGURE 1: P
IN
A
SSIGNMENTS
FOR
32-
LEAD
TSOP (8
MM
X
14
MM
)
I/O Buffers
392 ILL B1.2
Address Buffers
DQ7 - DQ0
SuperFlash
Memory
SRAM
Control Logic
Address Buffers
& Latches
OE#
BEF#
WE#
BES#
AMS - A0
Note: AMS = Most Significant Address
F
UNCTIONAL
B
LOCK
D
IAGRAM
A11
A9
A8
A13
A14
A17
WE#
VDD
BES#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
392 ILL F01.3
Standard Pinout
Top View
Die Up
A11
A9
A8
A13
A14
A17
BES#
VDD
WE#
A16
A15
A12
A7
A6
A5
A4
SST31LF021E
SST31LF021
SST31LF021
SST31LF021E
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