8/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.

CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Advance Information

FEATURES:

Flash Organization: 2M x16 or 4M x8

Dual-Bank Architecture for Concurrent
Read/Write Operation

32 Mbit Top Sector Protection
SST34HF32x4x: 8 Mbit + 24Mbit
SST34HF32x2x: 4 Mbit + 28 Mbit

(P)SRAM Organization:

4 Mbit: 256K x16
8 Mbit: 512K x16

Single 2.7-3.3V Read and Write Operations

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 25 mA (typical)
Standby Current: 20 µA (typical)

Hardware Sector Protection (WP#)

Protects 8 KWord in the smaller bank by holding

WP# low and unprotects by holding WP# high

Hardware Reset Pin (RST#)

Resets the internal state machine to reading

data array

Byte Selection for Flash (CIOF pin)

Selects 8-bit or 16-bit mode

Sector-Erase Capability

Uniform 2 KWord sectors

Flash Chip-Erase Capability

Block-Erase Capability

Uniform 32 KWord blocks

Erase-Suspend / Erase-Resume Capabilities

Read Access Time

Flash: 70 ns
(P)SRAM: 70 ns

Security ID Feature

SST: 128 bits
User: 256 bits

Latched Address and Data

Fast Erase and Program (typical):

Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 35 ms
Program Time: 7 µs

Automatic Write Timing

Internal

Generation

End-of-Write Detection

Toggle Bit
Data# Polling
Ready/Busy# pin

CMOS I/O Compatibility

JEDEC Standard Command Set

Packages Available

56-ball LFBGA (8mm x 10mm)
62-ball LFBGA (8mm x 10mm)

All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST34HF32x2xC/32x4x ComboMemory devices inte-
grate either a 2M x16 or 4M x8 CMOS flash memory bank
with either a 256K x16 or 512K x16 CMOS SRAM or
pseudo SRAM (PSRAM) memory bank in a multi-chip
package (MCP). These devices are fabricated using SST's
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF32x2xC/32x4x devices are ideal for applications
such as cellular phones, GPS devices, PDAs, and other
portable electronic devices in a low power and small form
factor system.

The SST34HF32x2xC/32x4x feature dual flash memory
bank architecture allowing for concurrent operations
between the two flash memory banks and the (P)SRAM.
The devices can read data from either bank while an Erase
or Program operation is in progress in the opposite bank.

The two flash memory banks are partitioned into 4 Mbit +
28 Mbit or 8 Mbit + 24 Mbit with top sector protection
options for storing boot code, program code, configuration/
parameter data and user data.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF32x2xC/32x4x devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years. With high-performance
Program operations, the flash memory banks provide a
typical Program time of 7 µsec. The entire flash memory
bank can be erased and programmed word-by-word in typ-
ically 4 seconds for the SST34HF32x2xC/32x4x, when
using interface features such as Toggle Bit, Data# Polling,

32 Mbit Concurrent SuperFlash + 4/8 Mbit (P)SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM (x16) MCP ComboMemory

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

or RY/BY# to indicate the completion of Program operation.
To protect against inadvertent flash write, the
SST34HF32x2xC/32x4x devices contain on-chip hardware
and software data protection schemes.

The flash and (P)SRAM operate as two independent mem-
ory banks with respective bank enable signals. The mem-
ory bank selection is done by two bank enable signals. The
(P)SRAM bank enable signals, BES1# and BES2, select
the (P)SRAM bank. The flash memory bank enable signal,
BEF#, has to be used with Software Data Protection (SDP)
command sequence when controlling the Erase and Pro-
gram operations in the flash memory bank. The memory
banks are superimposed in the same memory address
space where they share common address lines, data lines,
WE# and OE# which minimize power consumption and
area.

Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF32x2xC/
32x4x are offered in both commercial and extended tem-
peratures and a small footprint package to meet board
space constraint requirements. See Figure 1 for pin assign-
ments.

Device Operation

The SST34HF32x2xC/32x4x uses BES1#, BES2 and
BEF# to control operation of either the flash or the
(P)SRAM memory bank. When BEF# is low, the flash bank
is activated for Read, Program or Erase operation. When
BES1# is low, and BES2 is high the (P)SRAM is activated
for Read and Write operation. BEF# and BES1# cannot be
at low level, and BES2 cannot be at high level at the same
time. If all bank enable signals are asserted, bus con-
tention will result and the device may suffer permanent
damage. All address, data, and control lines are shared by
flash and (P)SRAM memory banks which minimizes power
consumption and loading. The device goes into standby
when BEF# and BES1# bank enables are raised to V

IHC

(Logic High) or when BEF# is high and BES2 is low.

Concurrent Read/Write Operation

Dual bank architecture of SST34HF32x2xC/32x4x devices
allows the Concurrent Read/Write operation whereby the
user can read from one bank while programming or eras-
ing in the other bank. This operation can be used when the
user needs to read system code in one bank while updat-
ing data in the other bank. See Table 3 for dual-bank mem-
ory organization.

Note: For the purposes of this table, write means to perform

Block-/Sector-Erase or Program operations
as applicable to the appropriate bank.

Flash Read Operation

The Read operation of the SST34HF32x2xC/32x4x is con-
trolled by BEF# and OE#, both have to be low for the sys-
tem to obtain data from the outputs. BEF# is used for
device selection. When BEF# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output pins.
The data bus is in high impedance state when either BEF#
or OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 6).

ONCURRENT

EAD

RITE

TATES

Flash

(P)SRAM

Bank 1

Bank 2

Read

Write

No Operation

Write

Read

No Operation

Write

No Operation

Read

No Operation

Write

Read

Write

No Operation

Write

No Operation

Write

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Flash Program Operation

These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the CIOF pin.
Before programming, one must ensure that the sector
being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.

See Figures 7 and 8 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 21 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.

Flash Sector- /Block-Erase Operation

These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (50H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (30H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 12 and 13 for timing wave-
forms.

Flash Chip-Erase Operation

The SST34HF32x2xC/32x4x provide a Chip-Erase opera-
tion, which allows the user to erase all flash sectors/blocks
to the "1" state. This is useful when the device must be
quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 6 for the command sequence, Figure 11 for timing
diagram, and Figure 25 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored.

Flash Erase-Suspend/-Resume Operations

The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (T

maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ

toggling and

at "1". While in Erase-Suspend mode, a Program

operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block-
Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one-
byte sequence.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Flash Write Operation Status Detection

The SST34HF32x2xC/32x4x provide one hardware and
two software means to detect the completion of a Write
(Program or Erase) cycle, in order to optimize the system
Write cycle time. The hardware detection uses the
Ready/Busy# (RY/BY#) pin. The software detection
includes two status bits: Data# Polling (DQ

) and Toggle

Bit (DQ

). The End-of-Write detection mode is enabled

after the rising edge of WE#, which initiates the internal
Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ

) or Toggle Bit (DQ

) read may be

simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ

. In order to prevent spurious rejection, if an erroneous

result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.

Ready/Busy# (RY/BY#)

The SST34HF32x2xC/32x4x include a Ready/Busy# (RY/
BY#) output signal. RY/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to V

via an external

pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.

Byte/Word (CIOF)

The device includes a CIOF pin to control whether the
device data I/O pins operate x8 or x16. If the CIOF pin is at
logic "1" (V

) the device is in x16 data configuration: all

data I/0 pins DQ

-DQ

are active and controlled by BEF#

and OE#.

If the CIOF pin is at logic "0", the device is in x8 data config-
uration: only data I/O pins DQ

-DQ

are active and con-

trolled by BEF# and OE#. The remaining data pins DQ

are at Hi-Z, while pin DQ

is used as the address

input A

-1

for the Least Significant Bit of the address bus.

Flash Data# Polling (DQ

)

When the devices are in an internal Program operation, any
attempt to read DQ

will produce the complement of the

true data. Once the Program operation is completed, DQ

will produce true data. During internal Erase operation, any
attempt to read DQ

will produce a `0'. Once the internal

Erase operation is completed, DQ

will produce a `1'. The

Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Poll-
ing (DQ

) timing diagram and Figure 22 for a flowchart.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Toggle Bits (DQ

and DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating "1"s

and "0"s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ

bit will

stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ

) is valid after the

rising edge of sixth WE# (or BEF#) pulse. DQ

will be set to

"1" if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ

will

toggle.

An additional Toggle Bit is available on DQ

, which can be

used in conjunction with DQ

to check whether a particular

sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ

)

is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 22 for a flowchart.

Note: DQ

and DQ

require a valid address when reading

status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.

Data Protection

The SST34HF32x2xC/32x4x provide both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Hardware Block Protection

The SST34HF32x2xC/32x4x provide a hardware block
protection which protects the outermost 8 KWord/16 KByte
in Bank 1. The block is protected when WP# is held low.
When WP# is held low and a Block-Erase command is
issued to the protected block, the data in the outermost 8
KWord/16 KByte section will be protected. The rest of the
block will be erased. See Table 3 for Block-Protection loca-
tion.

A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T

RP,

any in-progress operation will terminate and

return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of T

RHR

is required after RST# is driven high before a valid

Read can take place (see Figure 17).

The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 17 and 18 for timing
diagrams.

TABLE

1: W

RITE

PERATION

TATUS

Status

RY/BY#

Normal
Operation

Standard
Program

DQ7#

Toggle

No Toggle

Standard
Erase

Toggle

Erase-
Suspend
Mode

Read From
Erase
Suspended
Sector/Block

Toggle

Read From
Non-Erase
Suspended
Sector/Block

Data

Program

DQ7#

Toggle

No Toggle

T1.1 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Software Data Protection (SDP)

The SST34HF32x2xC/32x4x provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST34HF32x2xC/32x4x are
shipped with the Software Data Protection permanently
enabled. See Table 6 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode within T

RC.

The

contents of DQ

-DQ

are "Don't Care" during any SDP

command sequence.

Common Flash Memory Interface (CFI)

These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address
BK

555H in the last byte sequence. In order to enter the

CFI Query mode, the system can also use the one-byte
sequence with BK

55H on Address and 98H on Data Bus.

See Figure 15 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 7
through 9. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.

Security ID

The SST34HF32x2xC/32x4x devices offer a 136-bit Secu-
rity ID space. The Secure ID space is divided into two seg-
ments--one 128-bit factory programmed segment and one
128-word (256-byte) user-programmed segment. The first
segment is programmed and locked at SST with a unique,
128-bit number. The user segment is left un-programmed
for the customer to program as desired.

To program the user segment of the Security ID, the user
must use the Security ID Program command. End-of-Write
status is checked by reading the toggle bits. Data# Polling
is not used for Security ID End-of-Write detection. Once
programming is complete, the Sec ID should be locked
using the User-Sec-ID-Program-Lock-Out. This disables
any future corruption of this space. Note that regardless of
whether or not the Sec ID is locked, neither Sec ID seg-
ment can be erased. The Secure ID space can be queried
by executing a three-byte command sequence with Query-
Sec-ID command (88H) at address 555H in the last byte
sequence. To exit this mode, the Exit-Sec-ID command
should be executed. Refer to Table 6 for more details.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Product Identification

The Product Identification mode identifies the device as
either SST34HF32x2x or SST34HF32x4x and manufac-
turer as SST. This mode may be accessed by software
operations only. The hardware device ID Read operation,
which is typically used by programmers cannot be used on
this device because of the shared lines between flash and
(P)SRAM in the multi-chip package. Therefore, application
of high voltage to pin A

may damage this device. Users

may use the software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Tables 5 and 6 for software operation, Figure 14 for the
Software ID Entry and Read timing diagram and Figure 23
for the ID Entry command sequence flowchart.

Note: BK = Bank Address (A

-A

)

Product Identification Mode Exit/
CFI Mode Exit

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 6 for software command codes, Fig-
ure 16 for timing waveform and Figure 23 for a flowchart.

(P)SRAM Operation

With BES1# low, BES2 and BEF# high, the
SST34HF32x2xC/32x4x operate as either 256K x16 or
512K x16 CMOS (P)SRAM, with fully static operation
requiring no external clocks or timing strobes. The
SST34HF32x2xC/32x4x (P)SRAM is mapped into the first
512 KWord address space. When BES1#, BEF# are high
and BES2 is low, all memory banks are deselected and the
device enters standby. Read and Write cycle times are
equal. The control signals UBS# and LBS# provide access
to the upper data byte and lower data byte. See Table 5 for
x16 (P)SRAM Read and Write data byte control modes of
operation.

(P)SRAM Read

The (P)SRAM Read operation of the SST34HF32x2xC/
32x4x is controlled by OE# and BES1#, both have to be
low with WE# and BES2 high for the system to obtain data
from the outputs. BES1# and BES2 are used for (P)SRAM
bank selection. OE# is the output control and is used to
gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to the Read
cycle timing diagram, Figure 3, for further details.

(P)SRAM Write

The (P)SRAM Write operation of the SST34HF32x2xC/
32x4x is controlled by WE# and BES1#, both have to be
low, BES2 must be high for the system to write to the
(P)SRAM. During the Word-Write operation, the addresses
and data are referenced to the rising edge of either BES1#,
WE#, or the falling edge of BES2 whichever occurs first.
The write time is measured from the last falling edge of
BES#1 or WE# or the rising edge of BES2 to the first rising
edge of BES1#, or WE# or the falling edge of BES2. Refer
to the Write cycle timing diagrams, Figures 4 and 5, for fur-
ther details.

TABLE

2: P

RODUCT

DENTIFICATION

ADDRESS

DATA

Manufacturer's ID

BK0000H

00BFH

Device ID

SST34HF3242C/3282

BK0001H

7351H

SST34HF3244C/3284

BK0001H

7353H

T2.0 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

3: D

UAL

-B

ANK

EMORY

RGANIZATION

SST34HF3242C/3282

SST34HF3244C/3284

Block

Block Size

Address Range x8

Address Range x16

Bank 1

BA63

8 KW / 16 KB

3FC000H3FFFFFH

1FE000H1FFFFFH

24 KW / 48 KB

3F0000H3FBFFFH

1F8000H1FDFFFH

BA62

32 KW / 64 KB

3E0000H3EFFFFH

1F0000H1F7FFFH

BA61

32 KW / 64 KB

3D0000H3DFFFFH

1E8000H1EFFFFH

BA60

32 KW / 64 KB

3C0000H3CFFFFH

1E0000H1E7FFFH

BA59

32 KW / 64 KB

3B0000H3BFFFFH

1D8000H1DFFFFH

BA58

32 KW / 64 KB

3A0000H3AFFFFH

1D0000H1D7FFFH

BA57

32 KW / 64 KB

390000H39FFFFH

1C8000H1CFFFFH

BA56

32 KW / 64 KB

380000H38FFFFH

1C0000H1C7FFFH

Bank 2

BA55

32 KW / 64 KB

370000H37FFFFH

1B8000H1BFFFFH

BA54

32 KW / 64 KB

360000H36FFFFH

1B0000H1B7FFFH

BA53

32 KW / 64 KB

350000H35FFFFH

1A8000H1AFFFFH

BA52

32 KW / 64 KB

340000H34FFFFH

1A0000H1A7FFFH

BA51

32 KW / 64 KB

330000H33FFFFH

198000H19FFFFH

BA50

32 KW / 64 KB

320000H32FFFFH

190000H197FFFH

BA49

32 KW / 64 KB

310000H31FFFFH

188000H18FFFFH

BA48

32 KW / 64 KB

300000H30FFFFH

180000H187FFFH

Bank 2

BA47

32 KW / 64 KB

2F0000H2FFFFFH

178000H17FFFFH

BA46

32 KW / 64 KB

2E0000H2EFFFFH

170000H177FFFH

BA45

32 KW / 64 KB

2D0000H2DFFFFH

168000H16FFFFH

BA44

32 KW / 64 KB

2C0000H2CFFFFH

160000H167FFFH

BA43

32 KW / 64 KB

2B0000H2BFFFFH

158000H15FFFFH

BA42

32 KW / 64 KB

2A0000H--2AFFFFH

150000H157FFFH

BA41

32 KW / 64 KB

290000H--29FFFFH

148000H14FFFFH

BA40

32 KW / 64 KB

280000H--28FFFFH

140000H147FFFH

BA39

32 KW / 64 KB

270000H--27FFFFH

138000H13FFFFH

BA38

32 KW / 64 KB

260000H--26FFFFH

130000H137FFFH

BA37

32 KW / 64 KB

250000H--25FFFFH

128000H12FFFFH

BA36

32 KW / 64 KB

240000H--24FFFFH

120000H127FFFH

BA35

32 KW / 64 KB

230000H--23FFFFH

118000H11FFFFH

BA34

32 KW / 64 KB

220000H--22FFFFH

110000H117FFFH

BA33

32 KW / 64 KB

210000H--21FFFFH

108000H10FFFFH

BA32

32 KW / 64 KB

200000H--20FFFFH

100000H107FFFH

BA31

32 KW / 64 KB

1F0000H--1FFFFFH

0F8000H0FFFFFH

BA30

32 KW / 64 KB

1E0000H--1EFFFFH

0F0000H0F7FFFH

BA29

32 KW / 64 KB

1D0000H--1DFFFFH

0E8000H0EFFFFH

BA28

32 KW / 64 KB

1C0000H--1CFFFFH

0E0000H0E7FFFH

BA27

32 KW / 64 KB

1B0000H--1BFFFFH

0D8000H0DFFFFH

BA26

32 KW / 64 KB

1A0000H--1AFFFFH

0D0000H0D7FFFH

BA25

32 KW / 64 KB

190000H--19FFFFH

0C8000H0CFFFFH

BA24

32 KW / 64 KB

180000H--18FFFFH

0C0000H0C7FFFH

BA23

32 KW / 64 KB

170000H--17FFFFH

0B8000H0BFFFFH

BA22

32 KW / 64 KB

160000H--16FFFFH

0B0000H0B7FFFH

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Bank 2

BA21

32 KW / 64 KB

150000H--15FFFFH

0A8000H0AFFFFH

BA20

32 KW / 64 KB

140000H--14FFFFH

0A0000H0A7FFFH

BA19

32 KW / 64 KB

130000H--13FFFFH

098000H09FFFFH

BA18

32 KW / 64 KB

120000H--12FFFFH

090000H097FFFH

BA17

32 KW / 64 KB

110000H--11FFFFH

088000H08FFFFH

BA16

32 KW / 64 KB

100000H--10FFFFH

080000H087FFFH

BA15

32 KW / 64 KB

0F0000H--0FFFFFH

078000H07FFFFH

BA14

32 KW / 64 KB

0E0000H--0EFFFFH

070000H077FFFH

BA13

32 KW / 64 KB

0D0000H--0DFFFFH

068000H06FFFFH

BA12

32 KW / 64 KB

0C0000H--0CFFFFH

060000H067FFFH

BA11

32 KW / 64 KB

0B0000H--0BFFFFH

058000H05FFFFH

BA10

32 KW / 64 KB

0A0000H--0AFFFFH

050000H057FFFH

BA9

32 KW / 64 KB

090000H--09FFFFH

048000H04FFFFH

BA8

32 KW / 64 KB

080000H--08FFFFH

040000H047FFFH

BA7

32 KW / 64 KB

070000H--07FFFFH

038000H03FFFFH

BA6

32 KW / 64 KB

060000H--06FFFFH

030000H037FFFH

BA5

32 KW / 64 KB

050000H05FFFFH

028000H02FFFFH

BA4

32 KW / 64 KB

040000H04FFFFH

020000H027FFFH

BA3

32 KW / 64 KB

030000H03FFFFH

018000H01FFFFH

BA2

32 KW / 64 KB

020000H02FFFFH

010000H017FFFH

BA1

32 KW / 64 KB

010000H01FFFFH

008000H00FFFFH

BA0

32 KW / 64 KB

000000H00FFFFH

000000H007FFFH

T3.0 1282

TABLE

3: D

UAL

-B

ANK

EMORY

RGANIZATION

ONTINUED

) (2

SST34HF3242C/3282

SST34HF3244C/3284

Block

Block Size

Address Range x8

Address Range x16

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

PIN DESCRIPTION

FIGURE 1: P

SSIGNMENTS

FOR

56-

BALL

LFBGA (8

)

FIGURE 2: P

SSIGNMENTS

FOR

62-

BALL

LFBGA (8

)

1
2
8
2

5
6
-
l
f
b
g
a

P

1
.
1

A11

WE#

WP#

LBS#

A15

A12

A19

BES2

RST#

UBS#

A13

A20

RY/BY#

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

CIOF

Note*

DQ13

DQ4

DQ3

DQ9

OE#

BEF#

VSS

DQ7

DQ12

VDDS

VDDF

DQ10

DQ0

BES1#

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H

8
7
6
5
4
3
2
1

TOP VIEW (balls facing down)

Note: F7 = DQ

-1

1
2
8
2

6
2
-
l
f
b
g
a

P

2
.
1

A20

A16

WEF#

VSSS

WP#

LBS#

A18

A11

RY/BY#

RST#

UBS#

A17

A15

A10

A19

OES#

A14

DQ11

A13

DQ15

DQ13

DQ12

DQ9

BEF#

A12

WES#

DQ6

BES2

DQ10

DQ8

VSSF

DQ14

DQ4

VDDS

DQ2

DQ0

OEF#

DQ7

DQ5

VDDF

DQ3

DQ1

BES1#

A B C D E F G H J K

8
7
6
5
4
3
2
1

TOP VIEW (balls facing down)

Note: LSE for SST34HF3244C/3284

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

4: P

ESCRIPTION

Symbol

Pin Name

Functions

to A

Address Inputs

To provide flash address, A

-A

To provide (P)SRAM address, A

MSS

-A

-DQ

Data Inputs/Outputs

To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

-1

Data Input/Output
and LBS Address

is used as data I/O pin when in x16 mode (CIOF = "1")

-1

is used as the LBS address pin when in x8 mode (CIOF = "0")

BEF#

Flash Memory Bank Enable

To activate the Flash memory bank when BEF# is low

BES1#

(P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES1# is low

BES2

(P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES2 is high

OEF#

Output Enable

To gate the data output buffers for Flash

only

OES#

Output Enable

To gate the data output buffers for SRAM

only

WEF#

Write Enable

To control the Write operations for Flash

only

WES#

Write Enable

To control the Write operations for SRAM

only

OE#

Output Enable

To gate the data output buffers

WE#

Write Enable

To control the Write operations

CIOF

Byte Selection for Flash

When low, select Byte mode. When high, select Word mode.

UBS#

Upper Byte Control ((P)SRAM)

To enable DQ

-DQ

LBS#

Lower Byte Control ((P)SRAM)

To enable DQ

-DQ

WP#

Write Protect

To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program
operation

RST#

Reset

To Reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10K

- 100K

pull-up resistor is required to

allow RY/BY# to transition high indicating the device is ready to read.

SSF

Ground

Flash

only

SSS

Ground

SRAM

only

Ground

Power Supply (Flash)

2.7-3.3V Power Supply to Flash only

Power Supply ((P)SRAM)

2.7-3.3V Power Supply to (P)SRAM only

No Connection

Unconnected pins

T4.0 1282

1. A

MSS

= Most Significant Address

MSS

= A

for SST34HF324xC and A

for SST34HF328x

2. LSE package only

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

5: O

PERATIONAL

ODES

ELECTION

FOR

16 (P)SRAM

Mode

BEF#

BES1#

1,2

BES2

1,2

OE#

2,3

WE#

2,3

LBS#

UBS#

15-8

7-0

CIOF = V

Full Standby

HIGH-Z

Output Disable

HIGH-Z HIGH-Z

HIGH-Z

Flash Read

OUT

14-8

= HIGH-Z

= A

-1

Flash Write

14-8

= HIGH-Z

= A

-1

Flash Erase

(P)SRAM Read

OUT

HIGH-Z

OUT

HIGH-Z

(P)SRAM Write

HIGH-Z

Product
Identification

Manufacturer's ID

Device ID

T5.1 1282

1. Do not apply BEF# = V

, BES1# = V

and BES2 = V

at the same time

2. X can be V

or V

IH,

but no other value.

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LSE package only

4. Software mode only
5. With A

-A

= V

IL;

SST Manufacturer's ID = BFH, is read with A

=0,

SST34HF32x2x Device ID = 7351H, is read with A

SST34HF32x4x Device ID = 7353H, is read with A

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

6: S

OFTWARE

OMMAND

EQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word-Program

555H

AAH

2AAH

55H

555H

A0H

Data

Sector-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

50H

Block-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

30H

Chip-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Erase-Suspend

XXXXH

B0H

Erase-Resume

XXXXH

30H

Query Sec ID

555H

AAH

2AAH

55H

555H

88H

User-Security-ID-
Program

555H

AAH

2AAH

55H

555H

A5H

SIWA

Data

User-Security-ID-
Program-Lock-out

555H

AAH

2AAH

55H

555H

85H

XXH

0000H

Software ID Entry

555H

AAH

2AAH

55H

555H

90H

CFI Query Entry

555H

AAH

2AAH

55H

555H

98H

CFI Query Entry

55H

98H

Software ID Exit/
CFI Exit/
Sec ID Exit

10,11

555H

AAH

2AAH

55H

555H

F0H

Software ID Exit/
CFI Exit/
Sec ID Exit

10,11

XXH

F0H

T6.1 1282

1. Address format A

10-

(Hex), Addresses A

-A

can be V

or V

, but no other value, for the command sequence when in x16 mode.

When in x8 mode, Addresses A

-A

12,

Address A

-1

and

-DQ

can be V

or V

, but no other value, for the command sequence.

2. DQ

-DQ

can be V

or V

, but no other value, for the command sequence

3. WA = Program Word/Byte address
4. SA

for Sector-Erase; uses A

-A

address lines

for Block-Erase; uses A

-A

address lines

5. For SST34HF32x2xC/32x4x the Security ID Address Range is:

(x16 mode) = 000000H to 000087H,

(x8 mode) = 000000H to 00010FH

SST ID is read at Address Range

(x16 mode) = 000000H to 000007H

(x8 mode) = 000000H to 00000FH

User ID is read at Address Range

(x16 mode) = 000008H to 000087H

(x8 mode) = 000010H to 00010FH

Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

6. SIWA = User Security ID Program Word/Byte address

For SST34HF32x2xC/32x4x, valid Address Range is
(x16 mode) = 000008H-000087H

(x8 mode) = 000010H-00010FH.

All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.

7. The User-Security-ID-Program-Lock-out command must be executed in x16 mode. (CIOF = V

)

8. The device does not remain in Software Product Identification mode if powered down.
9. A

and A

= V

10. Both Software ID Exit operations are equivalent
11. IIf users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

User Sec ID mode again (the programmed "0" bits cannot be reversed to "1").

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

7: CFI Q

UERY

DENTIFICATION

TRING1

Address

x16 Mode

Address
x8 Mode

Data

Description

10H

20H

0051H

Query Unique ASCII string "QRY"

11H

22H

0052H

12H

24H

0059H

13H

26H

0002H

Primary OEM command set

14H

28H

0000H

15H

2AH

0000H

Address for Primary Extended Table

16H

2CH

0000H

17H

2EH

0000H

Alternate OEM command set (00H = none exists)

18H

30H

0000H

19H

32H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

34H

0000H

T7.1 1282

1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.

TABLE

8: S

YSTEM

NTERFACE

NFORMATION

Address

x16 Mode

Address
x8 Mode

Data

1. In x8 mode, only the lower byte of data is output.

Description

1BH

36H

0027H

Min (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1CH

38H

0036H

Max (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1DH

3AH

0000H

min (00H = no V

pin)

1EH

3CH

0000H

max (00H = no V

pin)

1FH

3EH

0004H

Typical time out for Program 2

µs (2

= 16 µs)

20H

40H

0000H

Typical time out for min size buffer program 2

µs (00H = not supported)

21H

42H

0004H

Typical time out for individual Sector/Block-Erase 2

ms (2

= 16 ms)

22H

44H

0006H

Typical time out for Chip-Erase 2

ms (2

= 64 ms)

23H

46H

0001H

Maximum time out for Program 2

times typical (2

x 2

= 32 µs)

24H

48H

0000H

Maximum time out for buffer program 2

times typical

25H

4AH

0001H

Maximum time out for individual Sector-/Block-Erase 2

times typical (2

x 2

= 32 ms)

26H

4CH

0001H

Maximum time out for Chip-Erase 2

times typical (2

x 2

= 128 ms)

T8.0 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE

9: D

EVICE

EOMETRY

NFORMATION

Address

x16 Mode

Address
x8 Mode

Data

Description

27H

4EH

0016H

Device size = 2

Bytes (16H = 22; 2

= 4 MByte)

28H

50H

0002H

Flash Device Interface description; 0002H = x8/x16 asynchronous interface

29H

52H

0000H

2AH

54H

0000H

Maximum number of bytes in multi-byte write = 2

(00H = not supported)

2BH

56H

0000H

2CH

58H

0002H

Number of Erase Sector/Block sizes supported by device

2DH

5AH

003FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

2EH

5CH

0000H

y = 63 + 1 = 64 blocks (003FH = 63)

2FH

5EH

0000H

30H

60H

0001H

z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

31H

62H

00FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

32H

64H

0003H

y = 1023 + 1 = 1024 sectors (03FFH = 1023)

33H

66H

0010H

34H

68H

0000H

z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

T9.2 1282

1. In x8 mode, only the lower byte of data is output.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V

+1.0V

Package Power Dissipation Capability (T

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. V

= V

DDF

and V

DDS

2. Excluding certain with-Pb 32-PLCC units, all packages are 260

C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240

C for 10 seconds; please consult the factory for the latest information.

3. Outputs shorted for no more than one second. No more than one output shorted at a time.

PERATING

ANGE

Range

Ambient Temp

Commercial

0°C to +70°C

2.7-3.3V

Extended

-20°C to +85°C

2.7-3.3V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

= 30 pF

See Figures 19 and 20

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE 10: DC O

PERATING

HARACTERISTICS

= V

DDF

AND

DDS

= 2.7-3.3V)

Symbol

Parameter

Limits

Test Conditions

Min

Max

Units

Active V

Current

Address input = V

ILT

IHT,

at f=5 MHz,

Max, all DQs open

Read

OE#=V

, WE#=V

Flash

BEF#=V

, BES1#=V

or BES2=V

(P)SRAM

BEF#=V

, BES1#=V

IL ,

BES2=V

Concurrent Operation

BEF#=V

, BES1#=V

IL ,

BES2=V

Write

WE#=V

Flash

BEF#=V

, BES1#=V

or BES2=V

, OE#=V

(P)SRAM

BEF#=V

, BES1#=V

IL ,

BES2=V

Standby V

Current

SRAM
PSRAM

30
85

µA
µA

= V

Max, BEF#=BES1#=V

IHC

BES2=V

ILC

Reset

Current

µA

RST#=GND

Input Leakage Current

µA

=GND to V

, V

Max

LIW

Input Leakage Current
on WP# pin and RST# pin

µA

WP#=GND to V

, V

Max

RST#=GND to V

, V

Max

Output Leakage Current

µA

OUT

=GND to V

, V

Max

Input Low Voltage

0.8

Min

ILC

Input Low Voltage (CMOS)

0.3

Max

Input High Voltage

0.7

Max

IHC

Input High Voltage (CMOS)

-0.3

Max

OLF

Flash Output Low Voltage

0.2

=100 µA, V

Min

OHF

Flash Output High Voltage

-0.2

=-100 µA, V

Min

OLS

(P)SRAM Output Low Voltage

0.4

IOL =1 mA, V

Min

OHS

(P)SRAM Output High Voltage

2.2

IOH =-500 µA, V

Min

T10.0 1282

1. Address input = V

ILT

IHT,

Max (See Figure 19)

2. I

active while Erase or Program is in progress.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE 11: R

ECOMMENDED

YSTEM

OWER

IMINGS

Symbol

Parameter

Minimum

Units

PU-READ

Power-up to Read Operation

100

µs

PU-WRITE

Power-up to Write Operation

100

µs

T11.0 1282

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 12: C

APACITANCE

= 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance

I/O

= 0V

20 pF

Input Capacitance

= 0V

16 pF

T12.0 1282

TABLE 13: F

LASH

ELIABILITY

HARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

END

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance

10,000

Cycles

JEDEC Standard A117

Data Retention

100

Years

JEDEC Standard A103

LTH

Latch Up

100 + I

JEDEC Standard 78

T13.0 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

AC CHARACTERISTICS

TABLE 14: (P)SRAM R

EAD

YCLE

IMING

ARAMETERS

Min

Max

Units

RCS

Read Cycle Time

AAS

Address Access Time

BES

Bank Enable Access Time

OES

Output Enable Access Time

BYES

UBS#, LBS# Access Time

BLZS

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output

OLZS

Output Enable to Active Output

BYLZS

UBS#, LBS# to Active Output

BHZS

BES# to High-Z Output

OHZS

Output Disable to High-Z Output

BYHZS

UBS#, LBS# to High-Z Output

OHS

Output Hold from Address Change

T14.0 1282

TABLE 15: (P)SRAM W

RITE

YCLE

IMING

ARAMETERS

Symbol

Parameter

Min

Max

Units

WCS

Write Cycle Time

BWS

Bank Enable to End-of-Write

AWS

Address Valid to End-of-Write

ASTS

Address Set-up Time

WPS

Write Pulse Width

WRS

Write Recovery Time

BYWS

UBS#, LBS# to End-of-Write

ODWS

Output Disable from WE# Low

OEWS

Output Enable from WE# High

DSS

Data Set-up Time

DHS

Data Hold from Write Time

T15.0 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

TABLE 16: F

LASH

EAD

YCLE

IMING

ARAMETERS

= 2.7-3.3V

Symbol

Parameter

Min

Max

Units

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

BEF# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

BEF# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

500

RHR

RST# High Before Read

1,2

RST# Pin Low to Read

µs

T16.0 1282

1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.

TABLE 17: F

LASH

ROGRAM

RASE

YCLE

IMING

ARAMETERS

Symbol

Parameter

Min

Max

Units

Program Time

10 µs

Address Setup Time

Address Hold Time

WE# and BEF# Setup Time

WE# and BEF# Hold Time

OES

OE# High Setup Time

OEH

OE# High Hold Time

BEF# Pulse Width

WE# Pulse Width

WPH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High

CPH

BEF# Pulse Width High

Data Setup Time

Data Hold Time

IDA

Software ID Access and Exit Time

150

Erase-Suspend Latency

µs

1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RY/BY# Delay Time

Bus Recovery Time

µs

Sector-Erase

Block-Erase

SCE

Chip-Erase

T17.1 1282

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 3: (P)SRAM R

EAD

YCLE

IMING

IAGRAM

FIGURE 4: (P)SRAM W

RITE

YCLE

IMING

IAGRAM

(WE# C

ONTROLLED

)

ADDRESSES

MSS-0

15-0

UBS#, LBS#

OE#

BES1#

BES2

RCS

AAS

BES

OES

BLZS

OLZS

BYES

BYLZS

BYHZS

DATA VALID

OHZS

BHZS

OHS

1282 F01.0

BES

Note: A

MSS

= Most Significant Address

MSS

= A

for SST34HF324xC and A

for SST34HF328x

AWS

ADDRESSES

AMSS3-0

BES1#

BES2

WE#

UBS#, LBS#

WPS

WRS

WCS

ASTS

BWS

BYWS

ODWS

OEWS

DSS

DHS

1282 F02.0

NOTE 2

DQ15-8, DQ7-0

VALID DATA IN

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.
Because D

signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. A

MSS

= Most Significant SRAM Address

MSS

= A

for SST34HF324xC and A

for SST34HF328x

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 6: F

LASH

EAD

YCLE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= A

DDRESS

NPUT

)

FIGURE 7: F

LASH

WE# C

ONTROLLED

ROGRAM

YCLE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= A

DDRESS

NPUT

)

1282 F04.0

ADDRESS A

20-0

15-0

WE#

OE#

BEF#

OLZ

HIGH-Z

CLZ

CHZ

HIGH-Z

DATA VALID

OHZ

1282 F05.0

ADDRESS A

20-0

15-0

WPH

BEF#

RY/BY#

555

2AA

555

ADDR

XXAA

XX55

XXA0

DATA

WORD

(ADDR/DATA)

OE#

WE#

Note: X can be V

or V

, but no other value.

VALID

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 8: F

LASH

BEF# C

ONTROLLED

ROGRAM

YCLE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= A

DDRESS

NPUT

)

FIGURE 9: F

LASH

ATA

# P

OLLING

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= A

DDRESS

NPUT

)

VALID

1282 F06.0

ADDRESS A

20-0

15-0

CPH

WE#

555

2AA

555

ADDR

XXAA

XX55

XXA0

DATA

WORD

(ADDR/DATA)

OE#

BEF#

RY/BY#

Note: X can be V

or V

, but no other value.

1282 F07.0

ADDRESS A20-0

DQ7

DATA

DATA#

DATA

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

RY/BY#

TBY

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 10: F

LASH

OGGLE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= D

ARE

)

FIGURE 11: F

LASH

WE# C

ONTROLLED

HIP

-E

RASE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= D

ARE

)

1282 F08.0

ADDRESS A

20-0

WE#

OE#

BEF#

OEH

TWO READ CYCLES

WITH SAME OUTPUTS

VALID DATA

VALID

1282 F09.0

ADDRESS

20-0

15-0

WE#

555

2AA

555

XX55

XX10

XX55

XXAA

XX80

XXAA

555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

RY/BY#

Note: This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 17.)
X can be V

or V

IH,

but no other value.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 12: F

LASH

WE# C

ONTROLLED

LOCK

-E

RASE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= D

ARE

)

FIGURE 13: F

LASH

WE# C

ONTROLLED

ECTOR

-E

RASE

IMING

IAGRAM

FOR

ORD

ODE

YTE

ODE

-1

= D

ARE

)

1282 F10.0

ADDRESS

20-0

15-0

WE#

555

2AA

555

XX55

XX30

XX55

XXAA

XX80

XXAA

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

RY/BY#

VALID

Note: This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 17.)
BA

= Block Address

X can be V

or V

IH,

but no other value.

1282 F11.0

ADDRESS

20-0

15-0

WE#

555

2AA

555

XX55

XX50

XX55

XXAA

XX80

XXAA

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

RY/BY#

VALID

Note: This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 17.)
SA

= Sector Address

X can be V

or V

IH,

but no other value.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 14: F

LASH

OFTWARE

ID E

NTRY

AND

EAD

YTE

ODE

-1

= 0)

FIGURE 15: CFI E

NTRY

AND

EAD

1282 F12.0

ADDRESS A

20-0

IDA

15-0

WE#

555

2AA

555

0000

0001

OE#

BEF#

Three-Byte Sequence For Software ID Entry

WPH

00BF

Device ID

XX55

XXAA

XX90

Note: X can be V

or V

IH,

but no other value.

Device ID = 7351H for SST34HF3242C/3282 or 7353H for SST34HF3244C/3284

1282 F22.0

ADDRESSES

IDA

15-0

WE#

555

2AA

555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

WPH

XX55

XXAA

XX98

Note: X can be V

or V

IH,

but no other value.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 23: S

OFTWARE

RODUCT

ID C

OMMAND

LOWCHARTS

1282 F19.1

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

Software ID Exit/

CFI Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Wait TIDA

Return to normal

operation

Note: X can be V

or V

IH,

but no other value.

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait TIDA

Read CFI data

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

FIGURE 25: E

RASE

OMMAND

EQUENCE

1282 F21.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

Note: X can be V

or V

IH,

but no other value.

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

PRODUCT ORDERING INFORMATION

Environmental Attribute

= non-Pb

Package Modifier

P = 56 balls
S = 62 balls

Package Type

L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size)
L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Range

E = Extended = -20°C to +85°C

Minimum Endurance

4 =10,000 cycles

Read Access Speed

70 = 70 ns

Version

C = x16 Mbit SRAM
blank = x16 PSRAM

Bank Split and Top Boot Block Protection

2 = 4 Mbit + 28 Mbit
4 = 8 Mbit + 24 Mbit

(P)SRAM Density

4 = 4 Mbit
8 = 8 Mbit

Flash Density

32 = 32 Mbit

Voltage

H = 2.7-3.3V

Product Series

34 = Concurrent SuperFlash + (P)SRAM ComboMemory

1. Environmental suffix "E" denotes non-Pb solder.

SST non-Pb solder devices are "RoHS Compliant".

Device

Speed

Suffix1

Suffix2

SST34HF32x4X- XXX

XXXX

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory
SST34HF3242C / SST34HF3244C
SST34HF3282 / SST34HF3284

S71282-00-000

8/05

PACKAGING DIAGRAMS

56-

BALL

PROFILE

, F

INE

PITCH

ALL

RID

RRAY

(LFBGA) 8

SST P

ACKAGE

ODE

: L1P

H G F E D C B A

A B C D E F G H

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.30 ± 0.10

0.12

0.45 ± 0.05
(56X)

0.80

5.60

0.80

5.60

56-lfbga-L1P-8x10-450mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

A1 CORNER

BOTTOM VIEW

TOP VIEW

8.00 ± 0.20

A1 CORNER

10.00 ± 0.20

Advance Information

32 Mbit Concurrent SuperFlash + 4/8 Mbit SRAM ComboMemory

SST34HF3242C / SST34HF3244C

SST34HF3282 / SST34HF3284

S71282-00-000

8/05

62-

BALL

PROFILE

, F

INE

PITCH

ALL

RID

RRAY

(LFBGA) 8

SST P

ACKAGE

ODE

: LS

TABLE 18: R

EVISION

ISTORY

Number

Description

Date

Initial Release

Aug 2005

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEW

TOP VIEW

8.00 ± 0.20

0.40 ± 0.05
(62X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

7.20

62-lfbga-LS-8x10-400mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE

0.32 ± 0.05

1.30 ± 0.10

0.12

Silicon Storage Technology, Inc. · 1171 Sonora Court · Sunnyvale, CA 94086 · Telephone 408-735-9110 · Fax 408-735-9036

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