5/02

373

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Concurrent SuperFlash and CSF are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

FEATURES:

Organized as 1M x16

Dual Bank Architecture for Concurrent
Read/Write Operation

16 Mbit Bottom Sector Protection

- SST36VF1601: 12 Mbit + 4 Mbit

Single 2.7-3.6V for Read and Write Operations

Superior Reliability

Endurance: 100,000 cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 6 mA typical
Standby Current: 4 µA typical

Hardware Sector Protection/WP# Input Pin

Protects 4 outermost sectors (4 KWord) in the

larger bank by driving WP# low and unprotects
by driving WP# high

Hardware Reset Pin (RST#)

Resets the internal state machine to reading

array data

Sector-Erase Capability

Uniform 1 KWord sectors

Block-Erase Capability

Uniform 32 KWord blocks

Fast Read Access Time

70 ns

Latched Address and Data

Fast Erase and Word-Program (typical):

Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 70 ms
Word-Program Time: 14 µs
Chip Rewrite Time: 8 seconds

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling
Ready/Busy# pin

CMOS I/O Compatibility

Conforms to Common Flash Memory Interface (CFI)

JEDEC Standards

Flash EEPROM Pinouts and command sets

Packages Available

48-lead TSOP (12mm x 20mm)
48-ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST36VF1601 is 1M x16 CMOS Concurrent Read/
Write Flash Memory manufactured with SST's proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST36VF1601 writes (Program
or Erase) with a 2.7-3.6V power supply. The
SST36VF1601 device conforms to JEDEC standard
pinouts for x16 memories.

Featuring high performance Word-Program, the
SST36VF1601 device provides a typical Word-Program
time of 14 µsec. The devices use Toggle Bit or Data# Poll-
ing to detect the completion of the Program or Erase opera-
tion. To protect against inadvertent write, the
SST36VF1601 device has on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, the
SST36VF1601 device is offered with a guaranteed endur-
ance of 10,000 cycles. Data retention is rated at greater
than 100 years.

The SST36VF1601 is suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, the
SST36VF1601 significantly improves performance and reli-
ability, while lowering power consumption. The
SST36VF1601 inherently uses less energy during Erase
and Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies. The SST36VF1601 also
improves flexibility while lowering the cost for program,
data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.

SST36VF16012.7V 16Mb (x16) Concurrent SuperFlash

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

To meet high density, surface mount requirements, the
SST36VF1601 is offered in 48-lead TSOP and 48-ball
TFBGA packages. See Figures 2 and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.

Concurrent Read/Write Operation

Dual bank architecture of SST36VF1601 device allows the
Concurrent Read/Write operation whereby the user can
read from one bank while program or erase in the other
bank. This operation can be used when the user needs to
read system code in one bank while updating data in the
other bank.

Note: For the purposes of this table, write means to perform Block-,

Sector-, or Chip-Erase or Word-Program operations as appli-
cable to the appropriate bank.

Read Operation

The Read operation of the SST36VF1601 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the out-
put control and is used to gate data on the output pins.
The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 4).

Word-Program Operation

The SST36VF1601 is programmed on a word-by-word
basis. Before programming, one must ensure that the sec-
tor, in which the word which is being programmed exists, is
fully erased. The Program operation consists of three
steps. The first step is the three-byte load sequence for
Software Data Protection. The second step is to load word
address and word data. During the Word-Program opera-
tion, the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last. The data is latched
on the rising edge of either CE# or WE#, whichever occurs
first. The third step is the internal Program operation which
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed typically within 10 µs. See Figures
5 and 6 for WE# and CE# controlled Program operation
timing diagrams and Figure 19 for flowcharts. During the
Program operation, the only valid reads are Data# Polling
and Toggle Bit. During the internal Program operation, the
host is free to perform additional tasks. Any commands
issued during the internal Program operation are ignored.
After detecting the completion of a Word-Program
operation (either through RY/BY# line, Data# Polling,
or Toggle Bit), the host must keep CE# signal low for a
minimum duration of Program Recovery Time
(T

= ~1 µs) before valid data can be read correctly.

Please see Figures 5 through 8 for corresponding AC
timing diagrams.

Sector- (Block-) Erase Operation

The Sector- (Block-) Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF1601 offers both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 1 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. See Figures 10
and 11 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.

ONCURRENT

EAD

RITE

TATE

Bank 1

Bank 2

Read

No Operation

Read

Write

Read

Write

No Operation

Read

No Operation

Write

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

Chip-Erase Operation

The SST36VF1601 provides a Chip-Erase operation,
which allows the user to erase all unprotected sectors/
blocks to the "1" state. This is useful when the device must
be quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. See
Table 4 for the command sequence, Figure 9 for timing dia-
gram, and Figure 22 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST36VF1601 provides one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two status
bits: Data# Polling (DQ

) and Toggle Bit (DQ

). The End-of-

Write detection mode is enabled after the rising edge of
WE#, which initiates the internal Program or Erase opera-
tion.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ

) or Toggle Bit (DQ

) read may

be simultaneous with the completion of the Write cycle. If
this occurs, the system may possibly get an erroneous
result, i.e., valid data may appear to conflict with either DQ

or DQ

. In order to prevent spurious rejection, if an errone-

ous result occurs, the software routine should include a
loop to read the accessed location an additional two (2)
times. If both reads are valid, then the device has com-
pleted the Write cycle, otherwise the rejection is valid.

Ready/Busy# (RY/BY#)

The SST36VF1601 includes a Ready/Busy# (RY/BY#)
output signal. RY/BY# is actively pulled low while during an
internal Erase or Program operation is in progress. RY/BY#
is an open drain output that allows several devices to be
tied in parallel to V

via an external pull up resistor. RY/

BY# is high impedance whenever CE# is high or RST# is
low. There is a 1 µs bus recovery time (T

) required before

valid data can be read on the data bus. New commands
can be entered immediately after RY/BY# goes high.

Data# Polling (DQ

)

When the SST36VF1601 is in the internal Program opera-
tion, any attempt to read DQ

will produce the complement

of the true data. Once the Program operation is completed,
DQ

will produce true data. During internal Erase opera-

tion, any attempt to read DQ

will produce a `0'. Once the

internal Erase operation is completed, DQ

will produce a

`1'. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling (DQ

) timing diagram and Figure 20 for a

flowchart. There is a 1 µs bus recovery time (T

) required

before valid data can be read on the data bus. New com-
mands can be entered immediately after DQ

becomes

true data.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ

bit will

stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 8 for
Toggle Bit timing diagram and Figure 20 for a flowchart.
There is a 1 µs bus recovery time (T

) required before

valid data can be read on the data bus. New commands
can be entered immediately after DQ

no longer toggles.

Data Protection

The SST36VF1601 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

Hardware Block Protection

The SST36VF1601 provides a hardware block protection
which protects the outermost 4 KWord in the larger bank.
The block is protected when WP# is held low. See Figure 1
for Block-Protection location.

A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T

RP,

any in-progress operation will terminate and

return to Read mode (see Figure 16). When no internal
Program/Erase operation is in progress, a minimum period
of T

RHR

is required after RST# is driven high before a valid

Read can take place (see Figure 15).

The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.

Software Data Protection (SDP)

The SST36VF1601 provides the JEDEC standard Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST36VF1601 is shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within T

RC.

The contents of DQ

can be V

or V

, but no other value during any SDP

command sequence.

Common Flash Memory Interface (CFI)

The SST36VF1601 also contains the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.

Product Identification

The Product Identification mode identifies the device and
manufacturer. For details, see Table 4 for software opera-
tion, Figure 12 for the Software ID Entry and Read timing
diagram and Figure 21 for the Software ID Entry command
sequence flowchart.

Product Identification Mode
Exit/CFI Mode Exit

In order to return to the standard Read mode, the Soft-
ware Product Identification mode must be exited. Exit is
accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program
or Erase operation. See Table 4 for the software command
code, Figure 14 for timing waveform and Figure 21 for a
flowchart.

TABLE

1: P

RODUCT

DENTIFICATION

Word

Data

Manufacturer's ID

0000H

00BFH

Device ID

SST36VF1601

0001H

2761H

T1.1 373

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

FIGURE 1: SST36VF1601, 1 M

BIT

16 C

ONCURRENT

UPER

LASH

UAL

-B

ANK

EMORY

RGANIZATION

FFFFFH

F8000H

Block 31

F7FFFH

F0000H

Block 30

EFFFFH

E8000H

Block 29

E7FFFH

E0000H

Block 28

DFFFFH

D8000H

Block 27

D7FFFH

D0000H

Block 26

CFFFFH
C8000H

Block 25

C7FFFH

C0000H

Block 24

Bank 2

BFFFFH

B8000H

Block 23

B7FFFH

B0000H

Block 22

AFFFFH

A8000H

Block 21

A7FFFH
A0000H

Block 20

9FFFFH
98000H

Block 19

97FFFH
90000H

Block 18

8FFFFH
88000H

Block 17

87FFFH
80000H

Block 16

7FFFFH
78000H

Block 15

77FFFH
70000H

Block 14

6FFFFH
68000H

Block 13

67FFFH
60000H

Block 12

5FFFFH
58000H

Block 11

57FFFH
50000H

Block 10

4FFFFH
48000H

Block 9

47FFFH
40000H

Block 8

3FFFFH
38000H

Block 7

37FFFH
30000H

Block 6

2FFFFH
28000H

Block 5

27FFFH
20000H

Block 4

1FFFFH
18000H

Block 3

17FFFH
10000H

Block 2

00FFFFH
008000H

Block 1

007FFFH
001000H
000FFFH
000000H

Block 0

Bank 1

Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors

4 KWord Sector Protection

(4- 1 KWord Sectors)

373 ILL F38.2

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

FIGURE 2: P

SSIGNMENTS

FOR

48-

LEAD

TSOP (12

)

FIGURE 3: P

SSIGNMENTS

FOR

48-

BALL

TFBGA (8

)

A15
A14
A13
A12
A11
A10

A9
A8

A19

WE#

RST#

WP#

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

373 ILL F01b.3

Standard Pinout

Top View

Die Up

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

373 ILL F01a.7

SST36VF1601

TOP VIEW (balls facing down)

A B C D E F G H

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

TABLE

2: P

ESCRIPTION

Symbol

Name

Functions

-A

Address Inputs

To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A

-A

address lines will select the sector. During Block-Erase A

-A

address lines

will select the block.

-DQ

Data Input/output

To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when OE#
or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers

WE#

Write Enable

To control the Write operations

RST#

Hardware Reset

To reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10K

- 100K pull-up resistor is required to allow

RY/BY# to transition high indicating the device is ready to read.

WP#

Write Protect

To protect and unprotect the bottom 4 sectors from Erase or Program operation.

Power Supply

To provide 2.7-3.6V power supply voltage

Ground

No Connection

Unconnected pins

T2.6 373

TABLE

3: O

PERATION

ODES

ELECTION

Mode

CE#

OE#

WE#

Address

Read

OUT

Program

Erase

1. X can be VIL or VIH, but no other value.

Sector or block address,

XXH for Chip-Erase

Standby V

High Z

Write Inhibit

High Z / D

OUT

High Z / D

OUT

Product Identification

Software Mode

Manufacturer's ID (00BFH)

See Table 4

Device ID

2. Device ID = 2761H

T3.6 373

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

TABLE

4: S

OFTWARE

OMMAND

EQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word-Program

5555H

AAH

2AAAH

55H

5555H

A0H

Data

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Software ID Entry

5,6

5555H

AAH

2AAAH

55H

5555H

90H

CFI Query Entry

5555H

AAH

2AAAH

55H

5555H

98H

Software ID Exit/
CFI Exit

5555H

AAH

2AAAH

55H

5555H

F0H

T4.4 373

1. Address format A

-A

(Hex), Addresses A

- A

can be V

or V

, but no other value, for the Command sequence.

2. DQ

-DQ

can be V

or V

, but no other value, for the Command sequence

3. WA = Program word address
4. SA

for Sector-Erase; uses A

-A

address lines

for Block-Erase; uses A

-A

address lines

5. The device does not remain in Software Product Identification mode if powered down.
6. With A

-A

= 0;

SST Manufacturer's ID = 00BFH, is read with A

= 0

SST36VF1601 Device ID = 2761H, is read with A

= 1

TABLE

5: CFI Q

UERY

DENTIFICATION

TRING1

1. Refer to CFI publication 100 for more details.

Address

Data

10H

0051H

Query Unique ASCII string "QRY"

11H

0052H

12H

0059H

13H

0001H

Primary OEM command set

14H

0007H

15H

0000H

Address for Primary Extended Table

16H

0000H

17H

0000H

Alternate OEM command set (00H = none exists)

18H

0000H

19H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

0000H

T5.0 373

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

TABLE

6: S

YSTEM

NTERFACE

NFORMATION

Address

Data

1BH

0027H

Min (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1CH

0036H

Max (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1DH

0000H

min (00H = no V

pin)

1EH

0000H

max (00H = no V

pin)

1FH

0004H

Typical time out for Word-Program 2

µs (2

= 16 µs)

20H

0000H

Typical time out for min size buffer program 2

µs (00H = not supported)

21H

0004H

Typical time out for individual Sector/Block-Erase 2

ms (2

= 16 ms)

22H

0006H

Typical time out for Chip-Erase 2

ms (2

= 64 ms)

23H

0001H

Maximum time out for Word-Program 2

times typical (2

x 2

= 32 µs)

24H

0000H

Maximum time out for buffer program 2

times typical

25H

0001H

Maximum time out for individual Sector/Block-Erase 2

times typical (2

x 2

= 32 ms)

26H

0001H

Maximum time out for Chip-Erase 2

times typical (2

x 2

= 128 ms)

T6.0 373

TABLE

7: D

EVICE

EOMETRY

NFORMATION

Address

Data

27H

0015H

Device size = 2

Bytes (15H = 21; 2

= 2 MByte)

28H

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

0000H

2AH

0000H

Maximum number of bytes in multi-byte write = 2

(00H = not supported)

2BH

0000H

2CH

0002H

Number of Erase Sector/Block sizes supported by device

2DH

00FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

0003H

y = 1023 + 1 = 1024 sectors (03FFH = 1023)

2FH

0008H

30H

0000H

z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8)

31H

003FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

0000H

y = 31 + 1 = 32 blocks (001FH = 31)

33H

0000H

34H

0001H

z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.4 373

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

+2.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

PERATING

ANGE

Range

Ambient Temp

Commercial

0°C to +70°C

2.7-3.6V

Extended

-20°C to +85°C

2.7-3.6V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

= 30 pF

See Figures 17 and 18

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

TABLE

8: DC O

PERATING

HARACTERISTICS

= 2.7-3.6V

Symbol

Parameter

Limits

Test Conditions

Min

Max

Units

Active V

Current

Address input=V

, at f=1/T

Min,

Max

Read

CE#=OE#=V

, WE#=V

, all I/Os open

Program and Erase

CE#=V

, OE#=V

Concurrent Read/Write

Standby V

Current

µA

CE#=V

IHC

, V

Max

Reset V

Current

µA

RST# = V

± 0.3V

Input Leakage Current

µA

=GND to V

, V

Max

Output Leakage Current

µA

OUT

=GND to V

, V

Max

Input Low Voltage

0.8

Min

ILC

Input Low Voltage (CMOS)

0.3

Max

Input High Voltage

0.7 V

Max

IHC

Input High Voltage (CMOS)

-0.3

Max

Output Low Voltage

0.2

=100 µA, V

Min

Output High Voltage

-0.2

=-100 µA, V

Min

T8.6 373

TABLE

9: R

ECOMMENDED

YSTEM

OWER

IMINGS

Symbol

Parameter

Minimum

Units

PU-READ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation

100

µs

PU-WRITE

Power-up to Write Operation

100

µs

T9.2 373

TABLE 10: C

APACITANCE

(Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance

I/O

= 0V

10 pF

Input Capacitance

= 0V

10 pF

T10.0 373

TABLE 11: R

ELIABILITY

HARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

END

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance

10,000

Cycles

JEDEC Standard A117

Data Retention

100

Years

JEDEC Standard A103

LTH

Latch Up

100 + I

JEDEC Standard 78

T11.1 373

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

AC CHARACTERISTICS

TABLE 12: R

EAD

YCLE

IMING

ARAMETERS

= 2.7-3.6V

Symbol

Parameter

SST36VF1601-70

Units

Min

Max

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

CE# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

500

RHR

RST# High before Read

1,2

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase opera-

tions.

RST# Pin Low to Read Mode

150

µs

T12.9 373

TABLE 13: P

ROGRAM

RASE

YCLE

IMING

ARAMETERS

Symbol

Parameter

Min

Max

Units

Word-Program Time

µs

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OES

OE# High Setup Time

OEH

OE# High Hold Time

CE# Pulse Width

WE# Pulse Width

WPH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High

CPH

CE# Pulse Width High

Data Setup Time

Data Hold Time

IDA

Software ID Access and Exit Time

150

Sector-Erase

Block-Erase

SCE

Chip-Erase

100

RY/BY# Delay Time

Program Recovery Time

µs

T13.7 373

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

FIGURE 10: WE# C

ONTROLLED

LOCK

-E

RASE

IMING

IAGRAM

FIGURE 11: WE# C

ONTROLLED

ECTOR

-E

RASE

IMING

IAGRAM

373 ILL F28.10

ADDRESSES

15-0

WE#

5555

2AAA

5555

XX55

XX50

XX55

XXAA

XX80

XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 13)
BAX = Block Address
X can be V

or V

, but no other value.

RY/BY#

VALID

373 ILL F29.10

ADDRESSES

15-0

WE#

5555

2AAA

5555

XX55

XX30

XX55

XXAA

XX80

XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 13)
SA

= Sector Address

X can be V

or V

, but no other value.

RY/BY#

VALID

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

FIGURE 22: E

RASE

OMMAND

EQUENCE

373 ILL F36.2

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Concurrent SuperFlash
SST36VF1601

S71142-07-000

5/02

373

PRODUCT ORDERING INFORMATION

Valid combinations for SST36VF1601

SST36VF1601-70-4C-EK

SST36VF1601-70-4C-BK

SST36VF1601-70-4E-EK

SST36VF1601-70-4E-BK

Note:

Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

Device

Speed

Suffix1

Suffix2

SST36VF160 1 -

XXX

Package Modifier

K = 48 balls

Package Type

B = TFBGA (8mm x 10mm)
E = TSOP (type 1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

1 = 12 Mbit + 4 Mbit

Device Density

160 = 1M x16

Voltage

V = 2.7-3.6V

Data Sheet

16 Mbit Concurrent SuperFlash

SST36VF1601

S71142-07-000

5/02

373

PACKAGING DIAGRAMS

48-

LEAD

HIN

MALL

UTLINE

ACKAGE

(TSOP) 12

SST P

ACKAGE

ODE

: EK

48-

BALL

HIN

PROFILE

, F

INE

PITCH

ALL

RID

RRAY

(TFBGA) 8

SST P

ACKAGE

ODE

: BK

1.05
0.95

0.70
0.50

18.50
18.30

20.20
19.80

0.70
0.50

12.20
11.80

0.27
0.17

0.15
0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20
max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEW

TOP VIEW

8.00 ± 0.20

0.30 ± 0.05
(48X)

A1 CORNER

10.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-BK-8x10-300mic-13

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

1mm

SIDE VIEW

SEATING PLANE

0.21 ± 0.05

1.10 ± 0.10

0.08

Silicon Storage Technology, Inc. · 1171 Sonora Court · Sunnyvale, CA 94086 · Telephone 408-735-9110 · Fax 408-735-9036

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