9/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

CSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Advance Information

32 Mbit (x8/x16) Concurrent SuperFlash

SST36VF3203 / SST36VF3204

FEATURES:

Organized as 2M x16 or 4M x8

Dual Bank Architecture for Concurrent
Read/Write Operation

32 Mbit Bottom Sector Protection

(in the smaller bank)
- SST36VF3203: 24 Mbit + 8 Mbit

32 Mbit Top Sector Protection

(in the smaller bank)
- SST36VF3204: 8 Mbit + 24 Mbit

Single 2.7-3.6V for Read and Write Operations

Superior Reliability

Endurance: 100,000 cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 6 mA typical
Standby Current: 4 µA typical
Auto Low Power Mode: 4 µA typical

Hardware Sector Protection/WP# Input Pin

Protects 8 KWord in the smaller bank or, top or

bottom bank for 16 Mbit+16 Mbit, by driving WP#
low and unprotects by driving WP# high

Hardware Reset Pin (RST#)

Resets the internal state machine to reading

array data

Byte# Pin

Selects 8-bit or 16-bit mode

Sector-Erase Capability

Uniform 2 KWord sectors

Chip-Erase Capability

Block-Erase Capability

Uniform 32 KWord blocks

Erase-Suspend / Erase-Resume Capabilities

Security ID Feature

SST: 128 bits
User: 256 Bytes

Fast Read Access Time

70 ns

Latched Address and Data

Fast Erase and Program (typical):

Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 35 ms
Program Time: 7 µs

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling
Ready/Busy# pin

CMOS I/O Compatibility

Conforms to Common Flash Memory Interface (CFI)

JEDEC Standards

Flash EEPROM Pinouts and command sets

Packages Available

48-ball TFBGA (6mm x 8mm)
48-lead TSOP (12mm x 20mm)

All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST36VF320x are 2M x16 or 4M x8 CMOS Concur-
rent Read/Write Flash Memory manufactured with SST's
proprietary, high performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches. The devices write (Pro-
gram or Erase) with a 2.7-3.6V power supply and conform
to JEDEC standard pinouts for x8/x16 memories.

Featuring high performance Word-Program, these devices
provide a typical Program time of 7 µsec and use the Tog-
gle Bit, Data# Polling, or RY/BY# to detect the completion
of the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,

and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.

These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.

SST36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.

To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 1 and 2 for pin assignments.

Device Operation

Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.

Auto Low Power Mode

These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the I

active Read current to 4 µA typically.

While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.

Concurrent Read/Write Operation

The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.

Note: For the purposes of this table, write means to perform Block-

or Sector-Erase or Program operations as applicable to the
appropriate bank.

Read Operation

The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 3).

Program Operation

These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.

See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 19 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.

ONCURRENT

EAD

RITE

TATE

Bank 1

Bank 2

Read

No Operation

Read

Write

Read

Write

No Operation

Read

No Operation

Write

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Sector- (Block-) Erase Operation

These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (50H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (30H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 9 and 10 for timing waveforms.

Chip-Erase Operation

The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the "1" state. This is
useful when a device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 7 for the command sequence, Figure 8
for timing diagram, and Figure 22 for the flowchart. When
WP# is low, any attempt to Chip-Erase will be ignored.

Erase-Suspend/Erase-Resume Operations

The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (T

maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ

toggling and

at "1". While in Erase-Suspend mode, a Program

operation is allowed except for the sector or block selected
for Erase-Suspend. The Software ID Entry command can
also be executed. To resume Sector-Erase or Block-Erase
operation which has been suspended, the system must
issue an Erase-Resume command. The operation is exe-
cuted by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the last
byte sequence.

Write Operation Status Detection

These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ

) and Toggle Bit (DQ

). The

End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ

), or Toggle Bit (DQ

) Read may

be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ

or DQ

. In

order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other-
wise the rejection is valid.

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V

via an external pull-up

resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.

Byte/Word (BYTE#)

The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic "1" (V

) the device is in x16 data configuration: all

data I/0 pins DQ

-DQ

are active and controlled by CE#

and OE#.

If the BYTE# pin is at logic "0", the device is in x8 data con-
figuration: only data I/O pins DQ

-DQ

are active and con-

trolled by CE# and OE#. The remaining data pins DQ

are at Hi-Z, while pin DQ

is used as the address

input A

-1

for the Least Significant Bit of the address bus.

Data# Polling (DQ

)

When the devices are in an internal Program operation, any
attempt to read DQ

will produce the complement of the

true data. Once the Program operation is completed, DQ

will produce true data. During internal Erase operation, any
attempt to read DQ

will produce a `0'. Once the internal

Erase operation is completed, DQ

will produce a `1'. The

Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
(DQ

) timing diagram and Figure 20 for a flowchart.

Toggle Bits (DQ

and DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating "1"s

and "0"s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ

bit will

stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ

) is valid after the

rising edge of sixth WE# (or CE#) pulse. DQ

will be set to

"1" if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ

will

toggle.

An additional Toggle Bit is available on DQ

, which can be

used in conjunction with DQ

to check whether a particular

sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ

)

is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 7 for Toggle Bit timing dia-
gram and Figure 20 for a flowchart.

Note: DQ

and DQ

require a valid address when reading

status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.

Data Protection

The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.

TABLE

1: W

RITE

PERATION

TATUS

Status

RY/BY#

Normal
Operation

Standard
Program

DQ7#

Toggle

No Toggle

Standard
Erase

Toggle

Erase-
Suspend
Mode

Read From
Erase
Suspended
Sector/Block

Toggle

Read From
Non-Erase
Suspended
Sector/Block

Data

Program

DQ7#

Toggle

N/A

T1.1 1270

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Hardware Block Protection

The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the smaller bank or, top or
bottom bank for 16 Mbit +16 Mbit. The block is protected
when WP# is held low. When WP# is held low and a Block-
Erase command is issued to the protected black, the data
in the outermost 8 KWord/16 KByte section will be pro-
tected. The rest of the block will be erased. See Tables 3
and 4 for Block-Protection location.

A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least T

RP,

any in-progress operation will terminate and

return to Read mode (see Figure 16) and all output pins
are set to High-Z. When no internal Program/Erase opera-
tion is in progress, a minimum period of T

RHR

is required

after RST# is driven high before a valid Read can take
place (see Figure 15).

The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.

Software Data Protection (SDP)

These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 7 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within T

RC.

The contents of DQ

-DQ

can be V

IH,

but no other value during any SDP command

sequence.

Common Flash Memory Interface (CFI)

These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address
BK

555H in the last byte sequence. In order to enter the

CFI Query mode, the system can also use the one-byte
sequence with BK

55H on Address and 98H on Data Bus.

See Figure 12 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 8
through 10. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Security ID

The SST36VF320x devices offer a 136-word Security ID
space. The Secure ID space is divided into two seg-
ments--one 128-bit factory programmed segment and one
128-word (256-byte) user-programmed segment. The first
segment is programmed and locked at SST with a unique,
128-bit number. The user segment is left un-programmed
for the customer to program as desired. To program the
user segment of the Security ID, the user must use the
Security ID Program command. End-of-Write status is
checked by reading the toggle bits. Data# Polling is not
used for Security ID End-of-Write detection. Once pro-
gramming is complete, the Sec ID should be locked using
the User Sec ID Program Lock-Out. This disables any
future corruption of this space. Note that regardless of
whether or not the Sec ID is locked, neither Sec ID seg-
ment can be erased. The Secure ID space can be queried
by executing a three-byte command sequence with Query
Sec ID command (88H) at address 555H in the last byte
sequence. See Figure 14 for timing diagram. To exit this
mode, the Exit Sec ID command should be executed.
Refer to Table 7 for more details.

Product Identification

The Product Identification mode identifies the devices and
manufacturer. For details, see Table 2 for software opera-
tion, Figure 11 for the Software ID Entry and Read timing
diagram and Figure 21 for the Software ID Entry command
sequence flowchart. The addresses A

and A

indicate a

bank address. When the addressed bank is switched to
Product Identification mode, it is possible to read another

address from the same bank without issuing a new Soft-
ware ID Entry command. The Software ID Entry command
may be written to an address within a bank that is in Read
Mode or in Erase-Suspend mode. The Software ID Entry
command may not be written while the device is program-
ming or erasing in the other bank.

Note: BK

= Bank Address (A

-A

)

Product Identification Mode
Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar-
ently causes the device to behave abnormally, e.g., not read
correctly. Please note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 7 for the software command code, Fig-
ure 13 for timing waveform and Figure 21 for a flowchart.

TABLE

2: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

00BFH

Device ID

SST36VF3203

0001H

7354H

SST36VF3204

0001H

7353H

T2.1 1270

1270 B01.0

SuperFlash Memory

Bank 1

I/O Buffers

SuperFlash Memory

Bank 2

Memory
Address

-1

- DQ

CE#

WP#

WE#

OE#

Control

Logic

RST#

BYTE#

RY/BY#

Address

Buffers

(8 KWord / 16 KByte

Sector Protection)

UNCTIONAL

LOCK

IAGRAM

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE

3: SST36VF3203, 2M

16 CSF B

OTTOM

UAL

-B

ANK

EMORY

RGANIZATION

SST36VF3203

Block

Block Size

Address Range x8

Address Range x16

Bank 1

BA0

8 KW / 16 KB

000000H003FFFH

000000H001FFFH

24 KW / 48 KB

004000H00FFFFH

002000H007FFFH

BA1

32 KW / 64 KB

010000H01FFFFH

008000H00FFFFH

BA2

32 KW / 64 KB

020000H02FFFFH

010000H017FFFH

BA3

32 KW / 64 KB

030000H03FFFFH

018000H01FFFFH

BA4

32 KW / 64 KB

040000H04FFFFH

020000H027FFFH

BA5

32 KW / 64 KB

050000H05FFFFH

028000H02FFFFH

BA6

32 KW / 64 KB

060000H--06FFFFH

030000H037FFFH

BA7

32 KW / 64 KB

070000H--07FFFFH

038000H03FFFFH

BA8

32 KW / 64 KB

080000H--08FFFFH

040000H047FFFH

BA9

32 KW / 64 KB

090000H--09FFFFH

048000H04FFFFH

BA10

32 KW / 64 KB

0A0000H--0AFFFFH

050000H057FFFH

BA11

32 KW / 64 KB

0B0000H--0BFFFFH

058000H05FFFFH

BA12

32 KW / 64 KB

0C0000H--0CFFFFH

060000H067FFFH

BA13

32 KW / 64 KB

0D0000H--0DFFFFH

068000H06FFFFH

BA14

32 KW / 64 KB

0E0000H--0EFFFFH

070000H077FFFH

BA15

32 KW / 64 KB

0F0000H--0FFFFFH

078000H07FFFFH

Bank 2

BA16

32 KW / 64 KB

100000H--10FFFFH

080000H087FFFH

BA17

32 KW / 64 KB

110000H--11FFFFH

088000H08FFFFH

BA18

32 KW / 64 KB

120000H--12FFFFH

090000H097FFFH

BA19

32 KW / 64 KB

130000H--13FFFFH

098000H09FFFFH

BA20

32 KW / 64 KB

140000H--14FFFFH

0A0000H0A7FFFH

BA21

32 KW / 64 KB

150000H--15FFFFH

0A8000H0AFFFFH

BA22

32 KW / 64 KB

160000H--16FFFFH

0B0000H0B7FFFH

BA23

32 KW / 64 KB

170000H--17FFFFH

0B8000H0BFFFFH

BA24

32 KW / 64 KB

180000H--18FFFFH

0C0000H0C7FFFH

BA25

32 KW / 64 KB

190000H--19FFFFH

0C8000H0CFFFFH

BA26

32 KW / 64 KB

1A0000H--1AFFFFH

0D0000H0D7FFFH

BA27

32 KW / 64 KB

1B0000H--1BFFFFH

0D8000H0DFFFFH

BA28

32 KW / 64 KB

1C0000H--1CFFFFH

0E0000H--0E7FFFH

BA29

32 KW / 64 KB

1D0000H--1DFFFFH

0E8000H--0EFFFFH

BA30

32 KW / 64 KB

1E0000H--1EFFFFH

0F0000H--0F7FFFH

BA31

32 KW / 64 KB

1F0000H--1FFFFFH

0F8000H--0FFFFFH

BA32

32 KW / 64 KB

200000H--20FFFFH

100000H--107FFFH

BA33

32 KW / 64 KB

210000H--21FFFFH

108000H--10FFFFH

BA34

32 KW / 64 KB

220000H--22FFFFH

110000H--117FFFH

BA35

32 KW / 64 KB

230000H--23FFFFH

118000H--11FFFFH

BA36

32 KW / 64 KB

240000H--24FFFFH

120000H--127FFFH

BA37

32 KW / 64 KB

250000H--25FFFFH

128000H--12FFFFH

BA38

32 KW / 64 KB

260000H--26FFFFH

130000H--137FFFH

BA39

32 KW / 64 KB

270000H--27FFFFH

138000H--13FFFFH

BA40

32 KW / 64 KB

280000H--28FFFFH

140000H--147FFFH

BA41

32 KW / 64 KB

290000H--29FFFFH

148000H--14FFFFH

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Bank 2

BA42

32 KW / 64 KB

2A0000H--2AFFFFH

150000H--157FFFH

BA43

32 KW / 64 KB

2B0000H2BFFFFH

158000H15FFFFH

BA44

32 KW / 64 KB

2C0000H2CFFFFH

160000H167FFFH

BA45

32 KW / 64 KB

2D0000H2DFFFFH

168000H16FFFFH

BA46

32 KW / 64 KB

2E0000H2EFFFFH

170000H177FFFH

BA47

32 KW / 64 KB

2F0000H2FFFFFH

178000H17FFFFH

BA48

32 KW / 64 KB

300000H30FFFFH

180000H187FFFH

BA49

32 KW / 64 KB

310000H31FFFFH

188000H18FFFFH

BA50

32 KW / 64 KB

320000H32FFFFH

190000H197FFFH

BA51

32 KW / 64 KB

330000H33FFFFH

198000H19FFFFH

BA52

32 KW / 64 KB

340000H34FFFFH

1A0000H1A7FFFH

BA53

32 KW / 64 KB

350000H35FFFFH

1A8000H1AFFFFH

BA54

32 KW / 64 KB

360000H36FFFFH

1B0000H1B7FFFH

BA55

32 KW / 64 KB

370000H37FFFFH

1B8000H1BFFFFH

BA56

32 KW / 64 KB

380000H38FFFFH

1C0000H1C7FFFH

BA57

32 KW / 64 KB

390000H39FFFFH

1C8000H1CFFFFH

BA58

32 KW / 64 KB

3A0000H3AFFFFH

1D0000H1D7FFFH

BA59

32 KW / 64 KB

3B0000H3BFFFFH

1D8000H1DFFFFH

BA60

32 KW / 64 KB

3C0000H3CFFFFH

1E0000H1E7FFFH

BA61

32 KW / 64 KB

3D0000H3DFFFFH

1E8000H1EFFFFH

BA62

32 KW / 64 KB

3E0000H3EFFFFH

1F0000H1F7FFFH

BA63

32 KW / 64 KB

3F0000H3FFFFFH

1F8000H1FFFFFH

T3.0 1270

TABLE

3: SST36VF3203, 2M

16 CSF B

OTTOM

UAL

-B

ANK

EMORY

RGANIZATION

ONTINUED

) (2

SST36VF3203

Block

Block Size

Address Range x8

Address Range x16

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE

4: SST36VF3204, 2M

16 CSF T

UAL

-B

ANK

EMORY

RGANIZATION

SST36VF3204

Block

Block Size

Address Range x8

Address Range x16

Bank 2

BA0

32 KW / 64 KB

000000H00FFFFH

000000H007FFFH

BA1

32 KW / 64 KB

010000H01FFFFH

008000H00FFFFH

BA2

32 KW / 64 KB

020000H02FFFFH

010000H017FFFH

BA3

32 KW / 64 KB

030000H03FFFFH

018000H01FFFFH

BA4

32 KW / 64 KB

040000H04FFFFH

020000H027FFFH

BA5

32 KW / 64 KB

050000H05FFFFH

028000H02FFFFH

BA6

32 KW / 64 KB

060000H--06FFFFH

030000H037FFFH

BA7

32 KW / 64 KB

070000H--07FFFFH

038000H03FFFFH

BA8

32 KW / 64 KB

080000H--08FFFFH

040000H047FFFH

BA9

32 KW / 64 KB

090000H--09FFFFH

048000H04FFFFH

BA10

32 KW / 64 KB

0A0000H--0AFFFFH

050000H057FFFH

BA11

32 KW / 64 KB

0B0000H--0BFFFFH

058000H05FFFFH

BA12

32 KW / 64 KB

0C0000H--0CFFFFH

060000H067FFFH

BA13

32 KW / 64 KB

0D0000H--0DFFFFH

068000H06FFFFH

BA14

32 KW / 64 KB

0E0000H--0EFFFFH

070000H077FFFH

BA15

32 KW / 64 KB

0F0000H--0FFFFFH

078000H07FFFFH

BA16

32 KW / 64 KB

100000H--10FFFFH

080000H087FFFH

BA17

32 KW / 64 KB

110000H--11FFFFH

088000H08FFFFH

BA18

32 KW / 64 KB

120000H--12FFFFH

090000H097FFFH

BA19

32 KW / 64 KB

130000H--13FFFFH

098000H09FFFFH

BA20

32 KW / 64 KB

140000H--14FFFFH

0A0000H0A7FFFH

BA21

32 KW / 64 KB

150000H--15FFFFH

0A8000H0AFFFFH

BA22

32 KW / 64 KB

160000H--16FFFFH

0B0000H0B7FFFH

BA23

32 KW / 64 KB

170000H--17FFFFH

0B8000H0BFFFFH

BA24

32 KW / 64 KB

180000H--18FFFFH

0C0000H0C7FFFH

BA25

32 KW / 64 KB

190000H--19FFFFH

0C8000H0CFFFFH

BA26

32 KW / 64 KB

1A0000H--1AFFFFH

0D0000H0D7FFFH

BA27

32 KW / 64 KB

1B0000H--1BFFFFH

0D8000H0DFFFFH

BA28

32 KW / 64 KB

1C0000H--1CFFFFH

0E0000H0E7FFFH

BA29

32 KW / 64 KB

1D0000H--1DFFFFH

0E8000H0EFFFFH

BA30

32 KW / 64 KB

1E0000H--1EFFFFH

0F0000H0F7FFFH

BA31

32 KW / 64 KB

1F0000H--1FFFFFH

0F8000H0FFFFFH

BA32

32 KW / 64 KB

200000H--20FFFFH

100000H107FFFH

BA33

32 KW / 64 KB

210000H--21FFFFH

108000H10FFFFH

BA34

32 KW / 64 KB

220000H--22FFFFH

110000H117FFFH

BA35

32 KW / 64 KB

230000H--23FFFFH

118000H11FFFFH

BA36

32 KW / 64 KB

240000H--24FFFFH

120000H127FFFH

BA37

32 KW / 64 KB

250000H--25FFFFH

128000H12FFFFH

BA38

32 KW / 64 KB

260000H--26FFFFH

130000H137FFFH

BA39

32 KW / 64 KB

270000H--27FFFFH

138000H13FFFFH

BA40

32 KW / 64 KB

280000H--28FFFFH

140000H147FFFH

BA41

32 KW / 64 KB

290000H--29FFFFH

148000H14FFFFH

BA42

32 KW / 64 KB

2A0000H--2AFFFFH

150000H157FFFH

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Bank 2

BA43

32 KW / 64 KB

2B0000H2BFFFFH

158000H15FFFFH

BA44

32 KW / 64 KB

2C0000H2CFFFFH

160000H167FFFH

BA45

32 KW / 64 KB

2D0000H2DFFFFH

168000H16FFFFH

BA46

32 KW / 64 KB

2E0000H2EFFFFH

170000H177FFFH

BA47

32 KW / 64 KB

2F0000H2FFFFFH

178000H17FFFFH

Bank 1

BA48

32 KW / 64 KB

300000H30FFFFH

180000H187FFFH

BA49

32 KW / 64 KB

310000H31FFFFH

188000H18FFFFH

BA50

32 KW / 64 KB

320000H32FFFFH

190000H197FFFH

BA51

32 KW / 64 KB

330000H33FFFFH

198000H19FFFFH

BA52

32 KW / 64 KB

340000H34FFFFH

1A0000H1A7FFFH

BA53

32 KW / 64 KB

350000H35FFFFH

1A8000H1AFFFFH

BA54

32 KW / 64 KB

360000H36FFFFH

1B0000H1B7FFFH

BA55

32 KW / 64 KB

370000H37FFFFH

1B8000H1BFFFFH

BA56

32 KW / 64 KB

380000H38FFFFH

1C0000H1C7FFFH

BA57

32 KW / 64 KB

390000H39FFFFH

1C8000H1CFFFFH

BA58

32 KW / 64 KB

3A0000H3AFFFFH

1D0000H1D7FFFH

BA59

32 KW / 64 KB

3B0000H3BFFFFH

1D8000H1DFFFFH

BA60

32 KW / 64 KB

3C0000H3CFFFFH

1E0000H1E7FFFH

BA61

32 KW / 64 KB

3D0000H3DFFFFH

1E8000H1EFFFFH

BA62

32 KW / 64 KB

3E0000H3EFFFFH

1F0000H1F7FFFH

BA63

24 KW / 48 KB

3F0000H3FBFFFH

1F8000H1FDFFFH

8 KW / 16 KB

3FC000H3FFFFFH

1FE000H1FFFFFH

T4.0 1270

TABLE

4: SST36VF3204, 2M

16 CSF T

UAL

-B

ANK

EMORY

RGANIZATION

ONTINUED

) (2

SST36VF3204

Block

Block Size

Address Range x8

Address Range x16

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

FIGURE 1: P

SSIGNMENTS

FOR

48-

BALL

TFBGA (6

)

FIGURE 2: P

SSIGNMENTS

FOR

48-

LEAD

TSOP (12

)

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A20

A16

DQ7

DQ5

DQ2

DQ0

BYTE#

DQ14

DQ12

DQ10

DQ8

CE#

NOTE*

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1270 48-tfbga P1.0

TOP VIEW (balls facing down)

A B C D E F G H

Note* = DQ

-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1270 48-tsop P02.0

Standard Pinout

Top View

Die Up

A15
A14
A13
A12
A11
A10

A9
A8

A19
A20

WE#

RST#

WP#

RY/BY#

A18
A17

A7
A6
A5
A4
A3
A2
A1

A16
BYTE#
VSS
DQ15/A

-1

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE

5: P

ESCRIPTION

Symbol

Name

Functions

-A

Address Inputs

To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A

-A

address lines will select the sector. During Block-Erase A

-A

address

lines will select the block.

-DQ

Data Input/Output

To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.

-1

Data Input/Output
and LBS Address

is used as data I/O pin when in x16 mode (BYTE# = "1")

-1

is used as the LSB address pin when in x8 mode (BYTE# = "0")

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers

WE#

Write Enable

To control the Write operations

RST#

Hardware Reset

To reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K

- 100K

pull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

WP#

Write Protect

To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.

BYTE#

Word/Byte Configuration To select 8-bit or 16-bit mode.

Power Supply

To provide 2.7-3.6V power supply voltage

Ground

No Connection

Unconnected pins

T5.0 1270

TABLE

6: O

PERATION

ODES

ELECTION

Mode

CE#

OE#

WE#

RST#

-DQ

Address

BYTE# = V

Read

OUT

-DQ

= High Z

Program

= A

-1

Erase

1. X can be V

or V

, but no other value.

High Z

Sector or Block

address,
555H for

Chip-Erase

Standby V

IHC

High Z

Write Inhibit

High Z / D

OUT

High Z / D

OUT

High Z

High Z / D

OUT

High Z / D

OUT

High Z

Product
Identification

Software
Mode

Manufacturer's ID

(BFH)

Manufacturer's ID

(00H)

High Z

See Table 7

Device ID

2. Device ID =

SST36VF3203 = 7354H, SST36VF3204 = 7353H

Device ID

High Z

Reset

High Z

T6.1 1270

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE

7: S

OFTWARE

OMMAND

EQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word-Program

555H

AAH

2AAH

55H

555H

A0H

Data

Sector-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

50H

Block-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

30H

Chip-Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

Erase-Suspend

XXXH

B0H

Erase-Resume

XXXH

30H

Query Sec ID

555H

AAH

2AAH

55H

555H

88H

User Security ID
Word-Program

555H

AAH

2AAH

55H

555H

A5H

SIWA

Data

User Security ID
Program Lock-out

555H

AAH

2AAH

55H

555H

85H

XXXH

0000H

Software ID Entry

8,9

555H

AAH

2AAH

55H

555H

90H

CFI Query Entry

555H

AAH

2AAH

55H

555H

98H

CFI Query Entry

55H

98H

Software ID Exit/
CFI Exit/
Sec ID Exit

10,11

555H

AAH

2AAH

55H

555H

F0H

Software ID Exit/
CFI Exit/
Sec ID Exit

10,11

XXH

F0H

T7.1 1270

1. Address format A

-A

(Hex), Addresses A

-A

can be V

or V

, but no other value (unless otherwise stated), for the command

sequence when in x16 mode.
When in x8 mode, Addresses A

-A

12,

Address A

-1,

and

-DQ

can be V

or V

, but no other value (unless otherwise stated), for

the command sequence.

2. DQ

-DQ

can be V

or V

, but no other value, for the command sequence

3. WA = Program word address
4. SA

for Sector-Erase; uses A

-A

address lines

for Block-Erase; uses A

-A

address lines

for Bank Address; uses A

-A

address lines

5. For SST36VF3203 the Security ID Address Range is: (x16 mode) = 100000H to 100087H,(x8 mode) = 100000H to 10010FH

SST ID is read at Address Range(x16 mode) = 100000H to 100007H

(x8 mode) = 100000H to 10000FH

User ID is read at Address Range(x16 mode) = 100008H to 100087H

(x8 mode) = 100010H to 10010FH

Lock status is read at Address 1000FFH (x16) or 1001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For SST36VF3204 the Security ID Address Range is:(x16 mode) = 000000H to 000087H,

(x8 mode) = 000000H to 00010FH

SST ID is read at Address Range

(x16 mode) = 000000H to 000007H

(x8 mode) = 000000H to 00000FH

User ID is read at Address Range

(x16 mode) = 000008H to 000087H

(x8 mode) = 000010H to 00010FH

Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0

6. SIWA = Valid Word addresses for user Sec ID

For SST36VF3203 User ID valid Address Range is

(x16 mode) = 100008H-100087H

(x8 mode) = 100010H-10010FH.

For SST36VF3204 User ID valid Address Range is

(x16 mode) = 000008H-000087H

(x8 mode) = 000010H-00010FH.

All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.

7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=V

8. The device does not remain in Software Product Identification mode if powered down.
9. A

20,

19,

and A

= BK

(Bank Address): address of the bank that is switched to Software ID/CFI Mode

With A

-A

= 0;SST Manufacturer's ID = 00BFH, is read with A

= 0

SST36VF3203 Device ID = 7354H, is read with A

= 1

SST36VF3204 Device ID = 7353H, is read with A

= 1

10. Both Software ID Exit operations are equivalent
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

User Sec ID mode again (the programmed "0" bits cannot be reversed to "1").

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE

8: CFI Q

UERY

DENTIFICATION

TRING1

Address

x16 Mode

Address
x8 Mode

Data

Description

10H

20H

0051H

Query Unique ASCII string "QRY"

11H

22H

0052H

12H

24H

0059H

13H

26H

0002H

Primary OEM command set

14H

28H

0000H

15H

2AH

0000H

Address for Primary Extended Table

16H

2CH

0000H

17H

2EH

0000H

Alternate OEM command set (00H = none exists)

18H

30H

0000H

19H

32H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

34H

0000H

T8.1 1270

1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.

TABLE

9: S

YSTEM

NTERFACE

NFORMATION

Address

x16 Mode

Address
x8 Mode

Data

1. In x8 mode, only the lower byte of data is output.

Description

1BH

36H

0027H

Min (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1CH

38H

0036H

Max (Program/Erase)

-DQ

: Volts, DQ

-DQ

: 100 millivolts

1DH

3AH

0000H

min (00H = no V

pin)

1EH

3CH

0000H

max (00H = no V

pin)

1FH

3EH

0004H

Typical time out for Program 2

µs (2

= 16 µs)

20H

40H

0000H

Typical time out for min size buffer program 2

µs (00H = not supported)

21H

42H

0004H

Typical time out for individual Sector/Block-Erase 2

ms (2

= 16 ms)

22H

44H

0006H

Typical time out for Chip-Erase 2

ms (2

= 64 ms)

23H

46H

0001H

Maximum time out for Program 2

times typical (2

x 2

= 32 µs)

24H

48H

0000H

Maximum time out for buffer program 2

times typical

25H

4AH

0001H

Maximum time out for individual Sector-/Block-Erase 2

times typical (2

x 2

= 32 ms)

26H

4CH

0001H

Maximum time out for Chip-Erase 2

times typical (2

x 2

= 128 ms)

T9.0 1270

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE 10: D

EVICE

EOMETRY

NFORMATION

Address

x16 Mode

Address
x8 Mode

Data

Description

27H

4EH

0016H

Device size = 2

Bytes (16H = 22; 2

= 4 MByte)

28H

50H

0002H

Flash Device Interface description; 0002H = x8/x16 asynchronous interface

29H

52H

0000H

2AH

54H

0000H

Maximum number of bytes in multi-byte write = 2

(00H = not supported)

2BH

56H

0000H

2CH

58H

0002H

Number of Erase Sector/Block sizes supported by device

2DH

5AH

003FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

2EH

5CH

0000H

y = 63 + 1 = 64 blocks (003FH = 63)

2FH

5EH

0000H

30H

60H

0001H

z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

31H

62H

00FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

32H

64H

0003H

y = 1023 + 1 = 1024 sectors (03FFH = 1023)

33H

66H

0010H

34H

68H

0000H

z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

T10.2 1270

1. In x8 mode, only the lower byte of data is output.

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to V

+2.0V

Package Power Dissipation Capability (T

= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260

C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240

C for 10 seconds; please consult the factory for the latest information.

PERATING

ANGE

Range

Ambient Temp

Extended

-20°C to +85°C

2.7-3.6V

Industrial

-40°C to +85°C

2.7-3.6V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C

= 30 pF

See Figures 17 and 18

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE 11: DC O

PERATING

HARACTERISTICS

= 2.7-3.6V

Symbol

Parameter

Limits

Test Conditions

Freq

Min

Max

Units

Active V

Current

Read

5 MHz

CE#=V

IL,

WE#=OE#=V

1 MHz

Program and Erase

CE#=WE#=V

, OE#=V

Concurrent Read/Write

5 MHz

CE#=V

IL,

OE#=V

1 MHz

Standby V

Current

µA

CE#, RST#=V

±0.3V

ALP

Auto Low Power V

Current

µA

CE#=0.1V, V

Max

WE#=V

-0.1V

Address inputs=0.1V or V

-0.1V

Reset V

Current

µA

RST#=GND

Input Leakage Current

µA

=GND to V

, V

Max

LIW

Input Leakage Current
on WP# pin and RST# pin

µA

WP#=GND to V

, V

Max

RST#=GND to V

, V

Max

Output Leakage Current

µA

OUT

=GND to V

, V

Max

Input Low Voltage

0.8

Min

ILC

Input Low Voltage (CMOS)

0.3

Max

Input High Voltage

0.7 V

+0.3

Max

IHC

Input High Voltage (CMOS)

-0.3

+0.3

Max

Output Low Voltage

0.2

=100 µA, V

Min

Output High Voltage

-0.2

=-100 µA, V

Min

T11.1 1270

1. Address input = V

ILT

IHT,

Max (See Figure 17)

TABLE 12: R

ECOMMENDED

YSTEM

OWER

IMINGS

Symbol

Parameter

Minimum

Units

PU-READ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation

100

µs

PU-WRITE

Power-up to Write Operation

100

µs

T12.0 1270

TABLE 13: C

APACITANCE

= 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

I/O

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance

I/O

= 0V

10 pF

Input Capacitance

= 0V

10 pF

T13.0 1270

TABLE 14: R

ELIABILITY

HARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

END

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance

10,000

Cycles

JEDEC Standard A117

Data Retention

100

Years

JEDEC Standard A103

LTH

Latch Up

100 + I

JEDEC Standard 78

T14.0 1270

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

AC CHARACTERISTICS

TABLE 15: R

EAD

YCLE

IMING

ARAMETERS

= 2.7-3.6V

Symbol

Parameter

Min

Max

Units

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

CLZ

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output

OLZ

OE# Low to Active Output

CHZ

CE# High to High-Z Output

OHZ

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

500

RHR

RST# High before Read

1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode

µs

T15.1 1270

TABLE 16: P

ROGRAM

RASE

YCLE

IMING

ARAMETERS

Symbol

Parameter

Min

Max

Units

Program Time

µs

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OES

OE# High Setup Time

OEH

OE# High Hold Time

CE# Pulse Width

WE# Pulse Width

WPH

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High

CPH

CE# Pulse Width High

Data Setup Time

Data Hold Time

IDA

Software ID Access and Exit Time

150

Sector-Erase

Block-Erase

SCE

Chip-Erase

Erase-Suspend Latency

µs

1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RY/BY# Delay Time

Bus Recovery Time

µs

T16.1 1270

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

FIGURE 9: WE# C

ONTROLLED

LOCK

-E

RASE

IMING

IAGRAM

FIGURE 10: WE# C

ONTROLLED

ECTOR

-E

RASE

IMING

IAGRAM

1270 F09.0

ADDRESSES

15-0

WE#

555

2AA

555

XX55

XX30

XX55

XXAA

XX80

XXAA

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 16)

BAX = Block Address

X can be VIL or VIH, but no other value.

RY/BY#

VALID

1270 F10.0

ADDRESSES

15-0

WE#

555

2AA

555

XX55

XX50

XX55

XXAA

XX80

XXAA

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#

signals are interchageable as long as minimum timings are met. (See Table 16)

= Sector Address

X can be V

or V

IH,

but no other value.

RY/BY#

VALID

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

FIGURE 13: S

OFTWARE

ID E

XIT

/CFI E

XIT

FIGURE 14: S

ID E

NTRY

1270 F13.0

ADDRESSES

15-0

IDA

WPH

WE#

555

2AA

555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA

XX55

XXF0

Note: X can be V

or V

, but no other value.

1270 F14.0

ADDRESS AMS-0

TIDA

DQ15-0

WE#

SW0

SW1

SW2

555

2AA

555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH

TAA

XX55

XXAA

XX88

Note: A

= Most significant address

= A

for SST39VF3203/3204

WP# must be held in proper logic state (V

or V

) 1 µs prior to and 1 µs after the command sequence

X can be V

or V

, but no other value.

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

FIGURE 21: S

OFTWARE

RODUCT

ID/CFI/S

ID E

NTRY

OMMAND

LOWCHARTS

1270 F20.0

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Software ID Exit/

CFI Exit/Sec ID

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Wait TIDA

Return to normal

operation

X can be V

or V

IH,

but no other value

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

FIGURE 22: E

RASE

OMMAND

EQUENCE

1270 F22.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait T

SCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SA

Load data: XXAAH

Address: 555H

Wait T

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BA

Load data: XXAAH

Address: 555H

Wait T

Block erased

to FFFFH

Note: X can be V

or V

IH,

but no other value.

Advance Information

32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204

S71270-01-000

9/05

PRODUCT ORDERING INFORMATION

Valid combinations for SST36VF3203

SST36VF3203-70-4E-B3KE

SST36VF3203-70-4E-EKE

SST36VF3203-70-4I-B3KE

SST36VF3203-70-4I-EKE

Valid combinations for SST36VF3204

SST36VF3204-70-4E-B3KE

SST36VF3204-70-4E-EKE

SST36VF3204-70-4I-B3KE

SST36VF3204-70-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

= non-Pb

Package Modifier

K = 48 balls or leads

Package Type

B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)

Temperature Range

E = Extended = -20°C to +85°C
I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Bank Split

3 = Bottom 24 Mbit + 8 Mbit
4 = Top 8 Mbit + 24 Mbit

Device Density

320 = 1 Mbit x16 or

2 Mbit x8

Voltage

V = 2.7-3.6V

Product Series

36 = Concurrent SuperFlash

1. Environmental suffix "E" denotes non-Pb solder.

SST non-Pb solder devices are "RoHS Compliant".

SST

320x -

B3K

XXXX - XXX

- XXX

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

PACKAGING DIAGRAMS

48-

BALL

HIN

PROFILE

, F

INE

PITCH

ALL

RID

RRAY

(TFBGA) 6

SST P

ACKAGE

ODE

: B3K

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEW

TOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05
(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note:

1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

Advance Information

32 Mbit Concurrent SuperFlash

SST36VF3203 / SST36VF3204

S71270-01-000

9/05

TABLE 17: R

EVISION

ISTORY

Number

Description

Date

Initial release of data sheet

Feb 2005

Updated "Erase-Suspend/Erase-Resume Operations" on page 3

Updated footnote 5 and added footnote 7 to Table 7 on page 13

Updated CFI Query Identification in Table 8 on page 14

Updated Device Geometry Information in Table 10 on page 15

Updated T

parameter from 20 µs to 10 µs in Table 16 on page 18

In "Product Ordering Information" on page 31

Removed all MPNs for packages containing Pb (B3K/EK)
Removed all commercial temperature MPNs
Added extended temperature MPNs for all devices

Sep 2005

Silicon Storage Technology, Inc. · 1171 Sonora Court · Sunnyvale, CA 94086 · Telephone 408-735-9110 · Fax 408-735-9036

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