5/01

397

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MTP is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)

Many-Time Programmable Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

FEATURES:

Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

2.7-3.6V Read Operation

Superior Reliability

Endurance: At least 1000 Cycles
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 10 mA (typical)
Standby Current: 2 µA (typical)

Fast Read Access Time:

70 ns
90 ns

Latched Address and Data

Fast Byte-Program Operation:

Byte-Program Time: 10 µs (typical)
Chip Program Time:

0.6 seconds (typical) for SST37VF512
1.2 seconds (typical) for SST37VF010
2.4 seconds (typical) for SST37VF020
4.8 seconds (typical) for SST37VF040

Electrical Erase Using Programmer

Does not require UV source
Chip-Erase Time: 100 ms (typical)

CMOS I/O Compatibility

JEDEC Standard Byte-wide Flash
EEPROM Pinouts

Packages Available

32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP

PRODUCT DESCRIPTION

The SST37VF512/010/020/040 devices are 64K x8 / 128K
x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable
(MTP), low cost flash, manufactured with SST's proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST37VF512/010/020/040 can
be electrically erased and programmed at least 1000 times
using an external programmer, e.g., to change the contents
of devices in inventory. The SST37VF512/010/020/040
have to be erased prior to programming. These devices
conform to JEDEC standard pinouts for byte-wide flash
memories.

Featuring high performance Byte-Program, the
SST37VF512/010/020/040 provide a typical Byte-Pro-
gram time of 10 µs. Designed, manufactured, and tested
for a wide spectrum of applications, these devices are
offered with an endurance of at least 1000 cycles. Data
retention is rated at greater than 100 years.

The SST37VF512/010/020/040 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.

To meet surface mount and conventional through hole
requirements, the SST37VF512/010/020/040 are offered in
32-pin PLCC, TSOP, and PDIP packages. See Figures 1,
2, and 3 for pinouts.

Device Operation

The SST37VF512/010/020/040 devices are nonvolatile
memory solutions that can be used instead of standard
flash devices if in-system programmability is not required. It
is functionally (Read) and pin compatible with industry
standard flash products.The device supports electrical
Erase operation via an external programmer.

Read

The Read operation of the SST37VF512/010/020/040 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (T

). Data is available at the

output after a delay of TOE from the falling edge of OE#,
assuming the CE# pin has been low and the addresses
have been stable for at least T

- T

. When the CE# pin

is high, the chip is deselected and a standby current of only
10 µA (typical) is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is V

Refer to Figure 4 for the timing diagram.

SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

S71151-02-000

5/01

397

Byte-Program Operation

The SST37VF512/010/020/040 are programmed by using
an external programmer. The programming mode is acti-
vated by asserting 12V (±5%) on OE# pin and V

on CE#

pin. The device is programmed using a single pulse (WE#
pin low) of 10 µs per byte. Using the MTP programming
algorithm, the Byte-Program process continues byte-by-
byte until the entire chip has been programmed. Refer to
Figure 10 for the flowchart and Figure 6 for the timing dia-
gram.

Chip-Erase Operation

The only way to change a data from a "0" to "1" is by electri-
cal erase that changes every bit in the device to "1". The
SST37VF512/010/020/040 use an electrical Chip-Erase
operation. The entire chip can be erased in 100 ms (WE#
pin low). In order to activate erase mode, the 12V (±5%) is
applied to OE# and A

pins while CE# is low. All other

address and data pins are "don't care". The falling edge of
WE# will start the Chip-Erase operation. Once the chip has
been erased, all bytes must be verified for FFH. Refer to Fig-
ure 9 for the flowchart and Figure 5 for the timing diagram.

Product Identification Mode

The Product Identification mode identifies the devices as
SST37VF512, SST37VF010, SST37VF020, and
SST37VF040 and manufacturer as SST. This mode may
be accessed by the hardware method. To activate this
mode, the programming equipment must force V

(12V±5%) on address A

. Two identifier bytes may then be

sequenced from the device outputs by toggling address
line A

. For details, see Table 3 for hardware operation.

Design Considerations

The SST37VF512/010/020/040 should have a 0.1µF
ceramic high frequency, low inductance capacitor con-
nected between V

and GND. This capacitor should be

placed as close to the package terminals as possible.

OE# and A

must remain stable at V

for the entire dura-

tion of an Erase operation. OE# must remain stable at V

for the entire duration of the Program operation.

TABLE

1: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

BFH

Device ID

SST37VF512

0001H

C4H

SST37VF010

0001H

C5H

SST37VF020

0001H

C6H

SST37VF040

0001H

C2H

T1.2 397

Y-Decoder

I/O Buffers

397 ILL B1.1

Address Buffer

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

UNCTIONAL

LOCK

IAGRAM

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

S71151-02-000

5/01

397

FIGURE 1: P

SSIGNMENTS

FOR

32-

PIN

PLCC

FIGURE 2: P

SSIGNMENTS

FOR

32-

PIN

TSOP (8

)

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

WE#

A12

A15

A16

WE#

A12

A15

A16

WE#

A17

A12

A15

A16

A18

WE#

A17

32-pin PLCC

Top View

397 ILL F02a.2

14 15 16 17 18 19 20

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

SST37VF512 SST37VF010 SST37VF020 SST37VF040

SST37VF040 SST37VF020 SST37VF010 SST37VF512

SST37VF512 SST37VF010 SST37VF020 SST37VF040

SST37VF040 SST37VF020 SST37VF010 SST37VF512

A11

A9
A8

A13
A14

WE#

VDD

NC
NC

A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

397 ILL F01.0

Standard Pinout

Top View

A11

A9
A8

A13
A14

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14
A17

WE#

VDD

A18
A16
A15
A12

A7
A6
A5
A4

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

SST37VF040 SST37VF020 SST37VF010 SST37VF512

SST37VF512 SST37VF010 SST37VF020 SST37VF040

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

S71151-02-000

5/01

397

FIGURE 3: P

SSIGNMENTS

FOR

32-

PIN

PDIP

TABLE

2: P

ESCRIPTION

Symbol

Pin Name

Functions

-A

1. A

= Most significant address

= A

for SST37VF512, A

for SST37VF010, A

for SST37VF020, and A

for SST37VF040

Address Inputs

To provide memory addresses.

-DQ

Data Input/output

To output data during Read cycles and receive input data during Program cycles.
The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

WE#

Write Enable

To program or erase (WE# = V

pulse during Program or Erase)

OE#

Output Enable

To gate the data output buffers during Read operation when low

Power Supply

To provide 3.0V supply (2.7-3.6V)

Ground

No Connection

Unconnected pins.

T2.1 397

32-pin

PDIP

Top View

A15

A12

DQ0

DQ1

DQ2

VSS

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

SST37VF512 SST37VF010 SST37VF020 SST37VF040

SST37VF040 SST37VF020 SST37VF010 SST37VF512

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

397 ILL F02b.1

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

S71151-02-000

5/01

397

Note: X = V

or V

(or V

in case of OE# and A

)

= 12V±5%

TABLE

3: O

PERATION

ODES

ELECTION

Mode

CE#

WE#

OE#

Address

Read

OUT

Output Disable

High Z

Standby

High Z

Chip-Erase

High Z

Byte-Program

Program/Erase Inhibit

High Z

or V

High Z/ D

OUT

Product Identification

Manufacturer's ID (BFH)
Device ID

- A

= V

, A

= V

- A

= V

, A

= V

T3.1 397

1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040
2. A

= Most significant address

= A

for SST37VF512, A

for SST37VF010, A

for SST37VF020, and A

for SST37VF040

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V

+ 1.0V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

PERATING

ANGE

Range

Ambient Temp

Commercial

0°C to +70°C

2.7-3.6V

AC C

ONDITIONS

EST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

= 100 pF

See Figures 7 and 8

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SST37VF512-90-3C-WH

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SST37VF512-90-3C-WH