2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
FlashBank is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
FEATURES:
Single 2.7-3.6V Read and Write Operations
Separate Memory Banks for Code or Data
Simultaneous Read and Write Capability
Superior Reliability
Endurance:
E
2
bank - 500,000 Cycles (typical)
Flash bank - 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption
Active Current, Read: 15 mA (typical)
Active Current, Concurrent Read while Write:
40 mA (typical)
Standby Current: 3 A (typical)
Auto Low Power Mode Current: 3 A (typical)
Fast Write Operation
Flash Bank-Erase + Program: 8 sec (typical)
Flash Block-Erase + Program: 500 ms (typical)
Flash Sector-Erase + Program: 30 ms (typical)
E
2
bank Word-Write: 9 ms (typical)
Fixed Erase, Program, Write Times
Remain constant after cycling
Read Access Time
70 ns
Latched Address and Data
End-of-Write Detection
Toggle Bit
Data# Polling
E
2
Bank:
Word-Write (Auto Erase before Program)
Sector-Erase (32 Words) + Word-Program
(same as Flash bank)
Flash Bank: Two Small Erase Element Sizes
1 KWords per Sector or 32 KWords per Block
Erase either element before Word-Program
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
48-Pin TSOP (12mm x 20mm)
Continuous Hardware and Software
Data Protection (SDP)
A One Time Programmable (OTP) E
2
Sector
PRODUCT DESCRIPTION
The SST38VF166 consists of three memory banks, 2 each
512K x16 bits sector mode flash EEPROM plus a 4K x16
bits word alterable E
2
PROM manufactured with SST's pro-
prietary, high performance SuperFlash Technology. The
SST38VF166 erases and programs with a single power
supply. The internal Erase/Program in the E
2
bank is trans-
parent to the user. The device conforms to (proposed)
JEDEC standard pinouts for word-wide memories.
The SST38VF166 device is divided into three separate
memory banks, 2 each 512K x16 Flash banks and a 4K
x16 E
2
bank. Each Flash bank is typically used for program
code storage and contains 512 sectors, each of 1 KWords
or 16 blocks, each of 32 KWords. The Flash banks may
also be used to store data. The E
2
bank is typically used for
data or configuration storage and contains 128 sectors,
each of 32 words. Any bank may be used for executing
code while writing data to a different bank. Each memory
bank is controlled by separate Bank Enable (BE#) lines.
The SST38VF166 inherently uses less energy during
Erase, Program, and Write than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter Erase time, the
total energy consumed during any Erase, Program, or
Write operation is less than alternative flash technologies.
The Auto Low Power mode automatically reduces the
active read current to approximately the same as standby;
thus, providing an average read current of approximately 1
mA/MHz of Read cycle time.
The SuperFlash technology provides fixed Erase, Program,
and Write times, independent of the number of Erase/Pro-
gram cycles that have occurred. Therefore the system soft-
ware or hardware does not have to be modified or de-rated
as is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Device Operation
The SST38VF166 operates as two independent 8-Megabit
Word-Program, Sector-Erase flash EEPROMs with the
additional functionality of a 64 Kbit word-alterable
E
2
PROM. All banks are superimposed in the same mem-
ory address space. All three memory banks share com-
mon address lines, I/O lines, WE#, and OE#. Memory
bank selection is by bank enable. BE#1 selects the first
SST38VF16616Mb (x16) FlashBank + 64Kb E
2
2
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
Flash bank, BE#2 selects the second Flash bank, BE#3
selects the E
2
bank. WE# is used with SDP to control the
Write or Erase and Program operation in each memory
bank.
The SST38VF166 provides the added functionality of
being able to simultaneously read from one memory bank
while writing, erasing, or programming to one other mem-
ory bank. Once the internally controlled Write, Erase, or
Program cycle in a memory bank has commenced, a differ-
ent memory bank can be accessed for read. Also, once
WE# and the applicable BE# are high during the SDP load
sequence, a different bank may be accessed to read. If
multiple bank enables are asserted simultaneously, the out-
puts will tri-state and no new memory operations can be
initiated. Only one bank may be written, erased, or pro-
grammed at any given time. The device ID and Common
Flash Interface (CFI) functions cannot be accessed while
any bank is writing, erasing, or programming.
The Auto Low Power Mode automatically puts the device
in a near standby mode after data has been accessed with
a valid Read operation. This reduces the I
DD
active read
current from typically 15mA to typically 3A. The Auto Low
Power mode reduces the typical I
DD
active read current to
the range of 1mA/MHz of Read cycle time. The device exits
the Auto Low Power Mode with any address transition or
control signal transition used to initiate another Read cycle,
with no access time penalty.
Flash Bank Read
The Read operation of the SST38VF166 Flash Bank is
controlled by BE#1 or BE#2 and OE#, a bank enable and
output enable both have to be low for the system to obtain
data from the outputs. BE#1 is used for Flash bank 1
selection. When BE#1 is high, the Flash bank 1 is dese-
lected. BE#2 is used for Flash bank 2 selection. When
BE#2 is high, the Flash bank 2 is deselected. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when OE#
is high. Refer to the timing waveforms for further details
(Figure 2 or 3).
E
2
Bank Read
The Read operation of the E
2
bank is controlled by BE#3
and OE#, both have to be low for the system to obtain data
from the outputs. BE#3 is used for E
2
bank selection. When
BE#3 is high, the E
2
bank is deselected. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the timing waveforms for further details (Figure 4).
Write Modes
The SST38VF166 device has separate Write modes for
the E
2
bank and Flash banks. The conventional E
2
PROM
Word-Write with internally timed automatic Erase before
Program is the most convenient and easy method for the
user to alter data in the E
2
bank with the Word-Write opera-
tion, the word being written is the only word that is altered.
Bank- or Sector-Erase plus Word-Program operations may
also be used for the E
2
bank. For both banks of the Flash
array, the SST38VF166 offers Bank-, Block-, and Sector-
Erase plus Word-Program operations.
Write
All Write operations are initiated by first issuing the Soft-
ware Data Protect (SDP) entry sequence for Bank-, Block-,
or Sector-Erase then Word-Program in the selected Flash
bank; or for Word-Write or for Sector-Erase and Word-Pro-
gram in the E
2
bank. Word-Write, Word-Program, and all
Erase commands have a fixed duration, that will not vary
over the life of the device, i.e., are independent of the num-
ber of Erase/Program cycles endured.
Either Flash bank may be read during the internally con-
trolled E
2
bank Write cycle, e.g., the Flash bank may be
accessed to fetch instructions or data when the E
2
bank is
being written, erased, or programmed. Additionally, the
alternate Flash bank may be read while erasing or pro-
gramming the other Flash or E
2
bank. At any given time,
only one bank may be performing a Write operation, during
that time any other bank is available for read.
The Write Status command may be used to determine if
any bank is being written, at any given time. This may be
required if the system does not use a timer or does not
monitor toggle bit or data# polling when writing a specific
bank. In order to implement the Write Status command,
address 5XXXH in the E
2
bank address space is reserved.
This address is outside the normal address space of the E
2
bank; therefore, will not interfere with normal reading within
the E
2
bank address space.
The device is always in the Software Data Protected mode
for all Write operations in both the Flash bank and E
2
bank.
Write operations are controlled by toggling WE# or BE#.
The falling edge of WE# or BE#, whichever occurs last,
latches the address. The rising edge of WE# or BE#,
whichever occurs last, latches the data and initiates the
Erase, Program, or Write cycle.
The SDP Erase, Program, or Write commands are all BE#
specific. Whichever BE# is used for the first SDP bus cycle
(except for Read operation with WE# high), that BE# must
be used for all subsequent SDP bus cycles, for the com-
mand to be executed. If a different BE# is pulsed during a
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
3
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
subsequent bus cycle, when WE# is low, in the SDP com-
mand sequence, the device will abort the attempted SDP
command and revert to the Read mode. Note, the SDP
command sequence may be suspended by taking WE#
high. A different BE# may then be pulsed to read from
either of the banks not involved with the SDP command
sequence.
For the purposes of simplification, the following descrip-
tions will assume WE# is toggled to initiate an Erase, Pro-
gram, or Write. Toggling the applicable BE# will accomplish
the same function. Note, there are separate timing dia-
grams to illustrate both WE# and BE# controlled Program
or Write commands.
Flash Bank Word-Program
The Flash bank Word-Program operation consists of issu-
ing the SDP Word-Program command, initiated by forcing
BE#1 or BE#2 and WE# low, and OE# high. The words to
be programmed must be in the erased state, prior to pro-
gramming. The Word-Program command programs the
desired addresses word-by-word. During the Word-Pro-
gram cycle, the addresses are latched by the falling edge of
WE#. The data is latched by the rising edge of WE#. See
Figure 5 or 7 for WE# or 6 and 8 for BE# controlled Word-
Program cycle timing waveforms, Table 6 for the command
sequence, and Figure 49 for a flowchart.
During the Flash bank Erase or Program operation, the
only valid reads from that bank are Data# Polling and Tog-
gle Bit. The other Flash bank or the E
2
bank may be read.
The specified Bank-, Block-, or Sector-Erase time is the
only time required to erase. There are no preprogramming
or other commands or cycles required either internally or
externally to erase the bank, block, or sector.
E
2
Bank Word-Write
The E
2
bank Word-Write operation consists of issuing the
SDP command, initiated by forcing BE#3 and WE# low,
and OE# high; followed by the Word Load cycle to the
SST38VF166. The internally controlled Write cycle stores
the data loaded in the word buffer into the E
2
bank. The
address selected is then erased and programmed, by inter-
nally controlled signals. During the Word Load cycle, the
address is latched by the falling edge of WE#. The data is
latched by the rising edge of WE#. The internal write cycle
is initiated on the rising edge of WE#. The Write cycle, once
initiated, will continue to completion, typically within 7 ms.
See Figure 9 for WE# or 10 for BE# controlled write cycle
timing waveforms, Table 7 for the command sequence, and
Figure 48 for a flowchart.
The Write operation has two functional cycles: the Word
Load cycle and the internal Write cycle. The Word Load
cycle consists of loading 1 word of data into the word buffer
at the completion of the SDP sequence. The internal Write
cycle consists of the write timer operation, to erase and
program the selected address. Note, the word does NOT
have to be erased prior to writing. During the Write opera-
tion, the only valid reads are Data# Polling and Toggle Bit
from the E
2
bank or normal read from either of the Flash
banks.
E
2
Bank Word-Program
The E
2
bank Word-Program operation consists of issuing
the SDP Word-Program command, initiated by forcing
BE#3 and WE# low and OE# high. The Word-Program
command programs the desired addresses word-by-word.
The words to be programmed must be in the erased state,
prior to programming, unlike the Word-Write operation.
During the Word-Program cycle, the addresses are latched
by the falling edge of WE#. The data is latched by the rising
edge of WE#. See Figure 11 for WE# or 12 for BE#3 con-
trolled Program cycle timing waveforms, Table 7 for the
command sequence and Figure 50 for a flowchart.
During the E
2
bank Erase or Program operation, the only
valid reads from the bank are Data# Polling and Toggle Bit.
Either Flash bank may be read.
The specified Bank- or Sector-Erase time is the only time
required to erase. There are no preprogramming or other
commands or cycles required either internally or externally
to erase the bank or sector.
Erase Operations
The Bank-Erase is initiated by a specific six-word load
sequence See Tables 6 and 7. A Bank-Erase will typically
be less than 70 ms.
An alternative to the Bank-Erase in the Flash bank is the
Block-Erase or Sector-Erase. The Block-Erase will erase
an entire Block (32 KWords) in typically 15 ms. The Sector-
Erase will erase an entire sector (1024 words) in typically
15 ms. The Sector-Erase provides a means to alter a sin-
gle sector using the Sector-Erase and Word-Program
modes. The Sector-Erase is initiated by a specific six-word
load sequence, see Table 6.
The E
2
bank may also use a Sector-Erase, instead of
Bank-Erase. An E
2
bank sector consists of 32 words that
will typically erase in 7 ms. The Sector-Erase is initiated by
a specific six-word load sequence, see Table 7. Sector- or
Bank-Erase and Word-Program is an alternative to Word-
Write as a means to alter the E
2
bank.
4
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
During any Sector-, Block-, or Bank-Erase within a bank,
any other bank may be read. During the Word-Write of the
E
2
bank, either Flash bank may be read.
Flash Bank Bank-Erase
The SST38VF166 provides a Flash Bank-Erase mode,
which allows the user to clear the Flash bank to the "1"
state. This is useful when the entire Flash must be quickly
erased.
The software Flash Bank-Erase mode is initiated by issuing
the specific six-word loading sequence, as in the Software
Data Protection operation. After the loading cycle, the
device enters into an internally timed cycle. See Table 6 for
specific codes, Figure 13 or 16 for the timing waveform,
and Figure 44 for a flowchart.
Flash Bank Block-Erase
The SST38VF166 provides a Block-Erase mode, which
allows the user to clear any block in the Flash bank to the
"1" state.
The software Block-Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software
Data Protect operation. After the loading cycle, the device
enters into an internally timed Erase cycle. See Table 6 for
specific codes, Figure 14 or 17 for the timing waveform,
and Figure 45 for a flowchart. During the Erase operation,
the only valid reads are Data# Polling and Toggle Bit from
the selected bank, other banks may perform normal read.
Flash Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which
allows the user to clear any sector in the Flash bank to the
"1" state.
The software Sector-Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software
Data Protect operation. After the loading cycle, the device
enters into an internally timed Erase cycle. See Table 6 for
specific codes, Figure 15 or 18 for the timing waveform,
and Figure 47 for a flowchart. During the Erase operation,
the only valid reads are Data# Polling and Toggle Bit from
the selected bank, other banks may perform normal read.
E
2
Bank Bank-Erase
The SST38VF166 provides a E
2
Bank-Erase mode, which
allows the user to clear the E
2
bank to the "1" state. This is
useful when the entire E
2
bank must be quickly erased.
The E
2
bank Bank-Erase command is disabled if the E
2
bank OTP option is enabled.
The E
2
Bank-Erase mode is initiated by issuing the specific
six-word loading sequence, as in the Software Data Pro-
tection operation. After the loading cycle, the device enters
into an internally timed cycle. See Table 7 for specific
codes, Figure 19 for the timing waveform, and Figure 44 for
a flowchart.
E
2
Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which
allows the user to clear any sector in the E
2
bank to the "1"
state. The software Sector-Erase mode is initiated by issu-
ing the specific six-word loading sequence, as in the Soft-
ware Data Protect operation. After the loading cycle, the
device enters into an internally timed. See Tables 6 and 7
for specific codes, Figure 20 for the timing waveform, and
Figure 46 for a flowchart. During the Erase operation, the
only valid reads are Data# Polling and Toggle Bit in the E
2
bank or normal read from either of the Flash banks.
Write Operation Status Detection
The SST38VF166 provides two software means to detect
the completion of a E
2
bank or a Flash bank Program
cycle, in order to optimize the system Write cycle time. The
software detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write Detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Write, Erase, or Program cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system will possibly get
an erroneous result, i.e. valid data may appear to conflict
with either DQ
7
or DQ
6
. In order to prevent spurious device
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Additionally, a Write Status read may be executed to deter-
mine if any bank has an Erase, Program, or Write opera-
tion in progress. A Write Status read may be used when,
for any reason, the system may have lost track of the status
of a Write, Erase, or Program operation in any bank.
Although normally, a Word-Write, Word-Program, Sector-
Erase, or Block-Erase will be completed prior to recovery
from a system reset, if a Bank-Erase was initiated prior to
the reset, the system may need to verify the Bank-Erase is
no longer in progress. Note, a Bank-Erase will not be per-
formed on the bank containing the boot code, so there will
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
5
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
be no issue when recovering from the system reset. See
Table 6 or 7 for the specific codes and Figure 40 for a timing
waveform.
There is no provision to abort an Erase, Program, or Write
operation, once initiated. For the SST SuperFlash technol-
ogy, the associated Erase, Program, and Write times are
so fast, relative to system reset times, there is no value in
aborting the operation. Note, reads can always occur from
any bank not performing an Erase, Program, or Write oper-
ation.
Should the system reset, while a Block- or Sector-Erase or
Word-Program is in progress in the bank where the boot
code is stored, the system must wait for the completion of
the operation before reading that bank. Since the maxi-
mum time the system would have to wait is 25 ms (for a
Block-Erase), the system ability to read the boot code
would not be affected.
Data# Polling (DQ
7
) - Flash Bank
When the SST38VF166 is in the internal Flash bank Pro-
gram cycle, any attempt to read DQ
7
of the last word
loaded during the Flash bank Word Load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ
7
will show true data. The device is then
ready for the next operation. See Figure 21 or 22 for the
Flash bank Data Polling timing waveforms and Figure 51
for a flowchart.
Data# Polling (DQ
7
) - E
2
Bank
When the SST38VF166 is in the internal E
2
bank Write
cycle, any attempt to read DQ
7
of the last word loaded dur-
ing the E
2
bank Word Load cycle will receive the comple-
ment of the true data. Once the Write cycle is completed,
DQ
7
will show true data. The device is then ready for the
next operation. See Figure 23 for E
2
bank Data Polling tim-
ing waveforms and Figure 51 for a flowchart.
Toggle Bit (DQ
6
) - Flash Bank
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 24 or 25 for Flash bank Tog-
gle Bit timing waveforms and Figure 51 for a flowchart.
Toggle Bit (DQ
6
) - E
2
Bank
During the E
2
bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 26 for E
2
bank Toggle Bit
timing waveforms and Figure 51 for a flowchart.
Data Protection
The SST38VF166 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, BE#1 and BE#2 high,
or WE# high will inhibit the Write operation to the Flash
bank. Forcing OE# low, BE#3 high, or WE# high will inhibit
the Write operation to the E
2
bank. This prevents inadvert-
ent writes during power-up or power-down.
A One Time Programmable E
2
Sector
The first sector of the E
2
bank offers the option of OTP
(One Time Programmable) prevention of write for the first
sector, i.e., addresses A
5
to A
13
are "0" (0000H to 001FH).
Once the OTP software instruction is executed, no Write,
Erase, or Program operation can be performed on these 32
words. This is permanent and non-reversible. Additionally, if
the OTP prevention is enabled, the Bank-Erase for the E
2
bank will not function. See Table 7 for specific codes and
Figure 39 for a timing waveform.
Software Data Protection (SDP)
The SST38VF166 provides the JEDEC approved Software
Data Protection scheme as a requirement for initiating a
Write, Erase, or Program operation. With this scheme, any
Write operation requires the inclusion of a series of three
word-load operations to precede the Word-Write or Word-
Program operation. The three-word load sequence is used
to initiate the Write or Program cycle, providing optimal pro-
tection from inadvertent Write operations, e.g., during the
system power-up or power-down. The six-word sequence
is required to initiate any Bank-, Block-, or Sector-Erase
operation.
6
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
The requirements for JEDEC compliant SDP are in byte
format. The SST38VF166 is organized by word; therefore,
the contents of DQ
8
to DQ
15
are "Don't Care" during any
SDP (3-word or 6-word) command sequence.
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur to any other bank during the SDP load
sequence.
The SDP load sequence is bank specific, i.e., the same
BE# must be low for each bus cycle. If the command
sequence is aborted, e.g., a different BE# is brought low
(except for Read operation with WE# high), an incorrect
address is loaded, or incorrect data is loaded, the device
will return to the Read mode within T
RC
of execution of the
load error.
Concurrent Read and Write Operations
The SST38VF166 provides the unique benefit of being
able to read any bank, while simultaneously writing, eras-
ing, or programming one other bank. This allows data alter-
ation code to be executed from one bank, while altering the
data in another bank. The following table lists all valid
states.
Note: For the purposes of this table, write means to Word-Write;
Block-, Sector-, or Chip-Erase; or Word-Program as applica-
ble to the appropriate bank.
SST does not recommend that any two of the bank enable
signals BE#1, BE#2 or BE#3 be simultaneously asserted.
The device will ignore all SDP commands and toggling of
WE# when an Erase, Program, or Write operation is in
progress. Note, both Product Identification and the Com-
mon Flash Interface entry commands use SDP; therefore,
these commands will also be ignored while an Erase, Pro-
gram, or Write operation is in progress.
Product Identification
The product identification mode identifies the device manu-
facturer as SST and provides a code to identify each bank.
The manufacturer ID is the same for each bank; however,
each bank has a separate device ID. Each bank is individu-
ally accessed using the applicable BE# and a software
command. Users may wish to use the device ID operation
to identify the write algorithm requirements for each bank.
For details, see Table 6 or 7 for software operation and Fig-
ures 27, 28, or 29 for timing waveforms.
Device IDs are unique to each bank. Should a chip ID be
required, any of the bank IDs may be used as the chip ID.
While in the read software ID mode or CFI mode, no other
operation is allowed until after exiting these modes.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the
device to behave abnormally, e.g., not read correctly. For
details, see Table 6 or 7 for software operation and Figures
30, 31, or 32 for timing waveforms.
TABLE
1: C
ONCURRENT
R
EAD
/W
RITE
S
TATE
Flash Bank 1
Flash Bank 2
E
2
Bank
Read
No Operation
Write
Read
Write
No Operation
Write
Read
No Operation
No Operation
Read
Write
Write
No Operation
Read
No Operation
Write
Read
T1.0 327
TABLE
2: P
RODUCT
I
DENTIFICATION
Address
Data
Manufacturer's ID
0000H
00BFH
Device ID
Flash Bank 1
0001H
2791H
Flash Bank 2
0001H
2792H
E
2
Bank
0001H
2793H
T2.1 327
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
7
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
Common Flash Interface (CFI)
The SST38VF166 also contains the CFI information in
each bank, to describe the characteristics of that bank. See
Tables 8 through 16 for the CFI contents for each bank.
Both flash banks use the same information, as each bank
operates the same. The E
2
bank contains the applicable
information for that bank.
In order to obtain the CFI information, the CFI memory
space is accessed by using the CFI entry command. For
details, see Table 6 or 7 for software operation and Figures
33, 34, or 35 for timing waveforms.
CFI Mode Exit
In order to return to the standard Read mode, the CFI
mode must be exited. Exit is accomplished by issuing the
CFI exit command, which returns the device to normal
operation. This command may also be used to reset the
device to the Read mode after any inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g., not read correctly. For details, see Table 6
or 7 for software operation and Figures 36, 37, or 38 for tim-
ing waveforms.
CFI is specified for byte wide information. Since the
SST38VF166 is organized word wide, the first byte (2 nib-
bles) of each CFI word is always 00H.
327 ILL F02.1
I/O Buffers and
Data Latches
512K x 16
Flash
Bank 2
4K x 16
E
2
Bank
512K x 16
Flash
Bank 1
X - Decoder
Control Logic
Address Buffer
and Latches
OE#
BE#1
BE#2
BE#3
WE#
A18 - A0
DQ15 - DQ0
Charge
Pump &
Vref.
Y - Decoder
F
UNCTIONAL
B
LOCK
D
IAGRAM
8
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 1: P
IN
A
SSIGNMENTS
FOR
48-P
IN
TSOP (12
MM
X
20
MM
)
TABLE
3: P
IN
D
ESCRIPTION
Symbol
Name
Functions
A
18
-A
0
Flash Bank Addresses
To provide Flash Bank addresses
A
11
-A
0
E
2
Bank Addresses
To provide E
2
Bank addresses
A
18
-A
15
Flash Bank Block Addresses
To select a Flash Bank Block for erase
A
18
-A
10
Flash Bank Sector Addresses To select a Flash Bank Sector for erase
A
11
-A
5
E
2
Bank Sector Addresses
To select an E
2
Bank Sector for erase
DQ
15
-DQ
0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# is high or BE#1, BE#2, and BE#3 are high.
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable 1
To control the Write, Erase, or Program operations
V
DD
Power Supply
To provide 2.7-3.6V power supply
V
SS
Ground
NC
No Connect
Unconnected pins
T3.4 327
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
BE#2
NC
BE#3
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
BE#1
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
327 ILL F01b.5
Standard Pinout
Top View
Die Up
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
9
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE
4: O
PERATION
M
ODES
S
ELECTION
FOR
F
LASH
B
ANK
Array Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Read
Flash Bank 1
V
IL
V
IH
V
IH
V
IL
V
IH
D
OUT
A
IN
Flash Bank 2
V
IH
V
IL
V
IH
V
IL
V
IH
D
OUT
A
IN
Block-Erase
Flash Bank 1
V
IL
V
IH
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Sector-Erase
Flash Bank 1
V
IL
V
IH
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Program
Flash Bank 1
V
IL
V
IH
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Standby
V
IH
V
IH
V
IH
X
X
High Z
X
Write Inhibit
Flash Bank 1
V
IH
X
X
V
IL
V
IH
X
X
Flash Bank 2
X
V
IH
X
V
IL
V
IH
X
X
Flash Bank-Erase
Flash Bank 1
V
IL
V
IH
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IH
V
IL
D
IN
See Tables 6 and 7
Status Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Write Status Read
V
IH
V
IH
V
IL
V
IL
V
IH
D
OUT
1
5XXXXH
Illegal State
V
IL
V
IL
V
IL
X
X
High Z
X
2
Illegal State
V
IL
V
IL
X
X
X
High Z
X
2
Illegal State
V
IL
X
V
IL
X
X
High Z
X
2
Illegal State
X
V
IL
V
IL
X
X
High Z
X
2
Product Identification
Flash Bank 1
V
IL
V
IH
V
IH
V
IL
V
IH
D
OUT
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IL
V
IH
D
OUT
See Tables 6 and 7
Common Flash Interface
Flash Bank 1
V
IL
V
IH
V
IH
V
IL
V
IH
D
OUT
See Tables 6 and 7
Flash Bank 2
V
IH
V
IL
V
IH
V
IL
V
IH
D
OUT
See Tables 6 and 7
T4.5 327
1. If Flash Bank 1 is writing, DQ
1
is low. If Flash Bank 2 is writing, DQ
2
is low. If E
2
Bank is writing, DQ
3
is low.
2. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write
will continue to normal completion.
10
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE
5: O
PERATION
M
ODES
S
ELECTION
FOR
E
2
B
ANK
Read Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Read E
2
Bank
V
IH
V
IH
V
IL
V
IL
V
IH
D
OUT
1
Write E
2
Bank
V
IH
V
IH
V
IL
V
IH
V
IL
D
IN
See Tables 6 and 7
Sector-Erase E
2
Bank
V
IH
V
IH
V
IL
V
IH
V
IL
D
IN
See Tables 6 and 7
Program E
2
Bank
V
IH
V
IH
V
IL
V
IH
V
IL
D
IN
See Tables 6 and 7
Standby
V
IH
V
IH
V
IH
X
X
D
IN
See Tables 6 and 7
Write Inhibit E
2
Bank
X
X
V
IH
V
IL
V
IH
High Z
X
Erase E
2
Bank
V
IH
V
IH
V
IL
V
IH
V
IL
D
IN
See Tables 6 and 7
OTP Enable E
2
Bank
V
IH
V
IH
V
IL
V
IH
V
IL
D
IN
See Tables 6 and 7
Status Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Write Status Read
V
IH
V
IH
V
IL
V
IL
V
IH
D
OUT
2
5XXXXH
Illegal State
V
IL
V
IL
V
IL
X
X
High Z
X
3
Illegal State
V
IL
V
IL
X
X
X
High Z
X
3
Illegal State
V
IL
X
V
IL
X
X
High Z
X
3
Illegal State
X
V
IL
V
IL
X
X
High Z
X
3
Product Identification
E
2
Bank
V
IH
V
IH
V
IL
V
IL
V
IH
D
OUT
See Tables 6 and 7
Common Flash Interface
E
2
Bank
V
IH
V
IH
V
IL
V
IL
V
IH
D
OUT
See Tables 6 and 7
T5.6 327
1. A
11
-A
0
are valid addresses; A
15
-A
12
are "Don't Care"; A
18
-A
16
cannot be 5H
2. If Flash Bank 1 is writing, DQ
1
is low. If Flash Bank 2 is writing, DQ
2
is low. If E
2
Bank is writing, DQ
3
is low.
3. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write
will continue to normal completion.
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
11
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE
6: S
OFTWARE
C
OMMAND
S
EQUENCE
FOR
F
LASH
B
ANKS
Command Code
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
6th Bus Cycle
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Software ID Entry
5555H
AAH
2AAAH
55H
5555H
90H
3
Software ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
Flash Bank
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA
5
Data
In
Flash Bank
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
6
30H
Flash Bank
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BA
6
50H
Flash Bank
Bank-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
CFI Entry
5555H
AAH
2AAAH
55H
5555H
98H
7
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
T6.4 327
1. Command Code Address format A
14
-A
0
(Hex), Addresses > A
14
are "Don't Care" for Command sequences
2. Data format DQ
7
-DQ
0
(Hex), DQ
15
- DQ
8
are "Don't Care"
3. With A
14
-A
1
= 0; SST Manufacturer's ID = 00BFH, is read with A
0
= 0
SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A
0
= 1 for the applicable BE# active
4. The device does not remain in Software Product ID Mode or CFI Mode if powered down.
5. WA = Word address
6. SA = Sector address
BA = Block address
7. There is a separate CFI for each bank. See Tables 8 through 16
TABLE
7: S
OFTWARE
C
OMMAND
S
EQUENCE
FOR
E
2
B
ANKS
Command Code
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
6th Bus Cycle
Addr
1
1. Command Code Address format A
14
-A
0
(Hex), Addresses > A
14
are "Don't Care" for Command sequences
Data
2
2. Data format DQ
7
-DQ
0
(Hex), DQ
15
- DQ
8
are "Don't Care"
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Addr
1
Data
2
Software ID Entry
5555H
AAH
2AAAH
55H
5555H
90H
3
3. With A
14
-A
1
= 0; SST Manufacturer's ID = 00BFH, is read with A
0
= 0
SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A
0
= 1 for the applicable BE# active
Software ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
4. The device does not remain in Software Product ID Mode or CFI Mode if powered down.
E
2
Bank
Word-Write
5555H
AAH
2AAAH
55H
5555H
A0H
WA
5
5. WA = Word address
Data
In
E
2
Bank
Word-Program
5555H
AAH
2AAAH
55H
5555H
A5H
WA
5
Data
In
E
2
Bank
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
6
6. SA = Sector address
30H
E
2
Bank
Bank-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
E
2
Bank
OTP Enable
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
70H
CFI Entry
5555H
AAH
2AAAH
55H
5555H
98H
7
7. There is a separate CFI for each bank. See Tables 8 through 16
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
T7.4 327
12
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE
8: CFI Q
UERY
I
DENTIFICATION
S
TRING
FOR
F
LASH
B
ANK
1
Address
Data
Data
10H
0051H
Query Unique ASCII string "QRY"
11H
0052H
12H
0059H
13H
0001H
Primary OEM command set (JEP-137)
14H
0008H
15H
0000H
Address for Primary Extended Table (00H = none exists)
16H
0000H
17H
0000H
Alternate OEM command set (00H = none exists)
18H
0000H
19H
0000H
Address for Alternate OEM extended Table (00H = none exits)
1AH
0000H
T8.2 327
TABLE
9: S
YSTEM
I
NTERFACE
I
NFORMATION
FOR
F
LASH
B
ANK
1
Address
Data
Data
1BH
0027H
V
DD
Min (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1CH
0036H
V
DD
Max (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1DH
0000H
V
PP
min. (00H = no V
PP
pin)
1EH
0000H
V
PP
max. (00H = no V
PP
pin)
1FH
0004H
Typical time out for Word-Program 2
N
s
20H
0000H
Typical time out for min. size Page-Write 2
N
s (00H = not supported)
21H
0004H
Typical time out for individual Sector-Erase 2
N
ms
22H
0006H
Typical time out for Bank-Erase 2
N
ms
23H
0001H
Maximum time out for Word-Program 2
N
times typical
24H
0000H
Maximum time out for Page-Write 2
N
times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2
N
times typical
26H
0001H
Maximum time out for Chip-Erase 2
N
times typical
T9.7 327
TABLE 10: D
EVICE
G
EOMETRY
I
NFORMATION
FOR
F
LASH
B
ANK
1
Address
Data
Data
27H
0014H
Bank size = 2
N
Byte (14H > 2
20
= 1 MByte = 8 Mbits)
28H
0001H
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
29H
0000H
2AH
0000H
Maximum number of bytes in Page-Write = 2
N
(00H = not supported)
2BH
0000H
2CH
0002H
Number of Erase Block Regions within device
2DH
00FFH
Erase Block Region 1 Information (Sector)
2EH
0001H
(Refer to the CFI specification or JESD-68)
2FH
0008H
y = 511 + 1 = 512 sectors (01FFH = 511)
30H
0000H
z = 2 KBytes/sector = 8 x 256 Bytes
31H
000FH
Erase Block Region 2 Information (Block)
32H
0000H
(Refer to the CFI specification or JESD-68)
33H
0000H
y = 15 + 1 = 16 blocks
34H
0001H
z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T10.5 327
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
13
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE 11: CFI Q
UERY
I
DENTIFICATION
S
TRING
FOR
F
LASH
B
ANK
2
Address
Data
Data
10H
0051H
Query Unique ASCII string "QRY"
11H
0052H
12H
0059H
13H
0001H
Primary OEM command set (JEP-137)
14H
0008H
15H
0000H
Address for Primary Extended Table (00H = none exists)
16H
0000H
17H
0000H
Alternate OEM command set (00H = none exists)
18H
0000H
19H
0000H
Address for Alternate OEM extended Table (00H = none exits)
1AH
0000H
T11.2 327
TABLE 12: S
YSTEM
I
NTERFACE
I
NFORMATION
FOR
F
LASH
B
ANK
2
Address
Data
Data
1BH
0027H
V
DD
Min (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1CH
0036H
V
DD
Max (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1DH
0000H
V
PP
min. (00H = no V
PP
pin)
1EH
0000H
V
PP
max. (00H = no V
PP
pin)
1FH
0004H
Typical time out for Word-Program 2
N
s
20H
0000H
Typical time out for min. size Page-Write 2
N
s (00H = not supported)
21H
0004H
Typical time out for individual Sector-Erase 2
N
ms
22H
0006H
Typical time out for Bank-Erase 2
N
ms
23H
0001H
Maximum time out for Word-Program 2
N
times typical
24H
0000H
Maximum time out for Page-Write 2
N
times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2
N
times typical
26H
0001H
Maximum time out for Chip-Erase 2
N
times typical
T12.8 327
TABLE 13: D
EVICE
G
EOMETRY
I
NFORMATION
FOR
F
LASH
B
ANK
2
Address
Data
Data
27H
0014H
Bank size = 2
N
Byte (14H > 2
20
= 1 MByte = 8 Mbits)
28H
0001H
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
29H
0000H
2AH
0000H
Maximum number of bytes in Page-Write = 2
N
(00H = not supported)
2BH
0000H
2CH
0002H
Number of Erase Block Regions within device
2DH
00FFH
Erase Block Region 1 Information (Sector)
2EH
0001H
(Refer to the CFI specification or JESD-68)
2FH
0008H
y = 511 + 1 = 512 sectors (01FFH = 511)
30H
0000H
z = 2 KBytes/sector = 8 x 256 Bytes
31H
000FH
Erase Block Region 2 Information (Block)
32H
0000H
(Refer to the CFI specification or JESD-68)
33H
0000H
y = 15 + 1 = 16 blocks
34H
0001H
z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T13.5 327
14
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE 14: CFI Q
UERY
I
DENTIFICATION
S
TRING
FOR
E
2
B
ANK
Address
Data
Data
10H
0051H
Query Unique ASCII string "QRY"
11H
0052H
12H
0059H
13H
0001H
Primary OEM command set (JEP-137)
14H
0009H
15H
0000H
Address for Primary Extended Table (00H = none exists)
16H
0000H
17H
0000H
Alternate OEM command set (00H = none exists)
18H
0000H
19H
0000H
Address for Alternate OEM extended Table (00H = none exits)
1AH
0000H
T14.1 327
TABLE 15: S
YSTEM
I
NTERFACE
I
NFORMATION
FOR
E
2
B
ANK
Address
Data
Data
1BH
0027H
V
DD
Min (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1CH
0036H
V
DD
Max (Program/Erase)
DQ
7
-DQ
4
: Volts, DQ
3
-DQ
0
: 100 millivolts
1DH
0000H
V
PP
min. (00H = no V
PP
pin)
1EH
0000H
V
PP
max. (00H = no V
PP
pin)
1FH
0005H
Typical time out for Word-Program 2
N
s
20H
0000H
Typical time out for min. size Page-Write 2
N
s (00H = not supported)
21H
0003H
Typical time out for individual Sector-Erase 2
N
ms
22H
0006H
Typical time out for Bank-Erase 2
N
ms
23H
0001H
Maximum time out for Word-Program 2
N
times typical
24H
0000H
Maximum time out for Page-Write 2
N
times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2
N
times typical
26H
0001H
Maximum time out for Chip-Erase 2
N
times typical
T15.7 327
TABLE 16: D
EVICE
G
EOMETRY
I
NFORMATION
FOR
E
2
B
ANK
Address
Data
Data
27H
000DH
Device size = 2
N
Byte (DH > 2
13
= 8 KBytes = 64 Kbits)
28H
0001H
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
29H
0000H
2AH
0001H
Maximum number of bytes in Page-Write = 2
N
(00H = not supported)
2BH
0000H
2CH
0001H
Number of Erase Block Regions within device
2DH
007FH
Erase Block Region 1 Information (Sector)
2EH
0000H
(Refer to the CFI specification or JESD-68)
2FH
0001H
y = 127 + 1 = 128 sectors (007FH = 127)
30H
0000H
z = 32 Bytes/sector = 1 x 256 Bytes
T16.4 327
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
15
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum
Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
DD
+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V
DD
+ 1.0V
Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C
Output Short Circuit Current
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
O
PERATING
R
ANGE
:
Range
Ambient Temp
V
DD
Commercial
0C to +70C
2.7-3.6V
AC C
ONDITIONS
OF
T
EST
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . C
L
= 30 pF
See Figures 42 and 43
TABLE 17: DC O
PERATING
C
HARACTERISTICS
V
DD
= 2.7-3.6V
Symbol
Parameter
Limits
Test Conditions
Min
Max
Units
I
DD
Power Supply Current
Address input = V
IL
/V
IH
, at f=1/T
RC
Min
V
DD
=V
DD
Max
Read
35
mA
BE#1,BE#2, or BE#3=V
IL
, WE#=V
IH
,
all I/Os open
Write: Flash Bank
40
mA
BE#1/2=WE#=V
IL
, OE#=V
IH
V
DD
=V
DD
Max or E
2
Bank
BE#3=WE#=V
IL
, OE#=V
IH
V
DD
=V
DD
Max
Read: Flash Bank plus
Write/Program/Erase:
E2 Bank or Flash Bank
75
mA
Address input = V
IL
/V
IH
, at f=1/T
RC
Min
WE#=V
IH
, V
DD
=V
DD
Max
BE#1,BE#2, or BE#3=V
IL
, OE#=WE#=V
IH
,
I
SB
Standby V
DD
Current
(CMOS inputs)
50
A
BE#1,BE#2, or BE#3=V
IHC
,
V
DD
= V
DD
Max
I
ALP
Auto Low Power Mode
(CMOS inputs)
50
A
BE#1,BE#2, or BE#3=V
ILC
, WE#= V
IHC
,
all I/Os open, Address input = V
IHC
/V
IHC
and static V
DD
=V
DD
Max
I
LI
Input Leakage Current
1
A
V
IN
=GND to V
DD
, V
DD
= V
DD
Max
I
LO
Output Leakage Current
1
A
V
OUT
=GND to V
DD
, V
DD
= V
DD
Max
V
IL
Input Low Voltage
0.3V
DD
V
V
DD
= V
DD
Min
V
ILC
Input Low Voltage (CMOS)
0.2
V
V
IH
Input High Voltage
0.7V
DD
V
V
DD
= V
DD
Max
V
IHC
Input High Voltage (CMOS)
V
DD
-0.2
V
V
DD
= V
DD
Max
V
OL
Output Low Voltage
0.2
V
I
OL
= 100 A, V
DD
= V
DD
Min
V
OH
Output High Voltage
V
DD
-0.2
V
I
OH
= -100 A, V
DD
= V
DD
Min
T17.1 327
16
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TABLE 18: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
Parameter
Minimum
Units
T
PU-READ
1
Power-up to Read Operation
100
s
T
PU-WRITE
1
Power-up to Write Operation
100
s
T18.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 19: C
APACITANCE
(Ta = 25C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
C
I/O
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance
V
I/O
= 0V
12 pF
C
IN
1
Input Capacitance
V
IN
= 0V
6 pF
T19.1 327
TABLE 20: R
ELIABILITY
C
HARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
N
END
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance - Flash Bank
Endurance - E2 Bank
10,000
100,000
Cycles/Sector
Cycles/Word
JEDEC Standard A117
T
DR
1
Data Retention
100
Years
JEDEC Standard A103
V
ZAP_HBM
1
ESD Susceptibility
Human Body Model
2000
Volts
JEDEC Standard A114
V
ZAP_MM
1
ESD Susceptibility
Machine Model
200
Volts
JEDEC Standard A115
I
LTH
1
Latch Up
100 + I
DD
mA
JEDEC Standard 78
T20.0 327
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
17
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
AC CHARACTERISTICS
TABLE 21: R
EAD
C
YCLE
T
IMING
P
ARAMETERS
Symbol
Parameter
SST38VF166-70
Units
Min
Max
T
RC
Read Cycle Time
70
ns
T
BE
Bank Enable Access Time
70
ns
T
AA
Address Access Time
70
ns
T
OE
Output Enable Access Time
30
ns
T
CLZ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output
0
ns
T
OLZ
1
OE# Low to Active Output
0
ns
T
CHZ
1
CE# High to High-Z Output
20
ns
T
OHZ
1
OE# High to High-Z Output
20
ns
T
OH
1
Output Hold from Address Change
0
ns
T21.1 327
TABLE 22: W
RITE
, E
RASE
, P
ROGRAM
C
YCLE
T
IMING
P
ARAMETERS
Symbol
Parameter
Min
Max
Units
T
WC
Word-Write Cycle (Erase and Program)
12.5
ms
T
BPE
Word-Program Time - E
2
Bank
40
s
T
BPF
Word-Program Time - Flash Bank
20
s
T
SEF
Sector-Erase Time - Flash Bank
25
ms
T
LEF
Block-Erase Time - Flash Bank
25
ms
T
BEF
Bank-Erase Time - Flash Bank
100
ms
T
SEE
Sector-Erase Time - E
2
Bank
12.5
ms
T
BEE
Bank-Erase Time - E
2
Bank
100
ms
T
AS
Address Setup Time
0
ns
T
AH
Address Hold Time
40
ns
T
BES
BE# Setup Time
0
ns
T
BEH
BE# Hold Time
0
ns
T
OES
OE# High Setup Time
0
ns
T
OEH
OE# High Hold Time
0
ns
T
WP
Write Pulse Low Width
40
ns
T
WPH
Write Pulse High Time
30
ns
T
DS
Data Setup Time
40
ns
T
DH
Data Hold Time
0
ns
T
VDDR
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
V
DD
Rise Time
0.1
50
ms
T
DBR
Time to DATA# Polling Read
35
ns
T
TBR
Time to Toggle Bit Read
35
ns
T
IDA
Time to ID or CFI Read/Exit Cycle
150
ns
T
BS
Bank Enable Setup Time for Concurrent Operation
0
ns
T22.0 327
18
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
TIMING DIAGRAMS
Address and data format are in hexadecimal
FIGURE 2: F
LASH
B
ANK
1, R
EAD
C
YCLE
T
IMING
D
IAGRAM
FIGURE 3: F
LASH
B
ANK
2, R
EAD
C
YCLE
T
IMING
D
IAGRAM
327 ILL F03a.2
ADDRESS A18-0
DQ15-0
BE#2, BE#3, WE#
OE#
BE#1
TBE
TRC
TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ
TOH
TCHZ
HIGH-Z
DATA VALID
DATA VALID
TOHZ
327 ILL F03b.2
ADDRESS A18-0
DQ15-0
BE#1 , BE#3, WE#
OE#
BE#2
TBE
TRC
TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ
TOH
TCHZ
HIGH-Z
DATA VALID
DATA VALID
TOHZ
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
19
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 4: E
2
B
ANK
, R
EAD
C
YCLE
T
IMING
D
IAGRAM
FIGURE 5: F
LASH
B
ANK
1, WE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
327 ILL F03c.2
ADDRESS A11-0
DQ15-0
BE#1 , BE#2, WE#
OE#
BE#3
TBE
TRC
TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ
TOH
TCHZ
HIGH-Z
DATA VALID
DATA VALID
TOHZ
327 ILL F04a1.3
ADDRESS A18-0
DQ150
TDH
TWPH
TDS
TWP
TAH
TAS
TBEH
TBES
BE#1
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#2, BE#3, OE#
WE#
TBPF
20
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 6: F
LASH
B
ANK
1, BE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
FIGURE 7: F
LASH
B
ANK
2, WE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
327 ILL F04a2.3
ADDRESS A18-0
DQ150
TDH
TWPH
TDS
TWP
TAH
TAS
TWEH
TWES
WE#1
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#2, BE#3, OE#
BE#1
TBPF
327 ILL F04b1.3
ADDRESS A18-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TBEH
TBES
BE#2
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#3, OE#
WE#
TBPF
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
21
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 8: F
LASH
B
ANK
2, BE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
FIGURE 9: E
2
B
ANK
, WE# C
ONTROLLED
W
ORD
-W
RITE
C
YCLE
T
IMING
D
IAGRAM
327 ILL F04b2.3
ADDRESS A18-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TWEH
TWES
WE#
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#3, OE#
BE#2
TBPF
327 ILL F04c1.3
ADDRESS A14-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TBEH
TBES
BE#3
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#2, OE#
WE#
TWC
22
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 10: E
2
B
ANK
, BE# C
ONTROLLED
W
ORD
-W
RITE
C
YCLE
T
IMING
D
IAGRAM
FIGURE 11: E
2
B
ANK
, WE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
327 ILL F04c2.3
ADDRESS A14-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TWEH
TWES
WE#
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A0
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#2, OE#
BE#3
TWC
327 ILL F04d1.3
ADDRESS A14-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TBEH
TBES
BE#3
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A5
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#2, OE#
WE#
TBPE
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
23
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 12: E
2
B
ANK
, BE# C
ONTROLLED
W
ORD
-P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
FIGURE 13: F
LASH
B
ANK
1, B
ANK
-E
RASE
T
IMING
D
IAGRAM
326 ILL F04d 2.3
ADDRESS A14-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TWEH
TWES
WE#
SW0
SW1
SW2
5555
2AAA
5555
ADDR
AA
55
A5
DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
BE#1, BE#2, OE#
BE#3
TBPE
327 ILL F05a1.2
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
10
55
AA
80
AA
5555
BE#2, BE#3, OE#
BE#1
SIX-BYTE CODE FOR BANK-ERASE
TBEF
TWP
TAH
TAS
TWPH
TDH
TDS
24
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 14: F
LASH
B
ANK
1, B
LOCK
-E
RASE
T
IMING
D
IAGRAM
FIGURE 15: F
LASH
B
ANK
1, S
ECTOR
-E
RASE
T
IMING
D
IAGRAM
327 ILL F05a2.3
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
50
55
AA
80
AA
BAX
BE#2, BE#3, OE#
BE#1
SIX-BYTE CODE FOR BLOCK-ERASE
TLEF
TWP
TAH
TAS
TWPH
TDH
TDS
327 ILL F05a3.3
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
30
55
AA
80
AA
SAX
BE#2, BE#3, OE#
BE#1
SIX-BYTE CODE FOR SECTOR-ERASE
TSEF
TWP
TAH
TAS
TWPH
TDH
TDS
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
25
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 16: F
LASH
B
ANK
2, B
ANK
-E
RASE
T
IMING
D
IAGRAM
FIGURE 17: F
LASH
B
ANK
2, B
LOCK
-E
RASE
T
IMING
D
IAGRAM
327 ILL F05b1.2
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
10
55
AA
80
AA
5555
BE#1, BE#3, OE#
BE#2
SIX-BYTE CODE FOR BANK-ERASE
TBEF
TWP
TAH
TAS
TWPH
TDH
TDS
327 ILL F05b2.4
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
50
55
AA
80
AA
BAX
BE#1, BE#3, OE#
BE#2
SIX-BYTE CODE FOR BLOCK-ERASE
TLEF
TWP
TAH
TAS
TWPH
TDH
TDS
26
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 18: F
LASH
B
ANK
2, S
ECTOR
-E
RASE
T
IMING
D
IAGRAM
FIGURE 19: E
2
B
ANK
, B
ANK
-E
RASE
T
IMING
D
IAGRAM
327 ILL F05b3.3
ADDRESS A18-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
30
55
AA
80
AA
SAX
BE#1, BE#3, OE#
BE#2
SIX-BYTE CODE FOR SECTOR-ERASE
TS EF
TWP
TAH
TAS
TWPH
TDH
TDS
327 ILL F05c1.2
ADDRESS A14-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
10
55
AA
80
AA
5555
BE#1, BE#2, OE#
BE#3
SIX-BYTE CODE FOR BANK-ERASE
TBEE
TWP
TAH
TAS
TWPH
TDH
TDS
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
27
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 20: E
2
B
ANK
, S
ECTOR
-E
RASE
T
IMING
D
IAGRAM
FIGURE 21: F
LASH
B
ANK
1, D
ATA
# P
OLLING
T
IMING
D
IAGRAM
327 ILL F05c2.3
ADDRESS A14-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
30
55
AA
80
AA
SAX
BE#1, BE#2, OE#
BE#3
SIX-BYTE CODE FOR SECTOR-ERASE
TSEE
TWP
TAH
TAS
TWPH
TDH
TDS
326 ILL F06a.3
DQ7
Data
Data#
Data#
Data
TOEH
TOE
TBE
TOES
ADDRESS A18-0
WE#
BE#2, BE#3
OE#
BE#1
28
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 22: F
LASH
B
ANK
2, D
ATA
# P
OLLING
T
IMING
D
IAGRAM
FIGURE 23: E
2
B
ANK
, D
ATA
# P
OLLING
T
IMING
D
IAGRAM
327 ILL F06b.3
DQ7
Data
Data#
Data#
Data
TOEH
TOE
TBE
TOES
ADDRESS A18-0
WE#
OE#
BE#2
BE#1, BE#3
327 ILL F06c.3
DQ7
Data
Data#
Data#
Data
TOEH
TOE
TBE
TOES
ADDRESS A14-0
WE#
OE#
BE#3
BE#1, BE#2
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
29
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 24: F
LASH
B
ANK
1, T
OGGLE
B
IT
T
IMING
D
IAGRAM
FIGURE 25: F
LASH
B
ANK
2, T
OGGLE
B
IT
T
IMING
D
IAGRAM
327 ILL F07a.3
ADDRESS A18-0
DQ6
WE#
OE#
BE#1
TOE
TOEH
TBE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
BE#2, BE#3
327 ILL F07b.3
ADDRESS A18-0
DQ6
WE#
OE#
BE#2
TOE
TOEH
TBE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
BE#1, BE#3
30
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 26: E
2
B
ANK
, T
OGGLE
B
IT
T
IMING
D
IAGRAM
FIGURE 27: F
LASH
B
ANK
1, S
OFTWARE
ID E
NTRY
AND
R
EAD
326 ILL F07c.3
ADDRESS A14 -0
DQ6
WE#
OE#
BE#3
TOE
TOEH
TBE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
BE#1, BE#2
327 ILL F08a.5
ADDRESS A14-0
TIDA
DQ15-0
WE#
OE#
SW0
SW1
SW2
5555
2AAA
5555
0000
0001
BE#1
Three-Byte Sequence for
Software ID Entry
TWP
TWPH
TAA
00BF
55
AA
90
BE#2, BE#3
2791
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
31
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 28: F
LASH
B
ANK
2, S
OFTWARE
ID E
NTRY
AND
R
EAD
FIGURE 29: E
2
B
ANK
, S
OFTWARE
ID E
NTRY
AND
R
EAD
327 ILL F08b.5
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0
SW1
SW2
5555
2AAA
5555
0000
0001
BE#2
Three-Byte Sequence for
Software ID Entry
TWP
TWPH
TAA
00BF
55
AA
90
OE#
BE#1, BE#3
2792
327 ILL F08c.5
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0
SW1
SW2
5555
2AAA
5555
0000
0001
BE#3
Three-Byte Sequence for
Software ID Entry
TWP
TWPH
TAA
00BF
2793
55
AA
90
BE#2, BE#3
OE#
32
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 30: F
LASH
B
ANK
1, S
OFTWARE
ID E
XIT
FIGURE 31: F
LASH
B
ANK
2, S
OFTWARE
ID E
XIT
327 ILL F09a.3
ADDRESS A14-0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
Three-Byte Sequence for
Software ID Exit
BE#2, BE#3, OE#
BE#1
AA
55
F0
327 ILL F09b.4
ADDRESS A14-0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
BE#1 , BE#3, OE#
BE#1
AA
55
F0
Three-Byte Sequence for
Software ID Exit
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
33
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 32: E
2
B
ANK
, S
OFTWARE
ID E
XIT
FIGURE 33: F
LASH
B
ANK
1, CFI E
NTRY
AND
R
EAD
327 ILL F09c.4
ADDRESS A14 -0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
BE#1 , BE#3, OE#
BE#1
AA
55
F0
Three-Byte Sequence for
Software ID Exit
327 ILL F10a.2
ADDRESS A14-0
TIDA
DQ15-0
WE#
OE#
SW0
SW1
SW2
5555
2AAA
5555
0010
0011
BE#1
Three-Byte Sequence for
CFI Entry
TWP
TWPH
TAA
0051
0052
55
AA
98
BE#2, BE#3
34
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 34: F
LASH
B
ANK
2, CFI E
NTRY
AND
R
EAD
FIGURE 35: E
2
B
ANK
, CFI E
NTRY
AND
R
EAD
327 ILL F10b.3
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0
SW1
SW2
5555
2AAA
5555
0010
0011
BE#2
Three-Byte Sequence for
CFI Entry
TWP
TWPH
TAA
0051
0052
55
AA
98
OE#
BE#1, BE#3
327 ILL F10c.3
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0
SW1
SW2
5555
2AAA
5555
0010
0011
BE#3
Three-Byte Sequence for
CFI Entry
TWP
TWPH
TAA
0051
0052
55
AA
98
BE#2, BE#3
OE#
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
35
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 36: F
LASH
B
ANK
1, CFI E
XIT
FIGURE 37: F
LASH
B
ANK
2, CFI E
XIT
327 ILL F11a.2
ADDRESS A14-0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
BE#2, BE#3, OE#
BE#1
AA
55
F0
Three-Byte Sequence for
CFI Exit
327 ILL F11b.3
ADDRESS A14-0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
BE#1 , BE#3, OE#
BE#1
AA
55
F0
Three-Byte Sequence for
CFI Exit
36
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 38: E
2
B
ANK
, CFI E
XIT
FIGURE 39: E
2
B
ANK
, OTP E
NABLE
327 ILL F11c.3
ADDRESS A14 -0
DQ15-0
TIDA
TWP
T WPH
WE#
SW0
SW1
SW2
5555
2AAA
5555
BE#1 , BE#3, OE#
BE#1
AA
55
F0
Three-Byte Sequence for
CFI Exit
327 ILL F12.2
ADDRESS A14 -0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
5555
2AAA
2AAA
5555
5555
55
70
55
AA
80
AA
5555
BE#1, BE#2, OE#
BE#3
SIX-BYTE CODE FOR OTP ENABLE
TBPE
TWP
TAH
TAS
TWPH
TDH
TDS
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
37
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 40: W
RITE
O
PERATION
S
TATUS
R
EAD
FIGURE 41: T
IMING
D
IAGRAM
TO
A
LTERNATE
B
ETWEEN
E
ACH
M
EMORY
B
ANK
327 ILL F13.3
ADDRESS A18-0
DQ15-0
BE#1, BE#2, WE#
OE#
BE#3
TBE
TRC
TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ
TOH
DATA VALID
5XXXX
327 ILL F25.1
ADDRESS A18-0
TBS
DQ15-0
BE#i
BE#i
WE#
OE#
Note: i = 1, 2, 3
38
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 42: AC I
NPUT
/O
UTPUT
R
EFERENCE
W
AVEFORMS
FIGURE 43: A T
EST
L
OAD
E
XAMPLE
327 ILL F14.3
REFERENCE POINTS
OUTPUT
INPUT
VIT
VIHT
VILT
VOT
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic "1" and V
ILT
(0.1 V
DD
) for a logic "0". Measurement reference points
for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input rise and fall times (10%
90%) are <10 ns.
Note: V
IT
- V
INPUT
Test
V
OT
- V
OUTPUT
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
327 ILL F15.3
TO TESTER
TO DUT
CL
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
39
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 44: B
ANK
-E
RASE
F
LOWCHART
Memory Bank
Bank-Erase
Start
Software Data Protect
Bank-Erase
Command
Wait for End-of-Erase
(T
BEE
, T
BEF
, Data #
Polling, or Toggle Bit)
Bank-Erase Complete
327 ILL F16.3
40
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 45: F
LASH
B
ANK
B
LOCK
-E
RASE
F
LOWCHART
Flash Bank
Block-Erase
Start
Software Data Protect
Block-Erase
Flash Bank Command
Set Block Address
Wait for End-of-Erase
(T
LEF
, Data #
Polling, or Toggle Bit)
327 ILL F17.5
Flash Bank
Block-Erase Complete
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
41
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 46: E
2
B
ANK
S
ECTOR
-E
RASE
F
LOWCHART
E2 Bank
Sector-Erase
Start
Software Data Protect
Sector-Erase
Flash Bank Command
Set Sector Address
Wait for End-of-Erase
(T
SEE
, Data #
Polling, or Toggle Bit)
327 ILL F18.5
E2 Bank
Sector-Erase Complete
42
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 47: F
LASH
B
ANK
S
ECTOR
-E
RASE
F
LOWCHART
Flash Bank
Sector-Erase
Start
Software Data Protect
Sector-Erase
Flash Bank Command
Set Sector Address
Wait for End-of-Erase
(T
SEF
, Data #
Polling, or Toggle Bit)
327 ILL F19.5
Flash Bank
Sector-Erase Complete
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
43
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 48: E
2
B
ANK
W
ORD
-W
RITE
F
LOWCHART
E2 Bank
Word-Write
Start
Software Data Protect
Write
E2 Bank Command
Set Word Address
Load Word Data
E2 Bank Word-Write
Complete
327 ILL F20.4
Wait for End-of-Write
(T
WC
, Polling,
or Toggle Bit)
44
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 49: F
LASH
B
ANK
W
ORD
-P
ROGRAM
F
LOWCHART
Flash Bank
Word-Program
Start
Software Data Protect
Program
Flash Bank Command
Set Word Address
Load Word Data
Flash Bank Word-Program
Complete
327 ILL F21.3
Wait for End of Program
(T
BPF
, Data # Polling,
or Toggle Bit)
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
45
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 50: E
2
B
ANK
W
ORD
-P
ROGRAM
F
LOWCHART
E2 Bank
Word-Program
Start
Software Data Protect
Program
E2 Bank Command
Set Word Address
Load Word Data
E2 Bank Word-Program
Complete
327 ILL F22.3
Wait for End of Program
(T
BPE
, Data # Polling,
or Toggle Bit)
46
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 51: E
ND
-
OF
-W
RITE
, E
RASE
,
OR
P
ROGRAM
W
AIT
O
PTIONS
F
LOWCHART
Internal
Timer
Erase, Program,
or Write Operation
Initiated
327 ILL F23.1
Wait TWC, TBPE, TBPF,
TSEF, TLEF, TBEF,
TSEE or TBEE
Erase, Program, or
Write Completed
Toggle Bit
Data# Polling
Erase, Program,
or Write Operation
Initiated
Read a word from a bank,
block, sector, or word
selected
Read the same
word again
Is DQ6 the same?
No
No
Yes
Erase, Program,
or Write Operation
Initiated
Read DQ7 of the last
address set (or any address
within selected bank,
block, sector for erase)
Erase, Program, or
Write Completed
Erase, Program, or
Write Completed
Is DQ7 same
as bit loaded?
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
47
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
FIGURE 52: C
ONCURRENT
O
PERATION
F
LOWCHART
327 ILL F24.1
Load SDP
Command
Sequence
Concurrent
Operation
Flash
Program/Erase or
E2 Write Initiated
Wait for
End-of-Write
Indication
Flash Operation
Completed
End Concurrent
Operation
Read
Another Bank
End
Wait
48
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
SST38VF166 Valid combinations
SST38VF166-70-4C-EK
Example:
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to
confirm availability of valid combinations and to determine availability of new combinations.
Device
Speed
Suffix1
Suffix2
SST38VF166
-
XXX
-
XX
-
XX
Package Modifier
K = 48 balls
Package Type
E = TSOP (12mm x 20mm)
Temperature Range
C = Commercial = 0C to +70C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Voltage
V = 2.7-3.6V
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
49
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
PACKAGING DIAGRAMS
48-P
IN
T
HIN
S
MALL
O
UTLINE
P
ACKAGE
(TSOP) 12
MM
X
20
MM
SST P
ACKAGE
C
ODE
: EK
48.TSOP-EK-ILL.5
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
12.20
11.80
.270
.170
1.05
0.95
.50
BSC
0.15
0.05
18.50
18.30
20.20
19.80
0.70
0.50
Pin # 1 Identifier
50
Data Sheet
16 Megabit FlashBank Memory
SST38VF166
2001 Silicon Storage Technology, Inc.
327-3 2/01
S71065
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, CA 94086 Telephone 408-735-9110 Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
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