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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

SST39SF512 / SST39SF010

FEATURES:

Organized as 64K x8 / 128K x8

Single 5.0V Read and Write Operations

Superior Reliability

Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 20 mA (typical)
Standby Current: 10 µA (typical)

Sector-Erase Capability

Uniform 4 KByte sectors

Fast Read Access Time:

70 ns
90 ns

Latched Address and Data

Fast Erase and Byte-Program:

Sector-Erase Time: 7 ms (typical)
Chip-Erase Time: 15 ms (typical)
Byte-Program Time: 20 µs (typical)
Chip Rewrite Time:

2 seconds (typical) for SST39SF512
3 seconds (typical) for SST39SF010

Automatic Write Timing

Internal V

Generation

End-of-Write Detection

Toggle Bit
Data# Polling

TTL I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF512/010 are CMOS Multi-Purpose Flash
(MPF) manufactured with SST's proprietary, high perfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate
approaches. The SST39SF512/010 devices write (Pro-
gram or Erase) with a 5.0V-only power supply. The
SST39SF512/010 device conforms to JEDEC standard
pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST39SF512/010 devices provide a maximum Byte-Pro-
gram time of 30 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.

The SST39SF512/010 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.

To meet high density, surface mount requirements, the
SST39SF512/010 are offered in 32-pin PLCC packages,
32-pin TSOP, and a 600 mil, 32-pin PDIP is also available.
See Figures 1, 2, and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#

SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

S71149-03-000

4/01

394

low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39SF512/010 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is deselected and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 4).

Byte-Program Operation

The SST39SF512/010 are programmed on a byte-by-byte
basis. The Program operation consists of three steps. The
first step is the three-byte-load sequence for Software Data
Protection. The second step is to load byte address and
byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 30 µs. See Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 15 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte-com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The end of Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.

Chip-Erase Operation

The SST39SF512/010 provide Chip-Erase operation,
which allows the user to erase the entire memory array to
the "1s" state. This is useful when the entire device must be
quickly erased.

The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 4 for the command sequence,
Figure 10 for timing diagram, and Figure 18 for the flow-
chart. Any commands written during the Chip-Erase opera-
tion will be ignored.

Write Operation Status Detection

The SST39SF512/010 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ

) and Toggle Bit (DQ

). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-
tiates the program or erase cycle.

The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ

or DQ

. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.

Data# Polling (DQ

)

When the SST39SF512/010 are in the internal Program
operation, any attempt to read DQ

will produce the com-

plement of the true data. Once the Program operation is
completed, DQ

will produce true data. The device is then

ready for the next operation. During internal Erase opera-
tion, any attempt to read DQ

will produce a `0'. Once the

internal Erase operation is completed, DQ

will produce a

`1'. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program Operation. For sector or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010

S71149-03-000

4/01

394

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-
secutive attempts to read DQ

will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with "1". When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39SF512/010 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.

Power Up/Down Detection: The write operation is

inhibited when V

is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39SF512/010 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three byte sequence.
The three byte-load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six byte load sequence. The SST39SF512 device is
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within T

Product Identification

The product identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software product identification operation
to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Table 3 for hardware operation or Table 4 for software oper-
ation, Figure 11 for the software ID entry and read timing
diagram and Figure 17 for the ID entry command
sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.

TABLE

1: P

RODUCT

DENTIFICATION

Address

Data

Manufacturer's ID

0000H

BFH

Device ID

SST39LF/VF512

0001H

B4H

SST39LF/VF010

0001H

B5H

T1.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010

S71149-03-000

4/01

394

FIGURE 2: P

SSIGNMENTS

FOR

32-

PIN

TSOP (8

)

FIGURE 3: P

SSIGNMENTS

FOR

32-

PIN

PDIP

A11

A9
A8

A13
A14

WE#

VDD

NC
NC

A15
A12

A7
A6
A5
A4

A11

A9
A8

A13
A14

WE#

VDD

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

394 ILL F01.2

Standard Pinout

Top View

Die Up

SST39SF512

SST39SF010

SST39SF512 SST39SF010

32-pin

PDIP

Top View

394 ILL F02a.3

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF512

SST39SF010

SST39SF512 SST39SF010

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD
WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

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