Preliminary Specifications
2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
8 Mbit (x8) Multi-Purpose Flash
SST39VF088
FEATURES:
Organized as 1M x8
Single Voltage Read and Write Operations
2.7-3.6V
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption (typical values at 5 MHz)
Active Current: 12 mA (typical)
Standby Current: 4 A (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Block-Erase Capability
Uniform 64 KByte blocks
Fast Read Access Time:
70 and 90 ns
Latched Address and Data
Fast Erase and Byte-Program
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 s (typical)
Chip Rewrite Time: 15 seconds (typical)
Automatic Write Timing
Internal V
PP
Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
48-lead TSOP (12mm x 20mm)
PRODUCT DESCRIPTION
The SST39VF088 device is a 1M x8 CMOS Multi-Purpose
Flash (MPF) manufactured with SST's proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39VF088 writes (Program or Erase)
with a 2.7-3.6V power supply. It conforms to JEDEC stan-
dard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39VF088 device provides a typical Byte-Program time
of 14 sec. The devices use Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
The SST39VF088 device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. They
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39VF088 is offered in 48-lead TSOP packaging. See
Figure 1 for pin assignments.
SST39VF0882.7V 8Mb (x8) MPF memory
2
Preliminary Specifications
8 Mbit Multi-Purpose Flash
SST39VF088
2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39VF088 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 2).
Byte-Program Operation
The SST39VF088 is programmed on a byte-by-byte basis.
Before programming, the sector where the byte exists must
be fully erased. The Program operation is accomplished in
three steps. The first step is the three-byte load sequence
for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or
CE#, whichever occurs first. The Program operation, once
initiated, will be completed within 20 s. See Figures 3 and
4 for WE# and CE# controlled Program operation timing
diagrams and Figure 13 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF088 offers both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 4 KByte. The Block-Erase mode
is based on uniform block size of 64 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (50H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 8 and 9 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39VF088 provides a Chip-Erase operation, which
allows the user to erase the entire memory array to the "1"
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address AAAH in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 7 for timing diagram,
and Figure 16 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST39VF088 provides two software means to detect
the completion of a write (Program or Erase) cycle, in order
to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
) and
Toggle Bit (DQ
6
). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Preliminary Specifications
8 Mbit Multi-Purpose Flash
SST39VF088
3
2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Data# Polling (DQ
7
)
When the SST39VF088 is in the internal Program opera-
tion, any attempt to read DQ
7
will produce the complement
of the true data. Once the Program operation is completed,
DQ
7
will produce true data. Note that even though DQ
7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 s. During internal Erase operation, any
attempt to read DQ
7
will produce a `0'. Once the internal
Erase operation is completed, DQ
7
will produce a `1'. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling
timing diagram and Figure 14 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle
Bit timing diagram and Figure 14 for a flowchart.
Data Protection
The SST39VF088 provides both hardware and software
features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF088 provides the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. The SST39VF088 device is shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within T
RC.
4
Preliminary Specifications
8 Mbit Multi-Purpose Flash
SST39VF088
2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
Product Identification
The Product Identification mode identifies the device as the
SST39VF088 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 10 for the Software ID Entry and Read
timing diagram and Figure 15 for the Software ID Entry
command sequence flowchart.
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 4 for software command codes and
Figure 15 for a flowchart.
TABLE
1: P
RODUCT
I
DENTIFICATION
Address
Data
Manufacturer's ID
0000H
BFH
Device ID
SST39VF088
0001H
D8H
T1.0 1227
Y-Decoder
I/O Buffers and Data Latches
1227 B1.0
Address Buffer & Latches
X-Decoder
DQ7 - DQ0
Memory
Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
F
UNCTIONAL
B
LOCK
D
IAGRAM
Preliminary Specifications
8 Mbit Multi-Purpose Flash
SST39VF088
5
2003 Silicon Storage Technology, Inc.
S71227-04-000
11/03
FIGURE 1: P
IN
A
SSIGNMENTS
FOR
48-
LEAD
TSOP
TABLE
2: P
IN
D
ESCRIPTION
Symbol
Pin Name
Functions
A
MS
1
-A
0
1. A
MS
= Most significant address
A
MS
= A
19
for SST39VF088
Address Inputs
To provide memory addresses. During Sector-Erase A
MS
-A
12
address lines will select the
sector. During Block-Erase A
MS
-A
16
address lines will select the block.
DQ
7
-DQ
0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
V
DD
Power Supply
To provide power supply voltage:
2.7-3.6V for SST39VF088
V
SS
Ground
NC
No Connection
Unconnected pins.
T2.0 1227
A16
A15
A14
A13
A12
A11
A10
A9
NC
NC
WE#
NC
NC
NC
NC
A19
A18
A8
A7
A6
A5
A4
A3
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A17
NC
VSS
A0
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
VDD
NC
DQ3
NC
DQ2
NC
DQ1
NC
DQ0
OE#
VSS
CE#
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1227 48-tsop P01.0
Standard Pinout
Top View
Die Up
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