www.statschippac.com
FEATURES
Body sizes: 4 x 4mm to 9 x 9mm
Lead pitch: 0.50mm and 0.80mm
Custom body / lead / pitch configurations available
Package profile heights (overall): maximum 0.80mm
Both single row & dual row design
Ni / Pd / Au plated bumps
Excellent thermal and electrical performance
Full in-house package and leadframe design capability
Full in-house electrical, thermal and mechanical
simulation and measurement capability
JEDEC standard compliant
APPLICATIONS
RF
Power Management
Analog/Linear
Logic
Applications requiring enhanced electrical and thermal
performance and reduced package size and weight
Saw singulated format
Package height 0.8mm max.
Square body size (rectangular body designable)
Staggered dual row or single row bump design
DESCRIPTION
STATS ChipPAC's Bump Chip Carrier (BCC) technology pro-
duces a chip scale leadframe based molded package with
bumps which are formed after the leadframe is etched away.
An exposed die pad coupled with extremely low RLC provides
excellent electrical and thermal performance enhancements
which are ideal for high frequency and high power applica-
tions especially for handheld portable applications such as
cell phones. The BCC is manufactured in a molded array
format that maximizes product throughput and material
utilization. The BCC is available with single row and dual row
bumps in BCC++ and BCC+. Overall package profile height is
0.80mm maximum.
BCC
Bump Chip Carrier
BCC++ (exposed paddle with ground ring)
BCC+ (exposed paddle without ground ring)
BCCs++ (staggered dual row design)
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks
of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information
will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document.
STATS ChipPAC reserves the right to change the information at any time and without notice.
Copyright 2006. STATS ChipPAC Ltd. All rights reserved.
May 2006
Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823
Global Offices USA 510-979-8000 JAPAN 81-3-5789-5850 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222
KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 31-38-333-2023
BCC
Bump Chip Carrier
SPECIFICATIONS
Die Thickness
279
m nominal, 355
m max.
Gold Wire
25
m (1.0mils) diameter
Lead Finish
Preplated Ni/Pd/Au bumps
Marking
Laser
Packing Options
Tape & reel / JEDEC tray
RELIABILITY
Moisture Sensitivity Level
JEDEC Level 2a/2/1@260C
(depending upon package)
Temperature Cycling
-65C/150C, 1000 cycles
High Temp Storage
150C, 1000 hrs
Temp / Humidity Test
85C/85% RH, 1000 cycles
Pressure Cooker Test
121C, 100% RH, 2 atm,
168 hrs
CROSS-SECTIONS
PACKAGE CONFIGURATIONS
Package Size
Lead Pitch
Lead Count
(mm)
(mm)
4 x 4
0.80
16
5 x 5
0.50
32
6 x 6
0.50
40
7 x 7
0.50
48 / 84
8 x 8
0.50
56
9 x 9
0.50
11 6
BCC+
BCC++
BCCs++
BCCs+
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