AI00769B
14
A0-A13
P
Q0-Q7
VPP
VCC
M27128A
G
E
VSS
8
Figure 1. Logic Diagram
M27128A
NMOS 128K (16K x 8) UV EPROM
FAST ACCESS TIME: 200ns
EXTENDED TEMPERATURE RANGE
SINGLE 5 V SUPPLY VOLTAGE
LOW STANDBY CURRENT: 40mA max
TTL COMPATIBLE DURING READ and
PROGRAM
FAST PROGRAMMING ALGORITHM
ELECTRONIC SIGNATURE
PROGRAMMING VOLTAGE: 12V
DESCRIPTION
The M27128A is a 131,072 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 16,384 words by 8 bits.
The M27128A is housed in a 28 Pin Window Ce-
ramic Frit-Seal Dual-in-Line package. The trans-
parent lid allows the user to expose the chip to
ultraviolet light to erase the bit pattern. A new
pattern can then be written to the device by follow-
ing the programming procedure.
A0 - A13
Address Inputs
Q0 - Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
1
28
FDIP28W (F)
March 1995
1/10
Q2
VSS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
E
Q3
A11
Q7
Q6
Q4
A13
P
A12
A4
VPP
VCC
A7
AI00770
M27128A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
20
19
18
17
16
15
A6
A5
A9
A8
28
27
26
25
24
23
22
21
Figure 2. DIP Pin Connections
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
grade 1
grade 6
0 to 70
40 to 85
C
T
BIAS
Temperature Under Bias
grade 1
grade 6
10 to 80
50 to 95
C
T
STG
Storage Temperature
65 to 125
C
V
IO
Input or Output Voltages
0.6 to 6.25
V
V
CC
Supply Voltage
0.6 to 6.25
V
V
A9
A9 Voltage
0.6 to 13.5
V
V
PP
Program Supply
0.6 to 14
V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
DEVICE OPERATION
The seven modes of operation of the M27128A are
listed in the Operating Modes table. A single 5V
power supply is required in the read mode. All
inputs are TTL levels except for V
PP
and 12V on A9
for Electronic Signature.
Read Mode
The M27128A has two control functions, both of
which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, inde-
pendent of device selection.
Assuming that the addresses are stable, address
access time (t
AVQV
) is equal to the delay from E to
output (t
ELQV
). Data is available at the outputs after
the falling edge of G, assuming that E has been low
and the addresses have been stable for at least
t
AVQV
-t
GLQV
.
Standby Mode
The M27128A has a standby mode which reduces
the maximum active power current from 85mA to
40mA. The M27128A is placed in the standby mode
by applying a TTL high signal to the E input. When
in the standby mode, the outputs are in a high
impedance state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
2/10
M27128A
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus.
This ensures that all deselected memory devices
are in their low power standby mode and that the
output pins are only active when data is required
from a particular memory device.
System Considerations
The power switching characteristics of fast
EPROMs require careful decoupling of the devices.
The supply current, I
CC
, has three segments that
are of interest to the system designer: the standby
current level, the active current level, and transient
current peaks that are produced by the falling and
rising edges of E. The magnitude of this transient
current peaks is dependent on the capacitive and
inductive loading of the device at the output. The
associated transient voltage peaks can be sup-
pressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a
1
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
F bulk electrolytic capacitor should be used
between V
CC
and GND for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
Programming
When delivered (and after each erasure for UV
EPPROM), all bits of the M27128A are in the "1"
state. Data is introduced by selectively program-
ming "0s" into the desired bit locations. Although
only "0s" will be programmed, both "1s" and "0s"
can be present in the data word. The only way to
change a "0" to a "1" is by ultraviolet light erasure.
The M27128A is in the programming mode when
V
PP
input is at 12.5V and E and P are at TTL low.
The data to be programmed is applied 8 bits in
parallel, to the data output pins. The levels required
for the address and data inputs are TTL.
Fast Programming Algorithm
Fast Programming Algorithm rapidly programs
M27128A EPROMs using an efficient and reliable
method suited to the production programming en-
vironment. Programming reliability is also ensured
as the incremental program margin of each byte is
Mode
E
G
P
A9
V
PP
Q0 - Q7
Read
V
IL
V
IL
V
IH
X
V
CC
Data Out
Output Disable
V
IL
V
IH
V
IH
X
V
CC
Hi-Z
Program
V
IL
V
IH
V
IL
Pulse
X
V
PP
Data In
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Out
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes Out
Note: X = V
IH
or V
IL
, V
ID
= 12V
0.5%.
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
0
0
1
0
0
1
89h
Table 4. Electronic Signature
DEVICE OPERATION (cont'd)
3/10
M27128A
AI00827
2.4V
0.45V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveforms
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.45V to 2.4V
Input and Output Timing Ref. Voltages
0.8V to 2.0V
AC MEASUREMENT CONDITIONS
AI00828
1.3V
OUT
CL = 100pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
=
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
=
12
pF
Note: 1. Sampled only, not 100% tested.
Table 5. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
AI00771
tAXQX
tEHQZ
DATA OUT
A0-A13
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
Figure 5. Read Mode AC Waveforms
4/10
M27128A
Symbol
Alt
Parameter
Test
Condition
M27128A
Unit
-2, -20
blank, -25
-3, -30
-4
Min
Max
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
,
G = V
IL
200
250
300
450
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
200
250
300
450
ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
75
100
120
150
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
55
0
60
0
105
0
130
ns
t
GHQZ
(2)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0
55
0
60
0
105
0
130
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
,
G = V
IL
0
0
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
Table 7. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
CC
10
A
I
LO
Output Leakage Current
V
OUT
= V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
75
mA
I
CC1
Supply Current (Standby)
E = V
IH
35
mA
I
PP
Program Current
V
PP
= V
CC
5
mA
V
IL
Input Low Voltage
0.1
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
=
0.45
V
V
OH
Output High Voltage
I
OH
= 400
A
2.4
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
Table 6. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 5V
5% or 5V
10%; V
PP
= V
CC
)
5/10
M27128A
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