AI00834B
13
A0-A12
P
Q0-Q7
VPP
VCC
M27C64A
G
E
VSS
8
Figure 1. Logic Diagram
March 1995
M27C64A
64K (8K x 8) UV EPROM and OTP ROM
VERY FAST ACCESS TIME: 150ns
COMPATIBLE with HIGH SPEED
MICROPROCESSORS, ZERO WAIT STATE
LOW POWER "CMOS" CONSUMPTION:
Active Current 30mA
Standby Current 100
A
PROGRAMMING VOLTAGE: 12.5V
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
HIGH SPEED PROGRAMMING
(less than 1 minute)
DESCRIPTION
The M27C64A is a high speed 65,536 bit UV eras-
able and electrically programmable memory
EPROM ideally suited for microprocessor systems
requiring large programs. It is organized as 8,192
by 8 bits.
The 28 pin Window Ceramic Frit-Seal Dual-in-Line
package has transparent lid which allows the user
to expose the chip to ultraviolet light to erase the
bit pattern. Anew pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only on time and erasure is not required, the
M27C64A is offered in Plastic Leaded Chip Carrier
package.
A0 - A12
Address Inputs
Q0 - Q7
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
PLCC32 (C)
1
28
FDIP28W (F)
1/11
Q2
VSS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
E
Q3
A11
Q7
Q6
Q4
NC
P
A12
A4
VPP
VCC
A7
AI00835
M27C64A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
20
19
18
17
16
15
A6
A5
A9
A8
28
27
26
25
24
23
22
21
Figure 2A. DIP Pin Connections
Warning: NC = Not Connected
AI00836
NC
A8
A10
Q4
17
A0
NC
Q0
Q1
Q2
DU
Q3
A6
A3
A2
A1
A5
A4
9
P
A9
1
V
PP
A11
Q6
A7
Q7
32
DU
V
CC
M27C64A
A12
NC
Q5
G
E
25
V
SS
Figure 2B. LCC Pin Connections
Warning: NC = Not Connected, DU = Don't Use
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
40 to 125
C
T
BIAS
Temperature Under Bias
50 to 125
C
T
STG
Storage Temperature
65 to 150
C
V
IO (2)
Input or Output Voltages (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
Table 2. Absolute Maximum Ratings
(1)
DEVICE OPERATION
The modes of operation of the M27C64A are listed
in the Operating Modes table. A single 5V power
supply is required in the read mode. All inputs are
TTL levels except for V
PP
and 12V on A9 for Elec-
tronic Signature.
Read Mode
The M27C64A has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
2/11
M27C64A
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output (t
ELQV
).
Data is available at the output after a delay of t
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C64A has a standby mode which reduces
the active current from 30mA to 100
A. The
M27C64A is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high impedance
state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
F bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
Mode
E
G
P
A9
V
PP
Q0 - Q7
Read
V
IL
V
IL
V
IH
X
V
CC
Data Out
Output Disable
V
IL
V
IH
V
IH
X
V
CC
Hi-Z
Program
V
IL
V
IH
V
IL
Pulse
X
V
PP
Data In
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Out
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Note: X = V
IH
or V
IL
, V
ID
= 12V
0.5V
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
1
0
0
1
1
0
1
1
9Bh
Device Code
V
IH
0
0
0
0
1
0
0
0
08h
Table 4. Electronic Signature
3/11
M27C64A
AI00826
2.4V
0.4V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveforms
Input Rise and Fall Times
20ns
Input Pulse Voltages
0.4 to 2.4V
Input and Output Timing Ref. Voltages
0.8 to 2.0V
AC MEASUREMENT CONDITIONS
AI00828
1.3V
OUT
CL = 100pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 5. Capacitance
(1)
(T
A
= 25
C, f = 1 MHz )
AI00778
tAXQX
tEHQZ
DATA OUT
A0-A12
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
Figure 5. Read Mode AC Waveforms
4/11
M27C64A
Symbol
Alt
Parameter
Test Condition
M27C64A
Unit
-15
-20
-25
-30
Min Max Min Max Min Max Min Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
150
200
250
300
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
150
200
250
300
ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
75
80
100
120
ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
50
0
50
0
60
0
105
ns
t
GHQZ
(2)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0
50
0
50
0
60
0
105
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP.
2. Sampled only, not 100% tested.
Table 7. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C: V
CC
= 5V
10%; V
PP
= V
CC
)
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
10
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
10
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
30
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
0.2V
100
A
I
PP
Program Current
V
PP
= V
CC
100
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
A
2.4
V
Output High Voltage CMOS
I
OH
= 100
A
V
CC
0.7V
V
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 6. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C: V
CC
= 5V
10%; V
PP
= V
CC
)
5/11
M27C64A
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