M54HC164
M74HC164
October 1992
8 BIT SIPO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES :
M54HC164F1R
M74HC164M1R
M74HC164B1R
M74HC164C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
.
HIGH SPEED
t
PD
= 15 ns (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX.) AT T
A
= 25
C
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
I
OH
= 4 mA (MIN.)
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS164
DESCRIPTION
The M54/74HC164 is a high speed CMOS 8 BIT
SIPO SHIFT REGISTER fabricated in silicon gate
C
2
MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
The HC164 is an 8 bit shift register with serial data
entry and an output from each of the eight stages.
Data is entered serially through one of two inputs (A
or B), either of these inputs can be used as an active
high enable for data entry through the other input.
An unused input must be high, or both inputs con-
nected together. Each low-to-high transition on the
clock input shifts data one place to the right and
enters into QA, the logic NAND of the two data inputs
(A
B), the data that existed before the rising clock
edge. A low level on the clear input overrides all
other inputs and clears the register asynchronously,
forcing all Q outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
1/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
OUTPUS
CLEAR
CLOCK
SERIAL IN
QA
QB
............
QH
A
B
L
X
X
X
L
L
............
L
H
X
X
NO CHANGE
H
L
X
L
QAn
............
QGn
H
X
L
L
QAn
............
QGn
H
H
H
H
QAn
............
QGn
X: Don't Care
QAn - QGn : The level of QA -QG, respectively. before the most-recent transition of th clock.
LOGIC DIAGRAM
M54/M74HC164
2/12
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1, 2
A, B
Data Inputs
3, 4, 5, 6,
10, 11, 12,
13
QA to QH
Outputs
8
CLOCK
Clock Input (LOW to
HIGH, Edge-triggered)
9
CLEAR
Master Reset Input
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
V
CC
= 6 V
0 to 400
M54/M74HC164
3/12
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
t
PLH
t
PHL
Propagation
Delay Time
(CLOCK - Q)
2.0
57
160
200
240
ns
4.5
19
32
40
48
6.0
16
27
34
41
t
PHL
Propagation
Delay Time
(CLEAR - Q)
2.0
60
175
220
265
ns
4.5
20
35
44
53
6.0
17
30
37
45
f
MAX
Maximum Clock
Frequency
2.0
6.2
18
5.0
4.2
MHz
4.5
31
53
25
21
6.0
37
62
30
25
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
2.0
24
75
95
110
ns
4.5
6
15
19
22
6.0
5
13
16
19
t
W(L)
Minimum Pulse
Width
(CLEAR)
2.0
40
75
95
110
ns
4.5
10
15
19
22
6.0
9
13
16
19
t
s
Minimum Set-up
Time
(A, B - CK)
2.0
16
50
65
75
ns
4.5
4
10
13
15
6.0
3
9
11
13
t
h
Minimum Hold
Time
(A, B - CK)
2.0
5
5
5
ns
4.5
5
5
5
6.0
5
5
5
t
REM
Minimum
Removal Time
2.0
5
5
5
ns
4.5
5
5
5
6.0
5
5
5
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
(*)
Power Dissipation
Capacitance
99
pF
(*) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
M54/M74HC164
5/12
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