1/11
April 2001
s
HIGH SPEED:
f
MAX
= 190MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT273 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Information signals applied to D inputs are
transfered to the Q output on the positive-going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ACT273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
74ACT273B
SOP
74ACT273M
74ACT273MTR
TSSOP
74ACT273TTR
TSSOP
DIP
SOP
74ACT273
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asyncronous Master Reset
(Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
Flip-Flop Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
CLOCK
Clock Input (LOW-to-HIGH
Edge Triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
FUNCTION
CLEAR
D
CLOCK
Q
L
X
X
L
CLEAR
H
L
L
H
H
H
H
X
Q
n
NO CHANGE
74ACT273
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
74ACT273
4/11
DC SPECIFICATIONS
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
2.0
1.5
2.0
2.0
V
5.5
2.0
1.5
2.0
2.0
V
IL
Low Level Input
Voltage
4.5
V
O
= 0.1 V or
V
CC
-0.1V
1.5
0.8
0.8
0.8
5.5
1.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.49
4.4
4.4
5.5
I
O
=-50
A
5.4
5.49
5.4
5.4
4.5
I
O
=-24 mA
3.86
3.76
3.7
V
5.5
I
O
=-24 mA
4.86
4.76
4.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.001
0.1
0.1
0.1
5.5
I
O
=50
A
0.001
0.1
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
0.5
5.5
I
O
=24 mA
0.36
0.44
0.5
I
I
Input Leakage Cur-
rent
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
- 2.1V
0.6
1.5
1.6
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
80
A
I
OLD
Dynamic Output
Current (note 1, 2)
5.5
V
OLD
= 1.65 V max
75
50
mA
I
OHD
V
OHD
= 3.85 V min
-75
-50
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CLOCK to Y
5.0
(*)
1.5
4.0
8.5
1.5
9.0
1.5
9.0
ns
t
PHL
Propagation Delay
Time CLEAR to Y
5.0
(*)
1.5
4.5
9.0
1.5
9.5
1.5
9.5
ns
t
WL
CLEAR Pulse
Width
5.0
(*)
2.3
4.0
4.0
4.0
ns
t
W
CLOCK Pulse
Width
5.0
(*)
1.8
4.0
4.0
4.0
ns
t
s
Setup Time D to
CLOCK, HIGH or
LOW
5.0
(*)
1.0
3.5
3.5
3.5
ns
t
h
Hold Time D to
CLOCK, HIGH or
LOW
5.0
(*)
-0.5
1.5
1.5
1.5
ns
t
REM
Recovery Time
CLEAR to CLOCK
5.0
(*)
0.5
3.0
3.0
3.0
ns
f
MAX
Maximum CLOCK
Frequency
5.0
(*)
125
190
110
110
MHz
74ACT273
5/11
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
4
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
f
IN
= 10MHz
32
pF
74ACT273
6/11
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74ACT273
7/11
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
74ACT273
8/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.254
0.010
B
1.39
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
0.130
Z
1.34
0.053
P001J
Plastic DIP-20 (0.25) MECHANICAL DATA
74ACT273
9/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.10
0.20
0.004
0.007
a2
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
M
0.75
0.029
S
8 (max.)
P013L
SO-20 MECHANICAL DATA
74ACT273
10/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.2
0.0035
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
o
4
o
8
o
0
o
4
o
8
o
L
0.50
0.60
0.70
0.020
0.024
0.028
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
TSSOP20 MECHANICAL DATA
74ACT273
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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11/11
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