74ACT574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
February 2000
s
HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at V
CC
= 3.3V
s
LOW POWER DISSIPATION:
I
CC
= 8
A (MAX.) at T
A
= 25
o
C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT574 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT
NON
INVERTING
fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
The device is designed to interface directly High
Speed CMOS system with TTL and NMOS
components.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
DIP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
DIP
M74ACT574B
SOP
M74ACT574M
M74ACT574MTR
TSSOP
M74ACT574TTR
1/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PI N No
SYMBOL
NAME AND FUNCT ION
1
OE
3 State Output Enable
Input (Active LOW)
2, 3, 4,
5, 6, 7,
8, 9
D0 to D7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7
3 State Outputs
11
CLOCK
Clock Input (LOW to
HIGH, edge triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUT PUTS
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
X:DON'T CARE
Z: HIGH IMPEDANCE
LOGIC DIAGRAMS
74ACT574
2/11
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
400
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature:
-40 to +85
o
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
1) V
IN
from 0.8 V to 2.0 V
74ACT574
3/11
DC SPECIFICATIONS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
V
IH
High Level Input Voltage
4.5
V
O
= 0.1 V or
V
CC
- 0.1 V
2.0
1.5
2.0
V
5.5
2.0
1.5
2.0
V
IL
Low Level Input Voltage
4.5
V
O
= 0.1 V or
V
CC
- 0.1 V
1.5
0.8
0.8
V
5.5
1.5
0.8
0.8
V
OH
High Level Output
Voltage
4.5
V
I
(* )
=
V
IH
or
V
IL
I
O
=-50
A
4.4
4.49
4.4
V
5.5
I
O
=-50
A
5.4
5.49
5.4
4.5
I
O
=-24 mA
3.86
3.76
5.5
I
O
=-24 mA
4.86
4.76
V
OL
Low Level Output
Voltage
4.5
V
I
(* )
=
V
IH
or
V
IL
I
O
=50
A
0.001
0.1
0.1
V
5.5
I
O
=50 mA
0.001
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
5.5
I
O
=24 mA
0.36
0.44
I
I
Input Leakage Current
5.5
V
I
= V
CC
or GND
0.1
1
A
I
OZ
3 State Output Leakage
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
-2.1 V
0.6
1.5
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
8
80
A
I
OLD
Dynamic Output Current
(note 1, 2)
5.5
V
OLD
= 1.65 V max
75
mA
I
OHD
V
OHD
= 3.85 V min
-75
mA
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
.
(*) All outputs loaded.
74ACT574
4/11
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
C
OUT
Output Capacitance
5.0
8
pF
C
IN
Input Capacitance
5.0
4
pF
C
PD
Power Dissipation
Capacitance (note 1)
5.0
26
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/n (per circuit)
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
t
PLH
t
PHL
Propagation Delay Time
CK to Q
5.0
(*)
5.0
10.0
11.0
ns
t
PZL
t
PZH
Output Enable Time
5.0
(*)
5.5
9.0
10.0
ns
t
PLH
t
PHL
Output Disable Time
5.0
(*)
5.0
8.5
9.0
ns
t
w
CK Pulse Width, HIGH
or LOW
5.0
(*)
1.5
3.0
4.0
ns
t
s
Setup Time Q to CK
HIGH or LOW
5.0
(*)
1.0
2.5
3.0
ns
t
h
Hold Time Q to CK
HIGH or LOW
5.0
(*)
-1.0
2.5
3.0
ns
f
MAX
Maximim Clock
Frequency
5.0
(*)
100
250
85
MHz
(*) Voltage range is 5V
0.5V
74ACT574
5/11
T EST
SW IT CH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
2V
CC
t
PZH
, t
PHZ
Open
C
L
= 50 pF or equivalent (includes jigand probe capacitance)
R
L
= R
1
= 500
orequivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
TEST CIRCUIT
74ACT574
6/11
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PULSE WIDTH
74ACT574
7/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
a1
0.254
0.010
B
1.39
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
3.3
0.130
Z
1.34
0.053
P001J
Plastic DIP-20 (0.25) MECHANICAL DATA
74ACT574
8/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.10
0.20
0.004
0.007
a2
2.45
0.096
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.299
L
0.50
1.27
0.19
0.050
M
0.75
0.029
S
8 (max.)
P013L
SO-20 MECHANICAL DATA
74ACT574
9/11
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.2
0.0035
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
o
4
o
8
o
0
o
4
o
8
o
L
0.50
0.60
0.70
0.020
0.024
0.028
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
TSSOP20 MECHANICAL DATA
74ACT574
10/11
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMi croelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics products
are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.
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74ACT574
11/11
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