74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
April 1997
s
HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
= 25
o
C
s
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
50
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and
double-layer
metal
wiring
C
2
MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All
inputs and
outputs
are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74ACT74B
74ACT74M
M
(Micro Package)
B
(Plastic Package)
1/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAMS
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND F UNCTIO N
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUT PUT S
F UNCT IO N
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
X: Don't Care
This logic diagram has not be used to estimate propagation delays
74ACT74
2/11
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Uni t
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
200
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature:
-40 to +85
o
C
dt/dv
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
8
ns/V
1) V
IN
from 0.8 V to 2.0 V
74ACT74
3/11
DC SPECIFICATIONS
Symbol
Parameter
Test Con dition s
Value
Unit
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Mi n.
Typ.
Max.
Min .
Max.
V
IH
High Level Input Voltage
4.5
V
O
= 0.1 V or
V
CC
- 0.1 V
2.0
1.5
2.0
V
5.5
2.0
1.5
2.0
V
IL
Low Level Input Voltage
4.5
V
O
= 0.1 V or
V
CC
- 0.1 V
1.5
0.8
0.8
V
5.5
1.5
0.8
0.8
V
OH
High Level Output
Voltage
4.5
V
I
(*)
=
V
IH
or
V
IL
I
O
=-50
A
4.4
4.49
4.4
V
5.5
I
O
=-50
A
5.4
5.49
5.4
4.5
I
O
=-24 mA
3.86
3.76
5.5
I
O
=-24 mA
4.86
4.76
V
OL
Low Level Output
Voltage
4.5
V
I
(*)
=
V
IH
or
V
IL
I
O
=50
A
0.001
0.1
0.1
V
5.5
I
O
=50 mA
0.001
0.1
0.1
4.5
I
O
=24 mA
0.36
0.44
5.5
I
O
=24 mA
0.36
0.44
I
I
Input Leakage Current
5.5
V
I
= V
CC
or GND
0.1
1
A
I
CCT
Max I
CC
/Input
5.5
V
I
= V
CC
-2.1 V
0.6
1.5
mA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
A
I
OLD
Dynamic Output Current
(note 1, 2)
5.5
V
OLD
= 1.65 V max
75
mA
I
OHD
V
OHD
= 3.85 V min
-75
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
.
(*) All outputs loaded.
74ACT74
4/11
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Con dition s
Value
Unit
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Mi n.
Typ.
Max.
Min .
Max.
C
IN
Input Capacitance
5.0
4
pF
C
PD
Power Dissipation
Capacitance (note 1)
5.0
43
pF
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/n (per circuit)
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3 ns)
Symbol
Parameter
T est Cond iti on
Value
Unit
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Mi n.
Typ.
Max.
Min .
Max.
t
PLH
t
PHL
Propagation Delay Time
CK to Q
5.0
(*)
5.0
10.0
11.0
ns
t
PLH
t
PHL
Propagation Delay Time
PR or CLR to Q or Q
5.0
(*)
5.0
10.0
11.0
ns
t
w
CK Pulse Width, HIGH
or LOW
5.0
(*)
1.5
5.0
6.0
ns
t
s
Setup Time Q to CK
HIGH or LOW
5.0
(*)
0.5
3.0
3.5
ns
t
h
Hold Time Q to CK
HIGH or LOW
5.0
(*)
-0.5
1.0
1.0
ns
t
rem
Removal Time PR or
CLR to CK
5.0
(*)
-0.7
1.0
1.0
ns
f
MAX
Maximim Clock
Frequency
5.0
(*)
100
250
85
MHz
(*) Voltage range is 5V
0.5V
74ACT74
5/11
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