1/11
February 2003
s
3.6V TOLERANT INPUTS AND OUTPUTS
s
HIGH SPEED :
t
PD
= 4.2 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 5.3 ns (MAX.) at V
CC
= 2.3 to 2.7V
t
PD
= 6.5 ns (MAX.) at V
CC
= 1.65V
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 18mA (MIN) at V
CC
= 2.3V
|I
OH
| = I
OL
= 4mA (MIN) at V
CC
= 1.65V
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
s
BUS HOLD PROVIDED ON DATA INPUTS
s
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
s
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16374 is a low voltage CMOS 16
BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON
INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C
2
MOS
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE).
On the positive transition of the (nCK), the nQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE) input is low, the outputs (nQ) will
be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state. Any output control does not
affect the internal operation of flip flops; that is, the
old data can be retained or the new data can be
entered even while the outputs are off.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ALVCH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74ALVCH16374TTR
TSSOP
PIN CONNECTION
74ALVCH16374
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2CK
Clock Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1CK
Clock Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74ALVCH16374
3/11
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND, V
O
> V
CC
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2V at V
CC
= 3.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +4.6
V
V
I
DC Input Voltage
-0.5 to +4.6
V
V
O
DC Output Voltage (OFF State)
-0.5 to +4.6
V
V
O
DC Output Voltage (High or Low State) (note 1)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 50
mA
I
OK
DC Output Diode Current (note 2)
- 50
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current per Supply Pin
100
mA
P
D
Power Dissipation
400
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
1.65 to 3.6
V
V
I
Input Voltage
-0.3 to 3.6
V
V
O
Output Voltage (OFF State)
0 to 3.6
V
V
O
Output Voltage (High or Low State)
0 to V
CC
V
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
24
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 2.3 to 2.7V)
12
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 1.65V)
4
mA
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1)
0 to 10
ns/V
74ALVCH16374
4/11
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
-40 to 85 C
-55 to 125 C
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
1.65 to 1.95
0.65 Vcc
0.65 Vcc
V
2.3 to 2.7
1.7
1.7
2.7 to 3.6
2.0
2.0
V
IL
Low Level Input
Voltage
1.65 to 1.95
0.35 Vcc
0.35 Vcc
2.3 to 2.7
0.7
0.7
2.7 to 3.6
0.8
0.8
V
OH
High Level Output
Voltage
1.65 to 3.6
I
O
=-100
A
V
CC
-0.2
V
CC
-0.2
V
1.65
I
O
=-4 mA
1.2
1.2
2.3
I
O
=-6 mA
2.0
2.0
2.3
I
O
=-12 mA
1.7
1.7
2.7
I
O
=-12 mA
2.2
2.2
3.0
I
O
=-12 mA
2.4
2.4
3.0
I
O
=-24 mA
2.0
2.0
V
OL
Low Level Output
Voltage
1.65 to 3.6
I
O
=100
A
0.2
0.2
V
1.65
I
O
=4 mA
0.45
0.45
2.3
I
O
=6 mA
0.4
0.4
2.3
I
O
=12 mA
0.7
0.7
2.7
I
O
=12 mA
0.4
0.4
3.0
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= 0 or 3.6V
5
5
A
I
IHOLD
Bus Hold Input
Leakage Current
1.65
V
I
=0.58 V
+ 25
+ 25
A
1.65
V
I
=1.07 V
- 25
- 25
2.3
V
I
=0.7 V
+ 45
+ 45
2.3
V
I
=1.7 V
- 45
- 45
3.0
V
I
=0.8 V
+ 75
+ 75
3.0
V
I
=2 V
- 75
- 75
3.6
V
I
= 0 to 3.6V
500
500
I
off
Power Off Leakage
Current
0
V
I
or V
O
= 3.6V
10
20
A
I
OZ
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
or V
IL
V
O
= 0 to V
CC
5
10
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
I
O
= 0
20
40
A
I
CC
I
CC
incr. per Input
3.0 to 3.6
V
IH
= V
CC
- 0.6V
500
750
A
74ALVCH16374
5/11
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
= t
r
(ns)
-40 to 85 C
-55 to 125 C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Qn
1.65 to 1.95
30
1000
2.0
1
6.5
1
6.5
ns
2.3 to 2.7
30
500
2.0
1
5.3
1
5.3
2.7
50
500
2.5
1
4.9
1
4.9
3.0 to 3.6
50
500
2.5
1
4.2
1
4.2
t
PZL
t
PZH
Output Enable Time
1.65 to 1.95
30
1000
2.0
1
7.5
1
7.5
ns
2.3 to 2.7
30
500
2.0
1
6.2
1
6.2
2.7
50
500
2.5
1
5.9
1
5.9
3.0 to 3.6
50
500
2.5
1
4.8
1
4.8
t
PLZ
t
PHZ
Output Disable Time
1.65 to 1.95
30
1000
2.0
1
6.5
1
6.5
ns
2.3 to 2.7
30
500
2.0
1
5.3
1
5.3
2.7
50
500
2.5
1
4.7
1
4.7
3.0 to 3.6
50
500
2.5
1
4.3
1
4.3
t
s
Setup TIme, HIGH or
LOW level Dn to CK
1.65 to 1.95
30
1000
2.0
1
1
ns
2.3 to 2.7
30
500
2.0
1
1
2.7
50
500
2.5
1
1
3.0 to 3.6
50
500
2.5
1
1
t
h
Hold Time High or
LOW level Dn to CK
1.65 to 1.95
30
1000
2.0
1.5
1.5
ns
2.3 to 2.7
30
500
2.0
1.5
1.5
2.7
50
500
2.5
1.5
1.5
3.0 to 3.6
50
500
2.5
1.5
1.5
t
w
CK Pulse Width,
HIGH
1.65 to 1.95
30
1000
2.0
4
4
ns
2.3 to 2.7
30
500
2.0
3.3
3.3
2.7
50
500
2.5
3.3
3.3
3.0 to 3.6
50
500
2.5
3.3
3.3
f
MAX
Maximum Clock
Pulse Frequency
1.65 to 1.95
30
1000
2.0
120
120
MHz
2.3 to 2.7
30
500
2.0
150
150
2.7
50
500
2.5
200
200
3.0 to 3.6
50
500
2.5
300
300
74ALVCH16374
6/11
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
TEST CIRCUIT
R
T
= Z
OUT
of pulse generator (typically 50
)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25 C
Min.
Typ.
Max.
C
IN
Input Capacitance Control
Inputs
3.3
V
IN
=V
CC
or GND
3
pF
C
IN
Input Capacitance Data Inputs
3.3
V
IN
=V
CC
or GND
6
pF
C
OUT
Output Capacitance
3.3
V
IN
= 0 to V
CC
7
pF
C
PD
Power Dissipation Capacitance
Output enabled (note 1)
3.3
f
IN
= 10MHz
C
L
=50pF
V
IN
= 0 or V
CC
19
pF
2.5
16
C
PD
Power Dissipation Capacitance
Output disabled (note 1)
3.3
5
2.5
4
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
(V
CC
= 3.0 to 3.6V)
6V
t
PZL
, t
PLZ
(V
CC
= 2.3 to 2.7V)
2V
CC
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.0 to 3.6V
2.7V
2.3 to 2.7V
1.65 to 1.95V
V
IH
2.7V
2.7V
V
CC
V
CC
V
M
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+0.3V
V
OL
+0.3V
V
OL
+0.15V
V
OL
+0.15V
V
Y
V
OH
-0.3V
V
OH
-0.3V
V
OH
-0.15V
V
OH
-0.15V
C
L
50pF
50pF
30pF
30pF
R
L
=R
1
500
500
500
1000
t
r
= t
r
<2.5ns
<2.5ns
<2.0ns
<2.0ns
74ALVCH16374
7/11
WAVEFORM 1 : PROPAGATION DELAYS, CK MINIMUM PULSE WIDTH, Dn TO CK SETUP AND
HOLD TIMES, CK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
74ALVCH16374
8/11
WAVEFORM 3 : CK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
74ALVCH16374
9/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.006
A2
0.9
0.035
b
0.17
0.27
0.0067
0.011
c
0.09
0.20
0.0035
0.0079
D
12.4
12.6
0.488
0.496
E
8.1 BSC
0.318 BSC
E1
6.0
6.2
0.236
0.244
e
0.5 BSC
0.0197 BSC
K
0
8
0
8
L
0.50
0.75
0.020
0.030
TSSOP48 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
7065588C
74ALVCH16374
10/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
330
12.992
C
12.8
13.2
0.504
0.519
D
20.2
0.795
N
60
2.362
T
30.4
1.197
Ao
8.7
8.9
0.343
0.350
Bo
13.1
13.3
0.516
0.524
Ko
1.5
1.7
0.059
0.067
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
Tape & Reel TSSOP48 MECHANICAL DATA
74ALVCH16374
11/11
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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