1/11
September 2001
s
5V TOLERANT INPUTS
s
HIGH SPEED :
f
MAX
= 150 MHz (MAX.) at V
CC
= 3V
s
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX74
LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74LCX74M
74LCX74MTR
TSSOP
74LCX74TTR
TSSOP
SOP
74LCX74
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR, 2CLR
Asynchronous Reset - Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input (LOW to HIGH, Edge Triggered)
4, 10
1PR, 2PR
Asynchronous Set - Direct Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
74LCX74
3/11
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (V
CC
= 0V)
-0.5 to +7.0
V
V
O
DC Output Voltage (High or Low State) (note 1)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 50
mA
I
OK
DC Output Diode Current (note 2)
- 50
mA
I
O
DC Output Current
50
mA
I
CC
DC Supply Current per Supply Pin
100
mA
I
GND
DC Ground Current per Supply Pin
100
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2.0 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (V
CC
= 0V)
0 to 5.5
V
V
O
Output Voltage (High or Low State)
0 to V
CC
V
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
24
mA
I
OH
, I
OL
High or Low Level Output Current (V
CC
= 2.7V)
12
mA
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2)
0 to 10
ns/V
74LCX74
4/11
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
-40 to 85
C
-55 to 125
C
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.7 to 3.6
2.0
2.0
V
V
IL
Low Level Input
Voltage
0.8
0.8
V
V
OH
High Level Output
Voltage
2.7 to 3.6
I
O
=-100
A
V
CC
-0.2
V
CC
-0.2
V
2.7
I
O
=-12 mA
2.2
2.2
3.0
I
O
=-18 mA
2.4
2.4
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
2.7 to 3.6
I
O
=100
A
0.2
0.2
V
2.7
I
O
=12 mA
0.4
0.4
3.0
I
O
=16 mA
0.4
0.4
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
2.7 to 3.6
V
I
= 0 to 5.5V
5
5
A
I
off
Power Off Leakage
Current
0
V
I
or V
O
= 5.5V
10
10
A
I
CC
Quiescent Supply
Current
2.7 to 3.6
V
I
= V
CC
or GND
10
10
A
V
I
or V
O
= 3.6 to 5.5V
10
10
I
CC
I
CC
incr. per Input
2.7 to 3.6
V
IH
= V
CC
- 0.6V
500
500
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
Min.
Typ.
Max.
V
OLP
Dynamic Low Level Quiet
Output (note 1)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
0.8
V
V
OLV
-0.8
74LCX74
5/11
AC ELECTRICAL CHARACTERISTICS
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per
Fli p-Flop)
Symbol
Parameter
Test Conditi on
Value
Unit
V
CC
(V)
C
L
(pF)
R
L
(
)
t
s
= t
r
(ns)
-40 to 85
C
-55 to 125
C
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time (CK to Q or Q)
2.7
50
500
2.5
1.5
8.0
1.5
9.2
ns
3.0 to 3.6
1.5
7.0
1.5
8.0
t
PLH
t
PHL
Propagation Delay
Time (PR or CLR to
Q or Q)
2.7
50
500
2.5
1.5
8.0
1.5
9.2
ns
3.0 to 3.6
1.5
7.0
1.5
8.0
t
S
Setup Time, HIGH or
LOW level D to CK
2.7
50
500
2.5
2.5
3.5
ns
3.0 to 3.6
2.5
3.5
t
h
Hold Time, HIGH or
LOW level D to CK
2.7
50
500
2.5
1.5
1.5
ns
3.0 to 3.6
1.5
1.5
t
W
CK Pulse Width,
HIGH or LOW
PR or CLR Pulse
Width, LOW
2.7
50
500
2.5
3.0
4.0
ns
3.0 to 3.6
3.0
4.0
t
rec
Recovery Time PR
or CLR to CK
2.7
50
500
2.5
0
0
ns
3.0 to 3.6
0
0
f
MAX
Clock Pulse
Frequency
2.7
50
500
2.5
150
150
MHz
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50
500
2.5
1.0
1.0
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
Min.
Typ.
Max.
C
IN
Input Capacitance
3.3
V
IN
= 0 to V
CC
6
pF
C
PD
Power Dissipation Capacitance
(note 1)
3.3
f
IN
= 10MHz
V
IN
= 0 or V
CC
40
pF
74LCX74
6/11
TEST CIRCUIT
C
L
= 50 pF or equivalent (includes jig and probe capacitance)
R
L
= 500
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
74LCX74
7/11
WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74LCX74
8/11
WAVEFORM 3 : RECOVERY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 4 : PULSE WIDTH (f=1MHz; 50% duty cycle)
74LCX74
9/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45
(typ.)
D
8.55
8.75
0.336
0.344
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
7.62
0.300
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.68
0.026
S
8
(max.)
SO-14 MECHANICAL DATA
PO13G
74LCX74
10/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.004
0.006
A2
0.8
1
1.05
0.031
0.039
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
8
0
8
L
0.45
0.60
0.75
0.018
0.024
0.030
TSSOP14 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
0080337D
74LCX74
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consequences of use of such inform ation nor for any infringe ment of patents or other righ ts of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information
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