74LVQ138
3 TO 8 LINE DECODER (INVERTING)
February 1999
s
HIGH SPEED: t
PD
= 5.5 ns (TYP.) at V
CC
= 3.3V
s
COMPATIBLE WITH TTL OUTPUT
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
= 25
o
C
s
LOW NOISE:
V
OLP
= 0.2 V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
s
PCI BUS LEVELS GUARANTEED AT 24mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ138 is a low voltage CMOS 3 TO 8 LINE
DECODER
(INVERTING)
fabricated
with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
It is ideal for low power and low noise 3.3V
applications.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It has better speed performance at 3.3V than 5V
LSTTL family combinad with the true CMOS low
power consumption.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ138M
74LVQ138T
1/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCT ION
1, 2, 3
A, B, C
Address Inputs
4, 5
G2A, G2B
Enable Inputs
6
G1
Enable Input
15, 14, 13,
12, 11, 10,
9, 7
Y0 to Y7
Outputs
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUT S
OUTPUTS
ENABL E
SELECT
G2B
G2A
G 1
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
L
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
X:Don't Care
Thislogic diagram has notbe used to esimate propagation delays
74LVQ138
2/9
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
200
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500mW:
65
o
C derated to 300 mW by 10 mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature:
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (V
CC
= 3V) (note 2)
0 to 10
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
74LVQ138
3/9
DC SPECIFICATIONS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
V
IH
High Level Input Voltage
3.0 to
3.6
2.0
2.0
V
V
IL
Low Level Input Voltage
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
V
I
(* )
=
V
IH
or
V
IL
I
O
=-50
A
2.9
2.99
2.9
V
I
O
=-12 mA
2.58
2.48
I
O
=-24 mA
2.2
V
OL
Low Level Output
Voltage
3.0
V
I
(*)
=
V
IH
or
V
IL
I
O
=50
A
0.002
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
I
O
=24 mA
0.55
I
I
Input Leakage Current
3.6
V
I
= V
CC
or GND
0.1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
A
I
OLD
Dynamic Output Current
(note 1, 2)
3.6
V
OLD
= 0.8 V max
36
mA
I
OHD
V
OHD
= 2 V min
-25
mA
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
.
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
V
OLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
3.3
C
L
= 50 pF
0.2
0.8
V
V
OLV
-0.8
-0.2
V
IHD
Dynamic High Voltage
Input (note 1, 3)
3.3
2
V
IL D
Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
). f=1MHz
74LVQ138
4/9
C
L
= 50 pF or equivalent (includes jigand probe capacitance)
R
L
= R
1
= 500
orequivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Co nditi ons
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
C
IN
Input Capacitance
3.3
5
pF
C
PD
Power Dissipation
Capacitance (note 1)
3.3
f
IN
= 10 MHz
50
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3 ns)
Symb ol
Parameter
T est Con ditio n
Valu e
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
T yp.
Max.
Mi n.
Max.
t
PLH
t
PHL
Propagation Delay Time
A, B, C to Y
2.7
7.0
17.0
20.0
ns
3.3
(*)
5.5
12.0
14.0
t
PLH
t
PHL
Propagation Delay Time
G1 to Y
2.7
7.0
17.0
20.0
ns
3.3
(*)
5.5
12.0
14.0
t
PLH
t
PHL
Propagation Delay Time
G2A or G2B to Y
2.7
7.0
17.0
20.0
ns
3.3
(*)
5.5
12.0
14.0
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1, 2)
2.7
0.5
1.5
1.5
ns
3.3
(*)
0.5
1.5
1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
pHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
TEST CIRCUIT
74LVQ138
5/9
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz;
duty cycle 50%)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; duty cycle 50%)
74LVQ138
6/9
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.004
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.62
0.024
S
8 (max.)
P013H
SO-16 MECHANICAL DATA
74LVQ138
7/9
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
o
4
o
8
o
0
o
4
o
8
o
L
0.50
0.60
0.70
0.020
0.024
0.028
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
TSSOP16 MECHANICAL DATA
74LVQ138
8/9
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9/9
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