1/14
July 2004
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 3.3 V
s
COMPATIBLE WITH TTL OUTPUTS
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
s
75
TRANSMISSION LINE DRIVING
CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
s
PCI BUS LEVELS GUARANTEED AT 24 mA
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ161 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
74LVQ161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74LVQ161MTR
TSSOP
74LVQ161TTR
TSSOP
SOP
Rev. 2
74LVQ161
2/14
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
X : Don't Care; A, B, C, D; Logic level of data input; CARRY OUT: TE x QA x QB x QC x QD
Figure 3: Logic Diagram
PIN N
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asynchronous
Master
Reset
2
CLOCK
Clock Input (LOW to
HIGH Edge Trigger)
3, 4, 5, 6
A, B, C, D
Data Inputs
7
PE
Count Enable Input
10
TE
Count Enable Carry Input
9
LOAD
Parallel Enable Input
14, 13, 12,
11
QA to QD
Flip-Flop Outputs
15
CARRY OUT Terminal Count Output
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLEAR
LOAD
PE
TE
CK
L
X
X
X
X
L
L
L
L
RESET TO "0"
H
L
X
X
A
B
C
D
PRESET DATA
H
H
X
L
NO CHANGE
NO COUNT
H
H
L
X
NO CHANGE
NO COUNT
H
H
H
H
COUNT UP
COUNT
H
X
X
X
NO CHANGE
NO COUNT
74LVQ161
3/14
Figure 4: Timing Chart
Table 4: Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
50
mA
I
CC
or I
GND
DC V
CC
or Ground Current
300
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
74LVQ161
4/14
Table 5: Recommended Operating Conditions
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Table 6: DC Specifications
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time V
CC
= 3.0V (note 2)
0 to 10
ns/V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input Volt.
3.0 to
3.6
2.0
2.0
2.0
V
V
IL
Low Level Input Volt.
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
3.0
I
O
=-50
A
2.9
2.99
2.9
2.9
V
I
O
=-12 mA
2.58
2.48
2.48
I
O
=-24 mA
2.2
2.2
V
OL
Low Level Output
Voltage
3.0
I
O
=50
A
0.002
0.1
0.1
0.1
V
I
O
=12 mA
0
0.36
0.44
0.44
I
O
=24 mA
0.55
0.55
I
I
Input Leakage
Current
3.6
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
I
OLD
Dynamic Output Cur-
rent (note 1, 2)
3.6
V
OLD
= 0.8 V max
36
25
mA
I
OHD
V
OHD
= 2 V min
-25
-25
mA
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.8
V
V
OLV
-0.8
-0.3
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3
2
V
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
V
74LVQ161
5/14
Table 8: AC Electrical Characteristics (C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
2.7
8.0
13.0
15.0
17.0
ns
3.3
(*)
6.8
9.5
11.0
12.5
t
PLH
t
PHL
Propagation Delay
Time CK to CARRY
OUT
2.7
9.1
14.0
16.0
18.5
ns
3.3
(*)
7.5
10.5
12.0
14.0
t
PLH
t
PHL
Propagation Delay
Time TE to CARRY
OUT
2.7
5.6
10.0
11.5
13.0
ns
3.3
(*)
4.7
8.0
9.5
10.5
t
PHL
Propagation Delay
Time CLR to Q
2.7
8.0
12.0
15.0
17.0
ns
3.3
(*)
6.1
9.5
11.0
12.5
t
PHL
Propagation Delay
Time CLR to
CARRY OUT
2.7
8.0
14.0
16.0
18.5
ns
3.3
(*)
6.7
10.5
12.0
14.0
t
W(L)
CLR Pulse Width,
LOW (LOAD)
2.7
4.0
1.9
4.0
4.0
ns
3.3
(*)
3.0
1.9
3.0
3.0
t
W
CLOCK Pulse
Width, HIGH or
LOW
2.7
4.0
1.9
4.0
4.0
ns
3.3
(*)
3.0
1.9
3.0
3.0
t
s
Setup Time HIGH
or LOW
(INPUT to CLOCK)
2.7
5.0
2.5
5.0
5.0
ns
3.3
(*)
4.0
2.1
4.0
4.0
t
h
Hold Time HIGH or
LOW
(INPUT to CLOCK)
2.7
1
-1.3
1
1
ns
3.3
(*)
0.5
-1.0
0.5
0.5
t
s
Setup Time HIGH
or LOW (LOAD to
CLOCK)
2.7
3.0
1.5
3.0
3.0
ns
3.3
(*)
2.5
1.2
2.5
2.5
t
h
Hold Time HIGH or
LOW (LOAD to
CLOCK)
2.7
1
-0.6
1
1
ns
3.3
(*)
0.5
-0.5
0.5
0.5
t
s
Setup Time HIGH
or LOW (PE or TE
to CLOCK)
2.7
7.0
3.4
7.0
7.0
ns
3.3
(*)
6.0
3.0
6.0
6.0
t
h
Hold Time HIGH or
LOW (PE or TE
to CLOCK)
2.7
0
-2.6
0
0
ns
3.3
(*)
0
-2.2
0
0
t
REM
Recovery Time
CLR to CK
2.7
1
-0.8
1
1
ns
3.3
(*)
0.5
-0.6
0.5
0.5
f
MAX
Maximum Clock
Frequency
2.7
100
150
80
60
MHz
3.3
(*)
120
180
100
80
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
2.7
0.5
1.0
1.0
1.0
ns
3.3
(*)
0.5
1.0
1.0
1.0
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