1/10
February 2003
s
HIGH SPEED:
f
MAX
= 160 MHz (TYP.) at V
CC
= 3V
s
5V TOLERANT INPUTS
s
POWER DOWN PROTECTION ON INPUTS
s
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
These 16 bit D-TYPE flip-flop is controlled by two
clock inputs (CK) and two output enable inputs
(nOE). The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop.On the positive
transition of the clock, the Q outputs will be set to
the logic state that were setup at the D inputs.
While the (OE) input is low, the outputs will be in
a normal logic state (high or low logic level); while
OE is high, the outputs will be in a high impedance
state.The output control does not affect the inter-
nal operation of flip-flops; that is, the old data can
be retained or the new data can be entered even
while the outputs are off.Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.This
device can be used to interface 5V to 3V. All in-
puts and outputs are equipped with protection cir-
cuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage.
74LVX16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP FLOP (3-STATE)
WITH 5V TOLERANT INPUTS
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74LVX16374TTR
TSSOP
PIN CONNECTION
74LVX16374
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2CK
Clock Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1CK
Clock Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74LVX16374
3/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage (note 1)
2 to 3.6
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 2) (V
CC
= 3V)
0 to 100
ns/V
74LVX16374
4/10
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0
2.0
2.0
2.0
3.6
2.4
2.4
2.4
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0
0.8
0.8
0.8
3.6
0.8
0.8
0.8
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
3.0
I
O
=-4 mA
2.58
2.48
2.4
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
I
OZ
High Impedance
Output Leakage
Current
3.6
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
2.5
A
I
I
Input Leakage
Current
3.6
V
I
= 5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
3.6
V
I
= V
CC
or GND
4
40
40
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
C
L
= 50 pF
0.3
0.8
V
V
OLV
-0.8
-0.3
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
3.3
2.0
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
74LVX16374
5/10
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
0.3V
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
2.7
15
9.5
16.3
1.0
19.5
1.0
20.5
ns
2.7
50
11.0
19.8
1.0
23.0
1.0
24.0
3.3
(*)
15
9
15
1
17
1
17
3.3
(*)
50
10.6
16.2
1
18.5
1
18.5
t
PZL
t
PZH
Output Enable
Time
2.7
15
8.6
14.5
1.0
17.5
1.0
18.5
ns
2.7
50
10.1
18.0
1.0
21.0
1.0
22.0
3.3
(*)
15
8
13
1
15
1
15
3.3
(*)
50
9.6
14.9
1
16
1
16
t
PLZ
t
PHZ
Output Disable
Time
2.7
50
11.5
18.5
1.0
22.0
1.0
23.0
ns
3.3
(*)
50
9.6
13.2
1.0
15.0
1.0
16.0
t
W
CK pulse Width,
HIGH
2.7
50
5
5
5
5
ns
3.3
(*)
50
5
5
5
5
t
S
Setup Time D to CK
HIGH or LOW
2.7
50
4.5
4
4
ns
3.3
(*)
50
3
3
3
t
h
Hold Time D to CK
HIGH or LOW
2.7
50
2
2
2
ns
3.3
(*)
50
2
2
2
f
MAX
Maximum Clock
Frequency
2.7
15
60
115
50
45
MHz
2.7
50
45
60
40
35
3.3
(*)
15
100
160
85
75
3.3
(*)
50
80
130
70
70
80
t
OSLH
t
OSHL
Output to Output
Skew Time (note
1,2)
2.7
50
0.5
1.0
1.5
1.5
ns
3.3
(*)
50
0.5
1.0
1.5
1.5
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
2.5
10
10
10
pF
C
OUT
Output
Capacitance
4
pF
C
PD
Power Dissipation
Capacitance
(note 1)
3.0
f
IN
= 10MHz
17
pF
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