1/10
July 2001
s
HIGH SPEED:
t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25
C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHC16373 is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74VHC16373
16-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS NON INVERTING
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74VHC16373TTR
TSSOP
PIN CONNECTION
74VHC16373
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don`t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1LE
Latch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
74VHC16373
3/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 30% to 70% of V
CC
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
75
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1) (V
CC
= 3.3
0.3V)
(V
CC
= 5.0
0.5V)
0 to 100
0 to 20
ns/V
74VHC16373
4/10
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0 to
5.5
0.7V
CC
0.7V
CC
0.7V
CC
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0 to
5.5
0.3V
CC
0.3V
CC
0.3V
CC
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
3.0
I
O
=-4 mA
2.58
2.48
2.4
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
4.5
I
O
=8 mA
0.36
0.44
0.55
I
OZ
High Impedance
Output Leakage
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
5
A
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
74VHC16373
5/10
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
0.3V
(**) Voltage range is 5.0V
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per Latch)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Qn
3.3
(*)
15
5.5
13
1
15
1
15
ns
3.3
(*)
50
7
14.5
1
16.5
1
16.5
5.0
(**)
15
3.6
8.5
1
9.5
1
9.5
5.0
(**)
50
5
9.5
1
10.5
1
10.5
t
PLH
t
PHL
Propagation Delay
Time
Dn to Qn
3.3
(*)
15
5.5
13
1
15
1
15
ns
3.3
(*)
50
7.5
14
1
16
1
16
5.0
(**)
15
4
8.2
1
9.5
1
9.5
5.0
(**)
50
5
9.2
1
10.5
1
10.5
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
15
5.2
13
1
15
1
15
ns
3.3
(*)
50
7.6
14.9
1
16
1
16
5.0
(**)
15
4
9.1
1
10
1
10
ns
5.0
(**)
50
5
10.1
1
11.5
1
11.5
t
PLZ
t
PHZ
Output Disable
Time
3.3
(*)
50
9
15.5
1
17
1
17
ns
5.0
(**)
50
6
10.5
1
11.5
1
11.5
t
w
Pulse Width (LE)
HIGH
3.3
(*)
5
5
5
ns
5.0
(**)
5
5
5
t
s
Setup Time Dn to
LE HIGH or LOW
3.3
(*)
4
4
4
ns
5.0
(**)
4
4
4
t
h
Hold Time Dn to LE
HIGH or LOW
3.3
(*)
1
1
1
ns
5.0
(**)
1
1
1
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
3.3
(*)
50
1.5
1.5
1.5
ns
5.0
(**)
50
1
1
1
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25
C
-40 to 85
C
-55 to 125
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
2.5
10
10
10
pF
C
OUT
Output
Capacitance
4
pF
C
PD
Power Dissipation
Capacitance
(note 1)
5.0
f
IN
= 10MHz
21
pF
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