1/9
June 2001
s
HIGH SPEED: t
PD
= 5.5 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 238
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC238 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go high. If enable input G1 is held low or either
G2A or G2B is held high, decoding function is
inhibited and all the 8 outputs go to low.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC238
3 TO 8 LINE DECODER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74VHC238M
74VHC238MTR
TSSOP
74VHC238TTR
TSSOP
SOP
74VHC238
2/9
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3
A, B, C
Address Inputs
4, 5
G2A, G2B
Enable Inputs
6
G1
Enable Input
15, 14, 13,
12, 11, 10, 9,
7
Y0 to Y7
Outputs
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
ENABLE
SELECT
G2B
G2A
G1
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
L
X
X
X
L
L
L
L
L
L
L
L
X
H
X
X
X
X
L
L
L
L
L
L
L
L
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
L
L
H
L
H
H
L
L
L
H
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
74VHC238
3/9
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 30% to 70% of V
CC
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
75
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1) (V
CC
= 3.3
0.3V)
(V
CC
= 5.0
0.5V)
0 to 100
0 to 20
ns/V
74VHC238
4/9
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
0.3V
(**) Voltage range is 5.0V
0.5V
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0 to
5.5
0.7V
CC
0.7V
CC
0.7V
CC
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0 to
5.5
0.3V
CC
0.3V
CC
0.3V
CC
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
3.0
I
O
=-4 mA
2.58
2.48
2.4
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
4.5
I
O
=8 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
A, B, C, to Y
3.3
(*)
15
8.0
12.3
1.0
14.5
1.0
14.5
ns
3.3
(*)
50
10.5
15.8
1.0
18.0
1.0
18.0
5.0
(**)
15
5.5
8.1
1.0
9.5
1.0
9.5
5.0
(**)
50
7.0
10.1
1.0
11.5
1.0
11.5
t
PLH
t
PHL
Propagation Delay
Time
G1 to Y
3.3
(*)
15
8.1
12.8
1.0
15.0
1.0
15.0
ns
3.3
(*)
50
10.6
16.3
1.0
18.5
1.0
18.5
5.0
(**)
15
5.4
8.1
1.0
9.5
1.0
9.5
5.0
(**)
50
6.9
10.1
1.0
11.5
1.0
11.5
t
PLH
t
PHL
Propagation Delay
Time
G2A, G2B to Y
3.3
(*)
15
8.1
12.3
1.0
14.5
1.0
14.5
ns
3.3
(*)
50
10.6
15.8
1.0
18.0
1.0
18.0
5.0
(**)
15
5.7
8.1
1.0
9.5
1.0
9.5
5.0
(**)
50
7.2
10.1
1.0
11.5
1.0
11.5
74VHC238
5/9
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
TEST CIRCUIT
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
Symbol
Parameter
Test Condition
Value
Unit
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
4
10
10
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
18
pF
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