1/11
June 2001
s
HIGH SPEED:
s
f
MAX
= 180 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHC574 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3
STATE OUTPUTS NON INVERTING fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology.
These 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic states that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74VHC574M
74VHC574MTR
TSSOP
74VHC574TTR
TSSOP
SOP
74VHC574
2/11
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3-State Output Enable
Input (Active LOW)
2, 3, 4, 5, 6,
7, 8, 9
D0 to D7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7
3-State Outputs
11
CK
Clock Input (LOW-to-HIGH
Edge Triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74VHC574
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 30% to 70% of V
CC
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
75
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1) (V
CC
= 3.3
0.3V)
(V
CC
= 5.0
0.5V)
0 to 100
0 to 20
ns/V
74VHC574
4/11
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
3.0 to
5.5
0.7V
CC
0.7V
CC
0.7V
CC
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
3.0 to
5.5
0.3V
CC
0.3V
CC
0.3V
CC
V
OH
High Level Output
Voltage
2.0
I
O
=-50
A
1.9
2.0
1.9
1.9
V
3.0
I
O
=-50
A
2.9
3.0
2.9
2.9
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
3.0
I
O
=-4 mA
2.58
2.48
2.4
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
2.0
I
O
=50
A
0.0
0.1
0.1
0.1
V
3.0
I
O
=50
A
0.0
0.1
0.1
0.1
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
3.0
I
O
=4 mA
0.36
0.44
0.55
4.5
I
O
=8 mA
0.36
0.44
0.55
Ioz
High Impedance
Output Leakage
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
2.5
A
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
74VHC574
5/11
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 3.3V
0.3V
(**) Voltage range is 5.0V
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per
Flip-Flop)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
CH to Q
3.3
(*)
15
8.5
13.2
1.0
15.5
1.0
15.5
ns
3.3
(*)
50
11.0
16.7
1.0
19.0
1.0
19.0
5.0
(**)
15
5.6
8.6
1.0
10.0
1.0
10.0
5.0
(**)
50
7.1
10.6
1.0
12.0
1.0
12.0
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
15
8.2
12.8
1.0
15.0
1.0
15.0
ns
3.3
(*)
50
10.7
16.3
1.0
18.5
1.0
18.5
5.0
(**)
15
5.9
9.0
1.0
10.5
1.0
10.5
5.0
(**)
50
7.4
11.0
1.0
12.5
1.0
12.5
t
PLZ
t
PHZ
Output Disable
Time
3.3
(*)
50
11.0
15.0
1.0
17.0
1.0
17.0
ns
3.3
(*)
50
7.1
10.1
1.0
11.5
1.0
11.5
t
w
Clock Pulse Width
HIGH or LOW
3.3
(*)
5.0
5.0
5.0
ns
5.0
(**)
5.0
5.0
5.0
t
s
Setup Time D to CK
HIGH or LOW
3.3
(*)
3.5
3.5
3.5
ns
5.0
(**)
3.5
3.5
3.5
t
h
Hold Time D to CK
HIGH or LOW
3.3
(*)
1.5
1.5
1.5
ns
5.0
(**)
1.5
1.5
1.5
f
MAX
Maximum Clock
Frequency
3.3
(*)
15
80
125
65
65
MHz
3.3
(*)
50
50
75
45
45
5.0
(**)
15
130
180
110
110
5.0
(**)
50
85
115
75
75
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
3.3
(*)
50
1.5
1.5
1.5
ns
5.0
(**)
50
1.0
1.0
1.0
Symbol
Parameter
Test Condition
Value
Unit
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
7
10
10
10
pF
C
OUT
Output
Capacitance
9
pF
C
PD
Power Dissipation
Capacitance
(note 1)
28
pF
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