1/10
February 2003
s
HIGH SPEED:
f
MAX
= 185 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
=2V (MIN.) V
IL
= 0.8 (MAX.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHCT16374A is an advanced high-speed
CMOS 16 D-TYPE FLIP FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 16 bit D-TYPE flip-flop is controlled by two
clock inputs (CK) and two output enable inputs
(nOE). The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop.
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the outputs will be in
a normal logic state (high or low logic level); while
OE is high, the outputs will be in a high impedance
state.
The output control does not affect the internal op-
eration of flip-flops; that is, the old data can be re-
tained or the new data can be entered even while
the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74VHCT16374A
16-BIT D-TYPE FLIP FLOP
WITH 3-STATE OUTPUTS NON INVERTING
ORDER CODES
PACKAGE
TUBE
T & R
TSSOP
74VHCT16374ATTR
TSSOP
PIN CONNECTION
74VHCT16374A
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to
1Q7
3-State Outputs
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to
2Q7
3-State Outputs
24
2OE
3 State Output Enable
Input (Active LOW)
25
2CK
Clock Input (LOW-to-HIGH
Edge Trigger)
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7 Data Inputs
47, 46, 44, 43,
41, 40, 38, 37
1D0 to 1D7 Data Inputs
48
1CK
Clock Input (LOW-to-HIGH
Edge Trigger)
4, 10, 15, 21,
28, 34, 39, 45
GND
Ground (0V)
7, 18, 31, 42
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
74VHCT16374A
3/10
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
1) V
IN
from 0.8V to 2.0V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
75
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (note 1) (Vcc= 5.0
0.
5V)
0 to 20
ns/V
74VHCT16374A
4/10
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
(Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5 to
5.5
2
2
2
V
V
IL
Low Level Input
Voltage
4.5 to
5.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
0.55
I
OZ
High Impedance
Output Leakage
Current
5.5
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.25
2.5
2.5
A
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q
5.0
(*)
15
5.6
9.4
1.0
10.5
1.0
10.5
ns
5.0
(*)
50
6.4
10.4
1.0
11.5
1.0
11.5
t
PZL
t
PZH
Output Enable
Time
5.0
(*)
15
RL = 1K
6.2
10.2
1.0
11.5
1.0
11.5
ns
5.0
(*)
50
7.3
11.2
1.0
12.5
1.0
12.5
t
PLZ
t
PHZ
Output Disable
Time
5.0
(*)
50
RL = 1K
7.0
11.2
1.0
12.0
1.0
12.0
ns
t
w
Clock Pulse Width
HIGH or LOW
5.0
(*)
6.5
6.5
6.5
ns
t
s
Setup Time D to CK
HIGH or LOW
5.0
(*)
2.5
2.5
2.5
ns
t
h
Hold Time D to CK
HIGH or LOW
5.0
(*)
2.5
2.5
2.5
ns
f
MAX
Maximum Clock
Frequency
5.0
(*)
15
90
140
110
80
MHz
5.0
(*)
50
85
130
75
75
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
5.0
(*)
50
1.0
1.0
1.0
ns
74VHCT16374A
5/10
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
Latch)
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
4
10
10
10
pF
C
OUT
Output
Capacitance
6
pF
C
PD
Power Dissipation
Capacitance
(note 1)
5.0
f
IN
= 10MHz
21
pF
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
C
L
= 50 pF
0.6
0.9
V
V
OLV
-0.9
-0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
5.0
3.5
V
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0
1.5
V
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