1/10
June 2001
s
HIGH SPEED:
f
MAX
= 170 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHCT273A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHCT273A
OCTAL D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74VHCT273AM
74VHCT273AMTR
TSSOP
74VHCT273ATTR
TSSOP
SOP
74VHCT273A
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asyncronous Master Reset
(Active LOW)
2, 5, 6, 9, 12,
15, 16,19
Q0 to Q7
Flip-Flop Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
CLOCK
Clock Input (LOW-to-HIGH
Edge Triggered)
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
FUNCTION
CLEAR
D
CLOCK
Q
L
X
X
L
CLEAR
H
L
L
H
H
H
H
X
Q
n
NO CHANGE
74VHCT273A
3/10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) V
CC
= 0V
2) High or Low State
RECOMMENDED OPERATING CONDITIONS
1) V
CC
= 0V
2) High or Low State
3) VIN from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 1)
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 2)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (see note 1)
0 to 5.5
V
V
O
Output Voltage (see note 2)
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
74VHCT273A
4/10
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5 to
5.5
2
2
2
V
V
IL
Low Level Input
Voltage
4.5 to
5.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
0.55
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1.0
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
I
CC
Additional Worst
Case Supply
Current
5.5
One Input at 3.4V,
other input at V
CC
or GND
1.35
1.5
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
5.0
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time CLOCK to Q
5.0
(**)
15
5.8
8.2
1.0
10.0
1.0
10.0
ns
5.0
(**)
50
6.8
9.2
1.0
11.0
1.0
11.0
t
PHL
Propagation Delay
Time CLEAR to Q
5.0
(**)
15
7.5
10.0
1.0
11.6
1.0
11.6
ns
5.0
(**)
50
8.5
11.0
1.0
12.6
1.0
12.6
t
W
CLR Pulse Width
LOW
5.0
(**)
5.0
5.0
5.0
ns
t
W
CK Pulse Width
HIGH or LOW
5.0
(**)
5.0
5.0
5.0
ns
t
s
Setup Time D to
CLOCK, HIGH or
LOW
5.0
(**)
2.0
2.0
2.0
ns
t
h
Hold Time D to CK,
HIGH or LOW
5.0
(**)
2.0
2.0
2.0
ns
t
REM
Removal Time CLR
to CLOCK
5.0
(**)
1.0
1.0
1.0
ns
f
MAX
Maximum Clock
Frequency
5.0
(**)
15
75
170
65
65
MHz
5.0
(**)
50
50
160
45
45
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
5.0
(**)
50
1.0
1.0
1.0
ns
74VHCT273A
5/10
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per
Flip-Flop)
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
TEST CIRCUIT
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
Symbol
Parameter
Test Condition
Value
Unit
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
6
10
10
10
pF
C
PD
Power Dissipation
Capacitance
(note 1)
16
pF
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
C
L
= 50 pF
0.6
0.9
V
V
OLV
-0.9
-0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
5.0
2.0
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0
0.8
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