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Электронный компонент: 74VHCT373ATTR

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1/10
June 2001
s
HIGH SPEED: t
PD
= 6.4 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely . When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHCT373A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
SOP
74VHCT373AM
74VHCT373AMTR
TSSOP
74VHCT373ATTR
TSSOP
SOP
74VHCT373A
2/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
* : Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0 to Q7
3-State Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
LE
Latch Enable Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUT
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE*
L
H
L
L
L
H
H
H
74VHCT373A
3/10
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) Output in OFF State
2) High or Low State
RECOMMENDED OPERATING CONDITIONS
1) Output in OFF State
2) High or Low State
3) V
IN
from 0.8V to 2V
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 1)
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 2)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (see note 1)
0 to 5.5
V
V
O
Output Voltage (see note 2)
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
74VHCT373A
4/10
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V
0.5V
Note 1 : Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5 to
5.5
2
2
2
V
V
IL
Low Level Input
Voltage
4.5 to
5.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
3.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
0.55
Ioz
High Impedance
Output Leakege
Current
4.5 to
5.5
V
I
= V
IH
or V
IL
V
O
= 0V to 5.5
0.25
2.5
2.5
A
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
0.1
1.0
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
40
A
I
CC
Additional Worst
Case Supply
Current
5.5
One Input at 3.4V,
other input at V
CC
or GND
1.35
1.5
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
5.0
A
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
5.0
(*)
15
5.4
12.3
1.0
13.5
1.0
13.5
ns
5.0
(*)
50
6.0
13.3
1.0
14.5
1.0
14.5
t
PLH
t
PHL
Propagation Delay
Time
D to Q
5.0
(*)
15
6.4
8.5
1.0
9.5
1.0
9.5
ns
5.0
(*)
50
7.1
9.5
1.0
10.5
1.0
10.5
t
PZL
t
PZH
Output Enable
Time
5.0
(*)
15
RL = 1K
6.2
10.9
1.0
12.5
1.0
12.5
ns
5.0
(*)
50
6.9
11.9
1.0
13.5
1.0
13.5
t
PLZ
t
PHZ
Output Disable
Time
5.0
(*)
50
RL = 1K
6.7
11.2
1.0
12.0
1.0
12.0
ns
t
w
Pulse Width (LE)
HIGH
5.0
(*)
6.5
8.5
8.5
ns
t
s
Setup Time D to LE
HIGH or LOW
5.0
(*)
1.5
1.5
1.5
ns
t
h
Hold Time D to LE
HIGH or LOW
5.0
(*)
3.5
3.5
3.5
ns
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
5.0
(*)
50
1.0
1.0
1.0
ns
74VHCT373A
5/10
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol
Parameter
Test Condition
Value
Unit
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
4
10
10
10
pF
C
OUT
Output
Capacitance
9
pF
C
PD
Power Dissipation
Capacitance
(note 1)
14
pF
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
C
L
= 50 pF
0.6
0.9
V
V
OLV
-0.9
-0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
5.0
2.0
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0
0.8
74VHCT373A
6/10
TEST CIRCUIT
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
L
= R1 = 1K
or equivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES
(f=1MHz; 50% duty cycle)
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
CC
t
PZH
, t
PHZ
GND
74VHCT373A
7/10
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
74VHCT373A
8/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.2
0.004
0.008
a2
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45 (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
M
0.75
0.029
S
8 (max.)
SO-20 MECHANICAL DATA
PO13L
74VHCT373A
9/10
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.2
0.047
A1
0.05
0.15
0.002
0.004
0.006
A2
0.8
1
1.05
0.031
0.039
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0
8
0
8
L
0.45
0.60
0.75
0.018
0.024
0.030
TSSOP20 MECHANICAL DATA
c
E
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1
L
K
e
0087225C
74VHCT373A
10/10
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