74VHCT573A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
February 2000
s
HIGH SPEED: t
PD
= 5.4 ns (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A (MAX.) at T
A
= 25
o
C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: V
OLP
= 0.9V (Max.)
DESCRIPTION
The 74VHCT573A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT
NON
INVERTING
fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
SOP
74VHCT573AM
74VHCT573AMTR
TSSOP
74VHCT573ATTR
1/10
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PI N No
SYMBOL
NAME AND FUNCT ION
1
OE
3 State Output Enable
Input (Active LOW)
2, 3, 4,
5, 6, 7,
8, 9
D0 to D7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
Q0 to Q7
3 State Latch Outputs
11
LE
Latch Enable
Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUT PUTS
OE
L E
D
Q
H
X
X
Z
L
L
X
NO CHANGE *
L
H
L
L
L
H
H
H
X:Don't care
Z: High impedance
* Q outputs are latched atthe time when the LEinput is taken low logic level.
LOGIC DIAGRAM
74VHCT573A
2/10
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (see note 1)
0 to 5.5
V
V
O
Output Voltage (see note 2)
0 to V
CC
V
T
op
Operating Temperature
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
1) Output in OFF State
2) High or Low State
3)V
IN
from0.8V to 2 V
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 1)
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 2)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
1) Output in OFF State
2) High or Low State
74VHCT573A
3/10
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
V
IH
High Level Input
Voltage
4.5 to 5.5
2
2
V
V
IL
Low Level Input
Voltage
4.5 to 5.5
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
I
OZ
High Impedance
Output Leakage
Current
4.5 to 5.5
V
I
= V
IH
or V
IL
V
O
= 0V to 5.5V
0.25
2.5
A
I
I
Input Leakage Current
0 to 5.5
V
I
= 5.5V or GND
0.1
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
4
40
A
I
CC
Additional Worst Case
Supply Current
5.5
One Input at 3.4V,
other input at V
CC
or
GND
1.35
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
A
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
V
CC
(V)
C
L
(pF )
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
t
PLH
t
PHL
Propagation Delay
Time LE to Q
5.0
(*)
15
5.3
7.5
1.0
9.0
ns
5.0
(*)
50
5.9
8.5
1.0
10.0
t
PLH
t
PHL
Propagation Delay
Time D to Q
5.0
(*)
15
5.4
7.0
1.0
9.0
ns
5.0
(*)
50
6.4
8.0
1.0
10.0
t
PZL
t
PZH
Output EnableTime
5.0
(*)
15
R
L
= 1K
5.4
7.5
1.0
10.0
ns
5.0
(*)
50
6.0
8.5
1.0
11.0
t
PLZ
t
PHZ
Output Disable Time
5.0
(*)
50
R
L
= 1K
6.3
9.0
1.0
12.0
ns
t
w
Pulse Width (LE)
HIGH
5.0
(*)
5.0
5.0
ns
t
s
Setup Time D to LE
HIGH or LOW
5.0
(*)
2.0
2.0
ns
t
h
Hold Time D toLE
HIGH or LOW
5.0
(*)
1.5
1.5
ns
t
OSLH
t
OSHL
Output to Output Skew
Time (note 1)
5.0
(*)
50
1.0
1.0
ns
(*) Voltage range is 5V
0.5V
Note 1: Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
74VHCT573A
4/10
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
C
IN
Input Capacitance
4
10
10
pF
C
OUT
Output Capacitance
8
pF
C
PD
Power Dissipation
Capacitance (note 1)
26
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
V
OLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
5.0
C
L
= 50 pF
0.6
0.9
V
V
OLV
-0.9
-0.6
V
IHD
Dynamic High Voltage
Input (note 1, 3)
5.0
2.0
V
IL D
Dynamic Low Voltage
Input (note 1, 3)
5.0
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (V
ILD
), 0V to threshold (V
IHD
), f=1MHz.
TEST CIRCUIT
T EST
SW IT CH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
CC
t
PZH
, t
PHZ
GND
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 1K
orequivalent
R
T
= Z
OUT
of pulse generator (typically 50
)
74VHCT573A
5/10
PDF 
ZIP