74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
March 2000
s
HIGH SPEED:
f
MAX
=160 MHz (TYP.) at V
CC
= 5V
s
LOW POWER DISSIPATION:
I
CC
= 2
A (MAX.) at T
A
= 25
o
C
s
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS
DUAL
D-TYPE
FLIP
FLOP
WITH
PRESET AND CLEAR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
SOP
74VHCT74AM
74VHCT74AMTR
TSSOP
74VHCT74ATTR
1/10
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCT ION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
1D, 2D
Data Input
3, 11
1CK, 2CK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
TRUTH TABLE
I NPUTS
OUT PUT S
F UNCTI ON
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
X:Don't Care
Thislogic diagram has notbe used to estimate propagation delays
74VHCT74A
2/10
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Valu e
Uni t
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to 5.5
V
V
O
Output Voltage (see note 1)
0 to 5.5
V
V
O
Output Voltage (see note 2)
0 to V
CC
V
T
op
Operating Temperature
-40 to +85
o
C
dt/dv
Input Rise and Fall Time (see note 3) (V
CC
= 5.0
0.5V)
0 to 20
ns/V
1) V
CC
=0
2) High or Low State
3)V
IN
from0.8V to 2 V
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Unit
V
CC
Supply Voltage
-0.5 to +7.0
V
V
I
DC Input Voltage
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 1)
-0.5 to +7.0
V
V
O
DC Output Voltage (see note 2)
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
- 20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
1) V
CC
=0
2) High or Low State
DC SPECIFICATIONS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
V
CC
(V)
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
V
IH
High Level Input
Voltage
4.5 to 5.5
2
2
V
V
IL
Low Level Input
Voltage
4.5 to 5.5
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-50
A
4.4
4.5
4.4
V
4.5
I
O
=-8 mA
3.94
3.8
V
OL
Low Level Output
Voltage
4.5
I
O
=50
A
0.0
0.1
0.1
V
4.5
I
O
=8 mA
0.36
0.44
I
I
Input Leakage Current
0 to 5.5
V
I
= 5.5V or GND
0.1
1.0
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
2
20
A
I
CC
Additional Worst Case
Supply Current
5.5
One Input at 3.4V,
other input at V
CC
or
GND
1.35
1.5
mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5
5.0
A
74VHCT74A
3/10
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
=3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
V
CC
(V)
C
L
(pF )
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
t
PLH
t
PHL
Propagation Delay
Time CK to Q or Q
5.0
(*)
15
5.8
7.8
1.0
9.0
ns
5.0
(*)
50
6.3
8.8
1.0
10.0
t
PLH
t
PHL
Propagation Delay
Time
PR or CLR to Q or Q
5.0
(*)
15
7.6
10.4
1.0
12.0
ns
5.0
(*)
50
8.1
11.4
1.0
13.0
t
w
CK Pulse Width
HIGH or LOW
5.0
(*)
5.0
5.0
ns
t
w
PR or CLR Pulse
Width LOW
5.0
(*)
5.0
5.0
ns
t
s
Setup Time D to CK
HIGH or LOW
5.0
(*)
5.0
5.0
ns
t
h
Hold Time D to CK
HIGH or LOW
5.0
(*)
0.0
0.0
ns
t
REM
Removal Time CLR or
PR to CK
5.0
(*)
3.5
3.5
ns
f
MAX
Maximum Clock
Frequency
5.0
(*)
15
100
160
80
MHz
5.0
(*)
50
80
140
65
(*) Voltage range is 5V
0.5V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
T
A
= 25
o
C
-40 to 85
o
C
Min.
Typ .
Max.
Min .
Max.
C
IN
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation
Capacitance (note 1)
10.5
pF
1) C
PD
isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2 (per Gate)
74VHCT74A
4/10
TEST CIRCUIT
C
L
= 15/50 pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
74VHCT74A
5/10
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