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EMIF03-SIM01
July 2002 - Ed: 6A
IEC61000-4-2 15kV
(air discharge)
8 kV
(contact discharge)
on input & output pins.
COMPLIES WITH THE FOLLOWING STANDARDS :
Flip Chip package
A2
A3
B3
B2
B1
C1
C2
C3
PIN CONFIGURATION (Ball side)
s
3 lines symetrical (I/O) low-pass-filter
s
High efficiency in EMI filtering
s
Very low PCB space consuming: 1.6 x 1.6 mm
2
s
Very thin package: 0.65 mm
s
High efficiency in ESD suppression on both input
& output PINS (IEC61000-4-2 level 4)
s
High reliability offered by monolithic integration
s
High reducing of parasitic elements through inte-
gration & wafer level packaging.
BENEFITS
3 LINES EMI FILTER
INCLUDING ESD PROTECTION
A.S.D.
TM
EMI filtering protection and ESD for :
s
SIM Interface (Subscriber identify Module)
MAIN APPLICATIONS
The EMIF03-SIM01 is a highly integrated array
designed to suppress EMI / RFI noise in all
systems
subjected
to
electromagnetic
interferences.
The EMIF03-SIM01 flip-chip packaging means the
package size is equal to the die size. That's why
EMIF03-SIM01 is a very small device.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
DESCRIPTION
TM : ASD is a trademark of STMicroelectronics.
EMIF03-SIM01
2/11
47R
B3
C3
B1
C1
100R
A3
A2
100R
C2
B2 is ground pin
GND
Schematic
sub
50p
0.05
0.08nH
0.1
DEMIF03 diodes Model
- RS = 1.2
- CJO = 17p
- M = 0.3333
- VJ = 0.6
- ISR = 100p
- BV = 6.8
- IBV = 1m
- TT = 100n
Rseries = 47R (CLK line)
= 100R (RST & Data lines)
DEMIF03_Vcc diode Model
- RS = 1.5
- CJO = 20p
- M = 0.3333
- VJ = 0.6
- ISR = 100p
- BV = 6.8
- IBV = 1m
- TT = 100n
Rseries
sub
Port1
50
Port2
50
MODEL = demif03
MODEL = demif03
MODEL = demif03_Vcc
sub
Vcc
Aplac model
Aplac 7.60 User: STMicroelectronics Feb 22 2001
100.0k
1.0M
10.0M
100.0M
1.0G
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
dB
f/Hz
B3_B1(CLK)
A3_A2(RST)
C3_C1(DAT)
Filtering behavior
EMIF03-SIM01
3/11
ESD response to IEC61000-4-2 (15kV air discharge)
10
15
20
25
30
35
0
1
2
3
4
5
6
F=1MHz
Vosc =30mV
VR(V)
C(pF)
Capacitance versus reverse applied voltage.
Symbol
Parameter and test conditions
Value
Unit
V
PP
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
15
8
kV
T
j
Junction temperature
125
C
T
op
Operating temperature range
-40 to + 85
C
T
stg
Storage temperature range
-55 to +150
C
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25 C)
Positive surge
Negative surge
EMIF03-SIM01
4/11
Symbol
Test conditions
Min.
Typ.
Max.
Unit
V
BR
I
R
= 1 mA
6
V
I
RM
V
RM
= 3V
1
A
R
d
1.5
R
1
95
100
105
R
2
44.65
47
49.35
R
3
95
100
105
C
line
@ 0V
35
pF
Symbol
Parameter
V
BR
Breakdown voltage
I
RM
Leakage current @ V
RM
V
RM
Stand-off voltage
V
CL
Clamping voltage
Rd
Dynamic impedance
I
PP
Peak pulse current
ELECTRICAL CHARACTERISTICS (T
amb
= 25 C)
TECHNICAL INFORMATION
The EMIF03-SIM01 is firstly designed as an EMI
/ RFI filter. This low-pass filter is characterized
by the following parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
Figure A1shows that attenuation is better than
-20dB at mobile phone frequencies (800MHz to
2.5GHz).
FREQUENCY BEHAVIOR
Aplac 7.60 User: STMicroelectronics Feb 22 2001
100.0k
1.0M
10.0M
100.0M
1.0G
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
dB
f/Hz
B3_B1(CLK)
A3_A2(RST)
C3_C1(DAT)
Fig. A1: Frequency response curve
EMIF03-SIM01
5/11
TEST BOARD
EMI03
SIM01
50
Vg
50
Fig. A2: Measurements conditions
In addition with the filtering the EMIF03-SIM01 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at:
V
V
R I
cl
br
d
pp
=
+
This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the
first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R.
Such a configuration makes the output voltage very low at the Vout level.
ESD PROTECTION
EMIF03-SIM01
S1
R = 100
or 47
S2
Rg
Rd
Rd
V
BR
V
BR
Vg
R load
ESD Surge
Device
to be
protected
Vin
Vout
Fig. A3: ESD clamping behavior
EMIF03-SIM01
6/11
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and
Rload>>Rd, it gives these formulas:
Vinput
R V
R V
R
g
br
d
g
g
=
+
Voutput
R V
R V
R
br
d
in
=
+
The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV,
Rg=330
) and Vbr=7V (typ.) give:
Vinput = 43.36V
Voutput = 7.65V (R = 100
)
8.38V (R = 47
)
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low
current involved after the series resistance R.
The early ageing and destruction of IC's is often due to latch-up phenomena which mainly induced by
dV/dt. Thanks to its RC structure, the EMIF03-SIM01 provides a high immunity to latch-up by integration of
fast edges. (Please refer to the response of the EMIF03-SIM01 to a 30 ns edge on Fig. A9)
The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD
protection :
- almost no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to Vbr for positive surge and close to ground for negative one
LATCH-UP PHENOMENA
TEST BOARD
EMI03
SIM01
V(in)
V(out)
Fig. A4: Measurements conditions
EMIF03-SIM01
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Fig. A5: Remaining voltage at both stages S1 (Vin1) and S2 (Vout1) during ESD surge
Please note that the EMIF03-SIM01 is not only acting for positive ESD surges but also for negative ones.
For negatives surges, it clamps close to ground voltage as shown in Fig. A5b.
Note: Dynamic resistance measurements
t
t
I
I
PP
2s
2.5 s
2.5 s duration measurement wave
Fig. A6: Rd measurement current wave
As the value of the dynamic resistance remains
stable for a surge duration lower than 20s, the
2.5s rectangular surge is well adapted. In
addition both rise and fall times are optimized to
avoid any parasitic phenomenon during the
measurement of Rd
a: Positive Surge
b: Negative Surge
8/11
EMIF03-SIM01
CROSSTALK BEHAVIOR
Fig. A7: Crosstalk phenomena
R
L1
R
L2
1
G1
12
G2
V
+
V
2
G2
21
G1
V
+
V
Line 1
Line 2
V
G1
V
G2
DRIVERS
RECEIVERS
R
G1
R
G2
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (
12 or
21 )
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load R
L2
is
2V
G2
, in fact the real voltage at this point has got an extra value
21
V
G1
. This part of the V
G1
signal represents the effect of the crosstalk phenomenon of the line 1 on
the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or
high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works
with low voltage signal or high load impedance (few k
).
1- Digital crosstalk
Fig. A8: Digital crosstalk measurements
+3V
+3V
74HC04
+3V
Square
Pulse
Generator
74HC04
V
G1
21
G1
V
B1
C1
B3
C3
EMI35
SIM01
Square pulse generator
s
frequency = 3.3MHz
s
0 - 3.3V
s
Risetime = 30ns
EMIF03-SIM01
9/11
Fig. A9: Digital crosstalk results
50
Vg
in1
TEST BOARD
out1
50
EMI35
SIM01
Fig. A10: Analog crosstalk phenomena
2- Analog crosstalk
Digital crosstalk is less than 2 mV peak to peak
EMIF03-SIM01
10/11
100.0k
1.0M
10.0M
100.0M
1.0G
-100.0
-90.00
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
dB
f/Hz
Aplac 7.60 User: STMicroelectronics Feb 22 2001
B3_C1
Fig. A11: Analog crosstalk results
EMIF 03
SIM 01
-
Electro Magnetic
Interference Filter
Nb of lines
SIM Card protection
Version number
ORDER CODE
Figure A10 gives the measurement circuit for the analog application. In Figure A11, the curve shows the
EMIF03-SIM01 provides a crosstalk immunity better than - 20dB up to 3GHz.
500m 50
315m 50
1.57mm 50m
1.57mm 50m
650m 65
PACKAGE MECHANICAL DATA
(all dimensions in m)
s
Bottom side (ball view): Pin A1 missing for die orientation
s
Top side (balls underweath): see the marking .
EMIF03-SIM01
11/11
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-
proval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - Printed in Italy - All rights reserved.
STMicroelectronics GROUP OF COMPANIES
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http://www.st.com
365
1570
1570
diam 230
365
220
200
FCT
YWW
MARKING and DIE SIZE (typical values)
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
EMIF03-SIM01
FCT
Flip Chip
3.3 mg
5000
Tape & reel 7"
PACKING
YWW: Date code (year + week code)
Note: More packing information are available in the application note AN1235: "Flip-Chip: Package
description and recommendations for use"
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