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ESDA6V1-4F1
QUAD TRANSILTM ARRAY
FOR ESD PROTECTION
The ESDA6V1-4F1 is a 4-bit wide monolithic
suppressor designed to protect against ESD
components which are connected to data and
transmission lines.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode
forward voltage drop below ground for negative
transients.
DESCRIPTION
July 2002 - Ed: 2A
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
s
Computers
s
Printers
s
Communication systems
s
GSM handsets and accessories
s
Other telephone sets
s
Set top boxes
APPLICATIONS
3
2
1
A
B
Z1
Z2
GND
GND
Z3
Z4
Flip Chip
(Bump side)
A1
A2
A3
B3
B2
B1
FUNCTIONAL DIAGRAM
A.S.D.TM
s
> 15kV ESD Protection
s
High integration
s
Suitable for high density boards
BENEFITS
- IEC61000-4-2: Level 4
15 kV
(air discharge)
8 kV
(contact discharge)
- MIL STD 883E-Method 3015-6: class3
(Human body model)
COMPLIES
WITH
THE
FOLLOWING
STAN-
DARDS:
s
4 Unirectional transil functions
s
Breakdown voltage: V
BR
= 6.1Vmin
s
Low leakage current < 10
A
s
Very low PCB space consuming
FEATURES
ESD RESPONSE TO IEC61000-4-2
(air discharge 16kV, positive surge)
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ESDA6V1-4F1
Symbol
Test conditions
Value
Unit
V
PP
ESD discharge - MIL STD 883E - Method 3015-6
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
15
8
kV
P
PP
Peak pulse power (8/20
s)
150
W
T
j
Junction temperature
150
C
T
stg
Storage temperature range
-55 to +150
C
T
L
Lead solder temperature (10 seconds duration)
260
C
T
op
Operating temperature range
-40 to +85
C
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25C)
Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
T
Voltage temperature coefficient
C
Capacitance per line
Rd
Dynamic impedance
V
F
Forward voltage drop
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
V
I
Slope = 1/Rd
V
CL
V
BR
V
RM
I
PP
I
RM
I
R
Type
V
BR
@
I
R
I
RM
@ V
RM
Rd
T
C
min.
max.
max.
typ.
max
max
note 1
note 2
0V bias
V
V
mA
A
V
m
10
-4
/C
pF
ESDA6V1- 4F1
6.1
7.2
1
10
5
350
6
250
Note 1: Square pulse IPP = 15A, tp = 2.5s
Note 2:
VBR =
T * (Tamb - 25) * VBR(25C)
ESDA6V1-4F1
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0
25
50
75
100
125
150
175
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Tj initial(C)
Ppp[Tj initial]/Ppp[Tj initial=25C]
Fig. 1: Peak power dissipation versus initial junc-
tion temperature
1
10
100
10
100
1000
tp(s)
Ppp(W)
Fig. 2: Peak pulse power versus exponential pulse
duration (Tj initial = 25C)
0
5
10
15
20
25
30
0.1
1.0
10.0
50.0
Vcl(V)
Ipp(A)
tp = 2.5s
Fig. 3: Clamping voltage versus peak pulse current
(Tj initial = 25C). Rectangular waveform t
P
= 2.5s.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
75
100
125
150
175
200
225
250
VR(V)
C(pF)
F=1MHz
Vosc=30mV
Fig. 4: Capacitance versus reverse applied voltage
(typical values).
25
50
75
100
125
150
1.0
1.2
1.4
1.6
1.8
Tj(C)
IR[Tj] / IR[Tj=25C]
Fig. 5: Relative variation of leakage current versus
junction temperature (typical values).
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ESDA6V1-4F1
As the value of the dynamic resistance remains stable for a surge duration lower than 20s, the 2.5s
rectangular surge is well adapted. In addition both rise and fall times are optimised to avoid any parasitic
phenomenon during the measurement of Rd.
The ESDA6V1-4F1 has been designed to clamp fast spikes like ESD. Generally the PCB designers need
to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the
classical parameters.
The voltage across the protection cell can be calculated with the following formula:
V
V
R
I
CL
BR
d
PP
=
+
Where IPP is the peak current through the ESDA cell.
USE OF THE DYNAMIC RESISTANCE
CALCULATION OF THE CLAMPING VOLTAGE
The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the
classical 8/20 s and 10/1000 s surges
DYNAMIC RESISTANCE MEASUREMENT
t
t
I
I
PP
2s
2.5 s
2.5 s duration measurement wave
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice
for minimal lead inductance. They serve as parallel protection elements, connected between the signal line
to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low
impedance path diverting the transient current to ground.
ESD PROTECTION WITH ESDA6V1-4F1
ESDA6V1-4F1
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Connector
IC
to
be
pr
otected
ESDA6V1-4F1
The ESDA6V1-4F1 array is the ideal product for use as board level protection of ESD sensitive
semiconductor components.
The Flip Chip package makes the ESDA6V1-4F1 device some of the smallest ESD protection devices
available. It also allows design flexibility in the design of "crowded" boards where the space saving is at a
premium. This enables to shorten the routing and can contribute to improved ESD performance.
500m
500m
=340m min (for 300m
pad
Non Solder mask opening
Copper Pad
Cu - Ni (2-6m) - Au (0.2m max)
= 250m (300m max)
=320m max (stencil aperture)
Solder paste
Stencil Design
thickness of 150m
500m
LAYOUT RECOMMENDATIONS
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
s
The ESDA6V1-4F1 should be placed as close as possible to the input terminals or connectors.
s
Minimise the path length between the ESD suppressor and the protected device
s
Minimise all conductive loops, including power and ground loops
s
The ESD transient return path to ground should be kept as short as possible.
s
Use ground planes whenever possible.
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