1/6
ESDA6V1BC6
QUAD BIDIRECTIONAL TRANSIL
SUPPRESSOR FOR ESD PROTECTION
DESCRIPTION
The ESDA6V1BC6 is a monolithic array designed
to protect up to 4 lines in a bidirectional way
against ESD transients.
The device is ideal for situations where board
space is at a premium.
January 2002 - Ed: 1C
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
s
COMPUTERS
s
PRINTERS
s
COMMUNICATION SYSTEMS
s
VIDEO EQUIPMENT
This device is particularly adapted to the protection
of symmetrical signals.
APPLICATIONS
SOT23-6L (SC-74)
FUNCTIONAL DIAGRAM
SOT23-6L
Application Specific Di
scretes
A.S.D.
BENEFITS
s
High ESD protection level : up to 25 kV
s
High integration
s
Suitable for high density boards
- IEC61000-4-2: 15 kV (air discharge)
8 kV
(contact discharge)
- MIL STD 883C-Method 3015-6: class3
(human body model)
COMPLIES WITH THE FOLLOWING STANDARDS:
s
4 BIDIRECTIONAL TRANSIL FUNCTIONS
s
ESD PROTECTION FOR DATA, SIGNAL AND
V
CC
BUS
s
STAND OFF VOLTAGE RANGE:
5 V MIN.
s
LOW LEAKAGE CURRENT < 1
A
s
PEAK PULSE POWER ( 8/20 ) = 80W
FEATURES
1
2
3
6
5
4
ESDA6V1BC6
2/6
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the
transient current to ground.
1. ESD protection by ESDA6V1BC6
CONNECTOR
DRIVER
Bidirectional protection for 0V biased signals.
The ESDA6V1BC6 array is the ideal product for use as board level protection of ESD sensitive
semiconductor components.
The tiny SOT23-6L package allows design flexibility in the design of "crowded" boards where the space
saving is at a premium. This enables to shorten the routing and can contribute to improve ESD
performance.
2. Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
s
The ESDA6V1BC6 should be placed as near as possible to the input terminals or connectors.
s
Minimise the path length between the ESD suppressor and the protected device
s
Minimise all conductive loops, including power and ground loops
s
The ESD transient return path to ground should be kept as short as possible.
s
Use ground planes whenever possible.
ESDA6V1BC6
3/6
Symbol
Test conditions
Value
Unit
V
PP
ESD discharge - MIL STD 883C - Method 3015-6
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
15
8
kV
P
PP
Peak pulse power (8/20
s)
80
W
T
j
Junction temperature
150
C
T
stg
Storage temperature range
-55 to +150
C
T
L
Lead solder temperature (10 second duration)
260
C
T
op
Operating temperature range (note 1)
-40 to +125
C
Note 1: Variation of parameters is given by curves.
ABSOLUTE MAXIMUM RATINGS (T
amb
= 25C)
I
V
V
BR
CL
VRM
I PP
I RM
V
Rd
Type
V
BR
@
I
R
I
RM
@ V
RM
Rd
T
C
min.
max.
max.
typ.
max.
typ.
note 1
0V bias
V
V
mA
A
V
10
-4
/C
pF
ESDA6V1BC6
6.1
8
1
1
5
1.35
3
20
Note 1 : Square pulse, Ipp = 3A, tp=2.5
s.
Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
CL
Clamping voltage
I
RM
Leakage current
I
PP
Peak pulse current
C
Capacitance
Rd
Dynamic resistance
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
ESDA6V1BC6
4/6
0
25
50
75
100
125
150
175
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Tj initial(C)
Ppp[Tj initial]/Ppp[Tj initial=25C]
Fig. 1: Peak power dissipation versus initial
junction temperature.
1
10
100
10
100
500
tp(s)
Ppp(W)
Fig. 2: Peak pulse power versus exponential pulse
duration (Tj initial = 25 C).
0
5
10
15
20
25
30
35
40
0.1
1.0
10.0
20.0
Vcl(V)
Ipp(A)
tp=2.5s
Fig. 3: Clamping voltage versus peak pulse
current (Tj initial = 25 C).
Rectangular waveform tp = 2.5
s.
0
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
VR(V)
C(pF)
F=1MHz
Vosc=30mV
Fig. 4: Capacitance versus reverse applied
voltage (typical values).
25
50
75
100
125
150
1
10
100
500
Tj(C)
IR[Tj] / IR[Tj=25C]
Fig. 5: Relative variation of leakage current versus
junction temperature (typical values).
ESDA6V1BC6
5/6
PACKAGE MECHANICAL DATA
SOT23-6L
mm
inch
3.50
0.138
0.60
0.024
1.20
0.047
1.10
0.043
0.95
0.037
2.30
0.090
FOOTPRINT
A2
A
L
H
b
E
D
e
e
A1
C
REF.
DIMENSIONS
Millimeters
Inches
Min.
Typ. Max.
Min.
Typ. Max.
A
0.90
1.45 0.035
0.057
A1
0
0.10
0
0.004
A2
0.90
1.30 0.035
0.0512
b
0.35
0.50 0.0137
0.02
c
0.09
0.20 0.004
0.008
D
2.80
3.00
0.11
0.118
E
1.50
1.75 0.059
0.0689
e
0.95
0.0374
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
10
10
ESDA 6V1 B C6
V
min.
BR
Bidirectional
ESD ARRAY
PACKAGE:
C6: SOT23-6L (SC-74)
ORDER CODE
Type
Marking
ESDA6V1BC6
BS55
Packaging: Standard packaging is tape and reel.
MARKING
PDF 
ZIP