ETC5064/64-X
ETC5067/67-X

November 1994

POWER AMPLIFIER

SERIAL INTERFACE CODEC/FILTER WITH RECEIVE

ORDERING NUMBERS:

ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X

COMPLETE CODEC AND FILTERING SYS-
TEM INCLUDING :

Transmit high-pass and low-pass filtering.

Receive low-pass filter with sin x/x correction.

Active RC noise filter.

-law or A-law compatible CODER and DE-

CODER.

Internal precision voltage reference.

Serial I/O interface.

Internal auto-zero circuitry.

Receive push-pull power amplifiers.

-LAW ETC5064

A-LAW ETC5067

MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.

5 V OPERATION.

LOW OPERATING POWER-TYPICALLY 70 mW

POWER-DOWN STANDBY MODE-TYPICALLY
3 mW

AUTOMATIC POWER DOWN

TTL OR CMOS COMPATIBLE DIGITAL INTER-
FACES

MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY

C TO 70

C OPERATION: ETC5064/67

C TO 85

C OPERATION: ETC5064-X/67-X

DESCRIPTION

The ETC5064 (

-law), ETC5067 (A-law) are mono-

lithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architectureshown in the Block Dia-
grams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.

Similar to the ETC505X family, these devices fea-
ture an additional Receive Power Amplifier to pro-
vide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two ex-
ternal resistors for an output level of up to

6.6 V

across a balanced 600

load.

Also included is an Analog Loopback switch and
TS

output.

DIP20

(Plastic) N

PL CC20

SO 20

ORDERING NUMBERS:

ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X

ORDERING NUMBERS:

ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X

1/18

PIN DESCRIPTION

Name

Pi n

Type (*)

Description

VPO

The Non-inverting Output of the Receive Power Amplifier

GNDA

GND

Analog Ground. All signals are referenced to this pin.

VPO

The Inverting Output of the Receive Power Amplifier

VPI

Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to V

Analog Output of the Receive Filter.

Positive Power Supply Pin. V

= +5V

Receive Frame Sync Pulse which enable BCLK

to shift PCM data into

. FS

is an 8KHz pulse train. See figures 1 and 2 for timing details.

Receive Data Input. PCM data is shifted into D

following the FS

leading

edge

BCLK

/CLKSEL

The bit Clock which shifts data into D

after the FS

leading edge. May

vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLK

is used

for both transmit and receive directions (see table 1). This input has an
internal pull-up.

MCKL

/PDN

Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK

, but should be synchronous with MCLK

for

best performance. When MCLK

is connected continuously low, MCLK

selected for all internal timing. When MCLK

is connected continuously

high, the device is powered down.

MCLK

Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK

BCLK

The bit clock which shifts out the PCM data on D

. May vary from 64KHz

to 2.048MHz, but must be synchronous with MCLK

The TRI-STAT E

PCM data output which is enabled by FS

Transmit frame sync pulse input which enables BCLK

to shift out the

PCM data on D

. FS

is an 8KHz pulse train. See figures 1 and 2 for

timing details.

Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.

ANLB

Analog Loopback Control Input. Must be set to logic '0' for normal
operation. When pulled to logic '1', the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO

output of the receive power amplifier.

Analog output of the transmit input amplifier. Used to set gain externally.

Inverting input of the transmit input amplifier.

Non-inverting input of the transmit input amplifier.

Negative Power Supply Pin. V

= -5V

(*) I: Input, O: Output, S: Power Supply.
TRI- STATE

is a trademark of National Semiconductor Corp.

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

3/18

FUNCTIONAL DESCRIPTION

POWER-UP

When power is first applied, power-on reset circuitry
initializes the device and places it into the power-
down mode. All non-essential circuits are deacti-
vated and the D

and VF

O outputs are put in high

impedancestates. To power-up the device, a logical
low level or clock must be applied to the
MCLK

/PDN pin and FS

and/or FS

pulses must

be present. Thus 2 power-down control modes are
available. The first is to pull the MCLK

/PDN pin

high; the alternative is to hold both FS

and FS

in-

puts continuously low. The device will power-down
approximately 2 ms after the last FS

pulse. The

TRI-STATE PCM data output, D

, will remain in the

high impedance state until the second FS

pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock
and bit clock should be used for both the transmit
and receive directions. In this mode, a clock must be
applied to MCLK

and the MCLK

/PDN pin can be

used as a power-down control. A low level on
MCLK

/PDN powers up the device and a high level

powers down the device. In either case, MCLKX will
be selected as the master clock for both the transmit
and receive circuits. A bit clock must also be applied
to BCLK

and the BCL

/CLKSEL can be used to se-

lect the proper internal divider for a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automatically compen-
sates for the 193 rd clock pulse each frame.

With a fixed level on the BCLK

/CKSEL pin, BCLK

will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the fre-
quencies of operation which can be selected, de-
pending on the state of BCLK

/CLKSEL. In this syn-

chronous mode, the bit clock, BCLK

, may be from

64 kHz to 2.048 MHz, but must be synchronouswith
MCLK

Each FS

pulse begins the encoding cycle and the

PCM data from the previous encode cycle is shift out
of the enabled D

output on the positive edge of

BCLK

. After 8 bit clock periods, the TRISTATE D

output is returned to a high impedance state. With an
FS

pulse, PCM data is latched via the D

input on

the negativeedge of BCLK

(or on BCKL

if running).

and FS

must be synchronous with MCLKX/

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and
receive clocks may be applied. MCLK

and MCLK

must be 2.048 MHz for the ETC5067 or 1.536 MHz,
1.544 MHz for the ETC5064, and need not be syn-
chronous. For best transmission performance, how-
ever, MCLK

should be synchronouswith MCLK

which is easily achieved by applyingonly static logic
levels to the MCLK

/PDN pin. This will automatically

connectMCLK

to all internal MCLK

functions(see

pin description). For 1.544 MHz operation, the de-
vice automatically compensates for the 193rd clock
pulse each frame. FS

starts each encoding cycle

and must be synchronous with MCLK

and BCLK

starts each decoding cycle and must be syn-

chronous with BCLK

. BCLK

must be a clock, the

logic levels shown in Table 1 are not valid in asyn-
chronous mode. BCLK

and BCLK

may operate

from 64kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The device can utilize either a short frame sync
pulse or a long frame sync pulse.Upon power initiali-
zation, the device assumes a short frame mode. In
this mode, both frame sync pulses. FS

and FS

must be one bit clock period long, with timing rela-
tionships specified in figure 2. With FS

high during

a falling edge of BCLK

, the next rising edge of

BCLK

enables the D

TRI-STATE output buffer,

which will output the sign bit. The following seven ris-
ing edges clock out the remaining seven bits, and
the next falling edge disables the D

output. With

high during a falling edge of BCLK

(BCLK

synchronous mode), the next falling edge of BCLK

latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both de-
vices may utilize the short frame sync pulse in syn-
chronous or asynchronous operating mode.

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync
pulses, FS

and FS

, must be three or more bit clock

periods long, with timing relationships specified in
figure 3. Based on the transmit frame sync FS

, the

device will sense whether short or long frame sync

Table 1: Selection of Master Clock Frequencies.

BCLKR/CLKSEL

Master Clock

Frequency Selected

ETC5067

ETC5067-X

ETC5064

ETC5064-X

Clocked

2.048MHz

1.536MHz or

1.544MHz

1.536MHz or

1.544MHz

2.048MHz

1 (or open circuit)

2.048MHz

1.536MHz or

1.544MHz

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

4/18

pulses are being used. For 64 kHz operation, the
frame sync pulses must be kept low for a minimum
of 160 ns (see Fig 1). The D

TRI-STATE output

buffer is enabled with the rising edge of FS

or the

rising edge of BCLK

, whichever comes later, and

the first bit clocked out is the sign bit. The following
seven BCLK

rising edges clock out the remaining

seven bits. The D

output is disabled by the falling

BCLK

edge following the eighth rising edge, or by

going low, whichever comes later. A rising edge

on the receive frame sync pulse, FS

, will cause the

PCM data at D

to be latched in on the next eight

falling edges of BCLK

(BCLK

in synchronous

mode). Both devices may utilize the long frame sync
pulse in synchronous or asynchronous mode.

TRANSMIT SECTION

The transmit section input is an operational amplifier
with provision for gain adjustment using two external
resistors, see figure 4. The low noiseand wide band-
width allow gains in excess of 20 dB across the
audio passband to be realized. The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encoder sample-
and-hold circuit. The A/D is of companding type ac-
cording to A-law (ETC5067 and ETC5067-X) or

law (ETC5064 and ETC5064-X) coding conven-
tions. A precision voltage reference is trimmed in
manufacturing to provide an input over load (t

MAX

)

of nominally 2.5V peak (see table of Transmission
Characteristics). The FS

frame sync pulse controls

the sampling of the filer output,and then the succes-
sive-approximationencodingcycle begins.The 8-bit
code is then loaded into a buffer and shifted out
throughD

at the next FS

pulse. the total encoding

delay will be approximately 165

s (due to the trans-

mit filter) plus 125

s (due to encoding delay), which

totals 290

s. Any offset voltage due to the filters or

comparator is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consist of an expanding DAC
which drives a fifth order switched-capacitor low
pass filter clocked at 256kHz. The decoder is A-law
(ETC5067 and ETC5067-X) or

law (ETC5064

and ETC5064-X) and the 5 th order low pass filter
corrects for the sin x/x attenuation due to the 8kHz
sample and hold. The filter is then followed by a 2
nd order RC active post-filter and power amplifier
capable of driving a 600

load to a level of 7.2dBm.

The receive section is unity-gain. Upon the oc-
curence of FS

, the data at the D

input is clocked

in on the falling edge of the next eight BCLK

(BCKL

) periods.At the end of the decoder time slot,

the decoding cycle begins, and 10

s later the de-

coder DAC output is updated.The total decoder de-
lay is about10

s (decoder up-date) plus 110

s (fil-

ter delay) plus 62.5

s (1/2 frame), which gives ap-

proximately 180

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided
for directly driving a matched line interface trans-
former. The gain of the first power amplifier can be
adjusted to boost the

2.5V peak output signal from

the receive filter up

3.3V peak into an unbalanced

300

load, or

4.0V into an unbalanced15k

load.

The second power amplifier is internally connected
in unity-gain inverting mode to give 6dB of signal
gain for balanced loads. Maximum power transfer to
a 600

subscriber line termination is obtained by

differientially driving a balanced transformer with a

: 1 turns ratio, as shown in figure 4. A total peak

power of 15.6dBm can be delivered to the load plus
termination. Both power amplifier can be powered
down independentlyfrom the PDN input by connect-
ing the VPI input to V

saving approximately 12

mW of power.

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Valu e

Un it

to GNDA

-7

, V

OUT

Voltage at any Analog Input or Output

+0.3 to V

-0.3

Voltage at any Digital Input or Output

+0.3 to GNDA -0.3

oper

Operating Temperature Range: ETC5064/67

ETC5064-X/67-X

-25 to +125
-40 to +125

stg

Storage Temperature Range

-65 to +150

Lead Temperature (soldering, 10 seconds)

300

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

5/18

ELECTRICAL OPERATING CHARACTERISTICS
V

= 5.0V

5%, V

= -5V

5%, GNDA = 0V, T

= 0

C to 70

C (ETC5064-X/67-X: T

= 40

C to 85

), unless

otherwise noted; typical characteristics specified at V

= 5.0V, V

=-5.0V, T

= 25

C; all signals are refer-

enced to GNDA.
DIGITAL INTERFACE (All devices)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Input Low Voltage

0.6

Input High Voltage

2.2

Output Low Voltage
I

= 3.2 mA

= 3.2 mA, Open Drain

0.4
0.4

V
V

Output High Voltage
IH = 3.2 mA

2.4

Input Low Current (GNDA

)all digital inputs

Except BCLK

Input High Current (V

) Except ANLB

Output Current in High Impedance State (TRI-STAT E)
(GNDA

)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Input Leakage Current

VFxI

or VFxI

( 2.5 V

+ 2.5 V)

200

Input Resistance

or VF

( 2.5 V

+ 2.5 V)

Output Resistance (closed loop, unity gain)

Load Resistance

Load Capacitance

Output Dynamic Range (R

10 k

)

2.8

+2.8

Voltage Gain (VF

to GS

)

5000

V/V

Unity Gain Bandwidth

MHz

Offset Voltage

Common-mode Voltage

2.5

CMRRXA

Common-mode Rejection Ratio

PSRRXA

Power Supply Rejection Ratio

ANALOG INTERFACE WITH RECEIVE FILTER (all devices)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Output Resistance

Load Resistance (VF

O =

2.5 V)

Load Capacitance

VOS

Output DC Offset Voltage

200

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

6/18

ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)

Symbol

Parameter

Min.

Typ.

Max.

Unit

IPI

Input Leakage Current ( 1.0 V

VPI

1.0 V)

100

RIPI

Input Resistance ( 1.0

VPI

1.0 V)

VIOS

Input Offset Voltage

ROP

Output Resistance (inverting unitygain at VPO

or VPO

)

Unitygain Bandwidth, Open Loop (VPO

)

400

kHz

Load Capacitance (VPO

or VPO

to GNDA)

1500

= 600

= 300

100
500

1000

GAp

Gain VPO

to VPO

to GNDA, Level at VPO

= 1. 77 Vrms

(+ 3 dBmO)

V/V

PSRRp

Power Supply Rejection of V

or V

(VPO

connected to VPI)

0 kHz 4 kHz
0 kHz 50 kHz

60
36

POWER DISSIPATION (all devices)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Power-down Current at ETC6064/67

ETC5064-X/67-X

0.5
0.5

1.5

mA
mA

Power-down Current at ETC6064/67

ETC5064-X/67-X

0.05
0.05

0.3
0.4

mA
mA

Active Current at ETC6064/67

ETC5064-X/67-X

7.0
7.0

10.0
12.0

mA
mA

Active Current at ETC6064/67

ETC5064-X/67-X

7.0
7.0

10.0
12.0

mA
mA

ELECTRICAL OPERATING CHARACTERISTICS (Continued)

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

7/18

All TIMING SPECIFICATIONS

Symbol

Parameter

Min.

Typ.

Max.

Unit

1/t

Frequency of master clocks
MCLK

and MCLK

Depends on the device used and the
BCLK

/CLKSEL Pin

1.536
2.048

1.544

MHz

WMH

Width of Master Clock High

MCLK

and MCLK

160

WML

Width of Master Clock Low

MCLK

and MCLK

160

Rise Time of Master Clock

MCLK

and MCLK

Fall Time of Master Clock

MCLK

and MCLK

Period of Bit Clock

485

488

15.725

WBH

Width of Bit Clock High (V

= 2.2 V)

160

WBL

Width of Bit Clock Low (V

= 0.6 V)

160

Rise Time of Bit Clock (t

= 488 ns)

Fall Time of Bit Clock (t

= 488 ns)

SBFM

Set-up time from BCLK

high to MCLK

falling edge.

(first bit clock after the leading edge of FS

)

100

HBF

Holding Time from Bit Clock Low to the Frame Sync
(long frame only)

SFB

Set-up Time from Frame Sync to Bit Clock (long frame only)

HBFI

Hold Time from 3rd Period of Bit Clock

or FS

Low to Frame Sync (long frame only)

100

DZF

Delay Time to valid data from FS

or BCLK

, whichever

comes later and delay time from FSX to data output disabled
(C

= 0 pF to 150 pF)

165

DBD

Delay Time from BCLK

high to data valid

(load = 150 pF plus 2 LSTTL loads)

150

DZC

Delay Time from BCLK

low to data output disabled

165

SDB

Set-up Time from D

valid to BCLK

R/X

low

HBD

Hold Time from BCLK

R/X

low to D

invalid

HOLD

Holding Time from Bit Clock High to Frame Sync (short frame only)

Set-up Time from FS

X/R

to BCLK

X/R

Low

(short frame sync pulse) - Note 1

Hold Time from BCLK

X/R

Low to FS

X/R

Low

(short frame sync pulse) - Note 1

100

XDP

Delay Time to TS

low (load = 150 pF plus 2 LSTTI loads)

140

WFL

Minimum Width of the Frame Sync Pulse (low level)
(64 bit/s operating mode)

160

Note : 1.For short frame sync timing. FS

and FS

must go high while their respective bit clocks are

high.

Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

8/18

TRANSMISSION CHARACTERISTICS
(all devices) T

= 0

C to 70

C (ETC5064-X/67-X: T

= 40

C to 85

), V

= 5V

5%, V

= 5V

5%,

GNDA = 0V, f = 1.02kHz, V

= 0dBm0 transmit input amplifier connected for unitygainnoninverting.(unless

otherwise specified).

AMPLITUDE RESPONSE

Symbo l

Parameter

Min.

T yp.

Max.

Unit

Absolute Levels - Nominal 0 dBm0 is 4 dBm (600

0 dBm0

1.2276

Vrms

MAX

Max Overload Level

3.14 dBm0

ETC5067

3.17 dBm0

ETC5064

2.492
2.501

VPK

Transmit Gain, Absolute (T

= 25

C, V

= 5V, V

= -5V)

Input at GS

= 0dBm0 at 1020Hz

-0.15

0.15

GXR

Transmit Gain, Relative to GXA
f = 16Hz
f = 50Hz
f = 60Hz
f = 180Hz
f = 200Hz
f = 300Hz -3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz
f = 4600Hz and up, measure response from oHz to 4000Hz

-
-
-

-2.8
-1.8

-0.15
-0.35
-0.35

-0.7

-40
-30
-26

-0.2
-0.1

0.15
0.20
0.05

-14
-32

XAT

Absolute Transmit Gain Variation with Temperature
T

= 0

C to +70

= 40

C to +85

C (ETC5064-X/67-X)

-0.1

-0.15

0.1

0.15

XAV

Absolute Transmit Gain Variation with Supply Voltage
(V

= 5V

5%, V

= -5V

5%)

-0.05

0.05

XRL

Transmit Gain Variation with Level
Sinusolidal Test Method Reference Level = -10dBm0
VF

= -40dBm0 to +3dBm0

= -50dBm0 to -40dBm0

= -55dBm0 to -50dBm0

-0.2
-0.4
-1.2

0.2
0.4
1.2

Receive Gain, Absolute (T

= 25

C, V

= 5V, V

= -5V)

Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz

-0.15

0.15

Receive Gain, Relative to G

f = 0Hz to 3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz

-0.15
-0.35
-0.35

-0.7

0.15
0.20
0.05

-14

RAT

Absolute Receive Gain Variation with Temeperature
T

= 0

C to +70

= 40

C to +85

C (ETC5064-X/67-X)

-0.1

-0.15

0.1

0.15

RAV

Absolute Receive Gain Variation with Supply Voltage
(V

= 5V

5%, V

= -5V

5%)

-0.05

0.05

RRL

Receive Gain Variation with Level
Sinusoidal Test Method; Reference Input PCM code
corresponds to an ideally encoded -10dBm0 signal
PCM level = -40dBm0 to +3dBm0
PCM level = -50dBm0 to -40dBm0
PCM level = -55dBm0 to -50dBm0

-0.2
-0.4
-1.2

0.2
0.4
1.2

Receive Filter Output at VF

O R

= 10K

-2.5

2.5

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

11/18

TRANSMISSION CHARACTERISTICS (continued).
ENVELOPE DELAY DISTORTION WITH FREQUENCY

Symbol

Parameter

Min.

Typ.

Max.

Unit

Transmit Delay, Absolute (f = 1600 Hz)

290

315

Transmit Delay, Relative to D

f = 500 Hz-600 Hz
f = 600 Hz-800 Hz
f = 800 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz

195
120

50
20
55
80

130

220
145

75
40
75

105
155

Receive Delay, Absolute (f = 1600 Hz)

180

200

Receive Delay, Relative to D

f = 500 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600 Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz

40
30

25
20

100
145

125
175

NOISE

Symbol

Parameter

Min.

Typ.

Max.

Unit

Transmit Noise, P Message (A-LAW, VF

= 0 V) Weighted

ETC5064
ETC5064-X

74
74

69
67

dBm0p
dBm0p

Receive Noise, P Message Weighted
(A-LAW, PCM Code Equals Positive Zero)

dBm0p

Transmit Noise, C Message Weighted
(

-LAW, VFxI

= 0 V)

ETC5064

ETC5064-X

12
12

15
16

dBrnC0
dBrnC0

Receive Noise, C Message Weighted
(

-LAW, PCM Code Equals Alternating Positive and Negative Zero)

dBrnC0

Noise, Single Frequency
f = 0 kHz to 100 kHz, Loop around Measurement, VF

= 0 V

dBm0

PPSR

Positive Power Supply Rejection, Transmit (note 2)
V

= 5.0 V

+ 100 mVrms, f = 0 kHz-50 kHz

dBp

NPSR

Negative Power Supply Rejection, Transmit (note 2)
V

= 5.0 V

+ 100 mVrms, f = 0 kHz-50 kHz

dBp

PPSR

Positive Power Supply Rejection, Receive (PCM code equals
positive zero, V

= 5.0 V

+ 100 mVrms)

f = 0 Hz-4000Hz

A LAW

LAW

f = 4 kHz-25 kHz
f = 25 kHz-50 kHz

40
40
40
36

dBp

dBc

dB
dB

NPSR

Negative Power Supply Rejection, Receive (PCM code equals
positive zero, V

= 5.0 V

+ 100 mVrms)

f = 0 Hz-4000Hz

A LAW

LAW

f = 4 kHz-25 kHz
f = 25 kHz-50 kHz

40
40
40
36

dBp

dBc

dB
dB

SOS

Spurious out-of-band Signals at the Channel Output
0 dBm0, 300 Hz-3400 Hz input PCM applied at D

4600 Hz-7600 Hz
7600 Hz-8400 Hz
8400 Hz-100,000 Hz

32
40
32

dB
dB
dB

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

12/18

TRANSMISSION CHARACTERISTICS (continued).

DISTORTION

Symbol

Parameter

Min.

Typ.

Max.

Unit

STD

Signal to Total Distortion (sinusoidal test method)

Transmit or Receive Half-channel
Level = 3.0 dBm0
= 0 dBm0 to 30 dBm0
= 40 dBm0

XMT

RCV

= 55 dBm0

XMT

RCV

33
36
29
30
14
15

dBp

(ALAW)

dBc

(

LAW)

SFD

Single Frequency Distortion, Transmit (T

= 25

SFD

Single Frequency Distortion, Receive (T

= 25

IMD

Intermodulation Distortion
Loop Around Measurement, VF

= 4 dBm0 to

21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz

CROSSTALK

Symbol

Parameter

Min.

Typ.

Max.

Unit

X-R

Transmit to Receive Crosstalk, 0dBm0 Transmit
f = 300 Hz-3400 Hz, D

= Steady PCM Code

ETC5064/67

ETC5064-X/67-X

75
65

dB
dB

R-X

Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2)
f = 300 Hz-3400 Hz, VF

I = 0 V

ETC5064/67

ETC5064-X/67-X

70
65

dB
dB

POWER AMPLIFIERS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Maximum 0 dBm0 Level for Better than

0.1 dB Linearity Over

the Range 10 dBm0 to + 3 dBm0
(balanced load, R

connected between VPO

and VPO

)

= 600

= 1200

= 30 k

3.5
4.0

Vrms

S/D

Signal/Distortion R

= 600

, 0 dBm0

Notes :

1. Measured by extrapolation from the distortion test results.
2. PPSRX, NPSRX, CTRX measured with a 50dBm0 activating signal applied at VF

ENCODING FORMAT AT D

OUTPUT

A-Law

(Including even bit inversion)

Law

(at GS

) = + Full-scale

1 0 1 0 1 0 1 0

1 0 0 0 0 0 0 0

(at GS

) = 0 V

1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1

(at GS

) = Full-scale

0 0 1 0 1 0 1 0

0 0 0 0 0 0 0 0

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

13/18

APPLICATION INFORMATION

POWER SUPPLIES

While the pins at the ETC506X family are well pro-
tected against electrical misure, it is recommended
that the standard CMOS practice be followed, en-
suring that ground is connected to the device before
any other connections are made. In applications
where the printed circuit board may be plugged into
a "hot" socket with power and clocks already pre-
sent, an extra long ground pin in the connector
should be used.

All ground connections to each device should meet
at a common point as close as possible to the GNDA
pin. This minimizes the interaction of ground return
currents flowing through a common bus impedance.
0.1

F supply decoupling capacitors should be con-

nected from this common ground point to VCC and
VBB as close to the device as possible.

For best performance, the ground point of each
CODEC/FILTER on a card should be connected to
a common card ground in star formation, rather than
via a ground bus. This common ground point should
be decoupled to VCC and VBB with 10

F capaci-

tors.

For best performance, TSx should be grounded if
not used.

Figure 4 : Typical Asynchronous Application.

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

14/18

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica-
tions mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information pre-
viously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

18/18

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ETC5064

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ETC5064