1/11
September 2001
s
MEDIUM SPEED OPERATION :
10 MHz (Typ.) at V
DD
= 10V
s
FULLY STATIC OPERATION
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
QUIESCENT CURRENT SPECIFIED UP TO
20V
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4017B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4017B is 5-stage Johnson counter
having 10 decoded outputs. Inputs include a
CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the clock input circuit
provides pulse shaping that allows unlimited clock
input pulse rise and fall times. This counter is
advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low.
Counter advanced via the clock line is inhibited
when the CLOCK INHIBIT signal is high. A high
RESET signal clears the counter to its zero count.
Use of the Johnson decade-counter configuration
permits high speed operation, 2-input decimal
decode gating and spike-free decoded outputs.
Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are
normally low and go high only at their respective
decoded time slot. Each decoded output remains
high for one full clock cycle. A CARRY - OUT
signal completes one cycle every 10 clock input
cycles and is used to ripple-clock the succeeding
device in a multi-device counting chain.
HCF4017B
DECADE COUNTER WITH 10 DECODED OUTPUTS
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF4017BEY
SOP
HCF4017BM1
HCF4017M013TR
DIP
SOP
HCF4017B
2/11
INPUT EQUIVALENT CIRCUIT
FUNCTIONAL DIAGRAM
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Qn : No Change
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
3, 2, 4, 7, 10,
1, 5, 6, 9, 11
0 to 9
Decoded Decimal Output
14
CLOCK
Clock Input
13
CLOCK
INHIBIT
Clock Inhibit Input
15
RESET
Reset Input
12
CARRY OUT Carry Output
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
CLOCK
CLOCK
INHIBIT
RESET
DECODED
OUTPUT
X
X
H
Q
0
L
X
L
Q
n
X
H
L
Q
n
L
L
Q
n+1
L
L
Q
n
H
L
Q
n
H
L
Q
n+1
HCF4017B
3/11
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
HCF4017B
4/11
DC SPECIFICATIONS
The Noise Margin for both "1" and "0" level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
Symbol
Parameter
Test Condition
Value
Unit
V
I
(V)
V
O
(V)
|I
O
|
(
A)
V
DD
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
I
L
Quiescent Current
0/5
5
0.04
5
150
150
A
0/10
10
0.04
10
300
300
0/15
15
0.04
20
600
600
0/20
20
0.08
100
3000
3000
V
OH
High Level Output
Voltage
0/5
<1
5
4.95
4.95
4.95
V
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
14.95
14.95
V
OL
Low Level Output
Voltage
5/0
<1
5
0.05
0.05
0.05
V
10/0
<1
10
0.05
0.05
0.05
15/0
<1
15
0.05
0.05
0.05
V
IH
High Level Input
Voltage
0.5/4.5
<1
5
3.5
3.5
3.5
V
1/9
<1
10
7
7
7
1.5/13.5
<1
15
11
11
11
V
IL
Low Level Input
Voltage
4.5/0.5
<1
5
1.5
1.5
1.5
V
9/1
<1
10
3
3
3
13.5/1.5
<1
15
4
4
4
I
OH
Output Drive
Current
0/5
2.5
<1
5
-1.36
-3.2
-1.1
-1.1
mA
0/5
4.6
<1
5
-0.44
-1
-0.36
-0.36
0/10
9.5
<1
10
-1.1
-2.6
-0.9
-0.9
0/15
13.5
<1
15
-3.0
-6.8
-2.4
-2.4
I
OL
Output Sink
Current
0/5
0.4
<1
5
0.44
1
0.36
0.36
mA
0/10
0.5
<1
10
1.1
2.6
0.9
0.9
0/15
1.5
<1
15
3.0
6.8
2.4
2.4
I
I
Input Leakage
Current
0/18
Any Input
18
10
-5
0.1
1
1
A
C
I
Input Capacitance
Any Input
5
7.5
pF
HCF4017B
5/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb
= 25C, C
L
= 50pF, R
L
= 200K
, t
r
= t
f
= 20 ns)
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/C.
(1) Measured with respect to carry out line.
Symbol
Parameter
Test Condition
Value (*)
Unit
V
DD
(V)
Min.
Typ.
Max.
CLOCKED OPERATION
t
PLH
t
PHL
Propagation Delay Time
(decode out)
5
325
650
ns
10
135
270
15
85
170
Propagation Delay Time
(carry out)
5
300
600
ns
10
125
250
15
80
160
t
THL
t
TLH
Transition Time (carry out
or decoded out lines)
5
100
200
ns
10
50
100
15
40
80
f
CL
(1)
Maximum Clock Input
Frequency
5
2.5
5
5
MHz
10
5
10
15
5.5
11
t
W
Minimum Clock Pulse
Width
5
100
200
ns
10
45
90
15
30
60
t
r
, t
f
Clock Input Rise or Fall
Time
5
unlimited
s
10
15
t
setup
Data Setup Time Minimum
Clock Inhibit
5
115
230
ns
10
50
100
15
35
75
RESET OPERATION
t
PLH,
t
PHL
Propagation Delay Time
(carry out or decoded out
lines)
5
265
530
ns
10
115
230
15
85
170
t
W
Minimum Reset Pulse
Width
5
130
260
ns
10
55
110
15
30
60
t
REM
Minimum Reset Removal
Time
5
200
400
ns
10
140
280
15
75
150
HCF4017B
6/11
TYPICAL APPLICATIONS
DIVIDE BY N COUNTER(N < 10) WITH
DECODED OUTPUTS
When the N
th
decoded output is reached (N
th
clock pulse) the S-R flip-flop (constructed from two
NOR gates of the HCF4001B) generates a reset
pulse which clears the HCF4017B to its zero
count. At this time, if the N
th
decoded output is
greater than or equal to 6, the C
OUT
line goes high
to clock the next HCF4017B counter section. The
"0" decoded output also goes high at this time.
Coincidence of the clock low and decoded "0"
output high resets the S-R flip-flop to enable the
HCF4017B. If the N
th
decoded output is less than
6, the COUT line will not go high and, therefore,
cannot be used. In this case "0" decoded output
may be used to perform the clocking function for
the next counter.
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 200K
R
T
= Z
OUT
of pulse generator (typically 50
)
HCF4017B
7/11
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2 : MINIMUM SETUP TIME (CLOCK INHIBIT TO CLOCK) (f=1MHz; 50% duty cycle)
HCF4017B
8/11
WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50% duty
cycle)
WAVEFORM 4 : MINIMUM SETUP TIME (CLOCK TO CLOCK INHIBIT) (f=1MHz; 50% duty cycle)
HCF4017B
9/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
a1
0.51
0.020
B
0.77
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
3.3
0.130
Z
1.27
0.050
Plastic DIP-16 (0.25) MECHANICAL DATA
P001C
HCF4017B
10/11
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
1.75
0.068
a1
0.1
0.2
0.003
0.007
a2
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
0.62
0.024
S
8 (max.)
SO-16 MECHANICAL DATA
PO13H
HCF4017B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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11/11
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