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September 2002
s
INDIVIDUAL CLOCK LINES FOR COUNTING
UP OR COUNTING DOWN
s
SYNCHRONOUS HIGH-SPEED CARRY AND
BORROW PROPAGATION DELAYS FOR
CASCADING
s
ASYNCHRONOUS RESET AND PRESET
CAPABILITY
s
MEDIUM-SPEED OPERATION - f
CL
= 8MHz
(typ.) AT 10 V
s
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s
QUIESCENT CURRENT SPECIF. UP TO 20V
s
5V, 10V AND 15V PARAMETRIC RATINGS
s
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25C
s
100% TESTED FOR QUIESCENT CURRENT
s
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40193B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40193B Presettable Binary Up/Down Counter
consists of 4 synchronously clocked, GATED "D"
type flip-flops connected as a counter. The inputs
consist of four individual jam lines, a PRESET
ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY
and BORROW outputs for multiple-stage counting
schemes are provided. The counter is cleared so
that all outputs are in a low state by a high on the
RESET line. A RESET is accomplished
asynchronously with the clock. Each output is
individually programmable asynchronously with
the clock to the level on the corresponding jam
input when the PRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP
line is high. The CARRY and BORROW signals
are high when the counter counts up or down. The
CARRY signal goes low one-half clock cycle after
the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low
HCF40193B
PRESETTABLE UP/DOWN COUNTERS
(DUAL CLOCK WITH RESET) BINARY TYPE
PIN CONNECTION
ORDER CODES
PACKAGE
TUBE
T & R
DIP
HCF40193BEY
SOP
HCF40193BM1
HCF40193M013TR
DIP
SOP
HCF40193B
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one-half clock cycle after the counter reaches its
minimum count in the count-down mode. The
cascading of multiple packages is easily
accomplished without the need for additional
external circuitry by tying the BORROW and
CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the following
package.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
3, 2, 6, 7
Q1 to Q4
Flip-Flop Outputs
4
CLOCK
DOWN
Clock Down Input
5
CLOCK UP
Clock Up Input
11
PRESET
ENABLE
Preset Enable Input
12
CARRY
Count Up (Carry)
13
BORROW
Count Down (Borrow)
14
RESET Reset
Input
15, 1, 10, 9
J1 to J4
Data Input
8
V
SS
Negative Supply Voltage
16
V
DD
Positive Supply Voltage
HCF40193B
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
-0.5 to +22
V
V
I
DC Input Voltage
-0.5 to V
DD
+ 0.5
V
I
I
DC Input Current
10
mA
P
D
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
T
op
Operating Temperature
-55 to +125
C
T
stg
Storage Temperature
-65 to +150
C
Symbol
Parameter
Value
Unit
V
DD
Supply Voltage
3 to 20
V
V
I
Input Voltage
0 to V
DD
V
T
op
Operating Temperature
-55 to 125
C
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